1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Armada AP806 System Controller
5 * Copyright (C) 2016 Marvell
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "ap806-system-controller: " fmt
13 #include "armada_ap_cp_helper.h"
14 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
21 #define AP806_SAR_REG 0x400
22 #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
24 #define AP806_CLK_NUM 5
26 static struct clk *ap806_clks[AP806_CLK_NUM];
28 static struct clk_onecell_data ap806_clk_data = {
30 .clk_num = AP806_CLK_NUM,
33 static int ap806_syscon_common_probe(struct platform_device *pdev,
34 struct device_node *syscon_node)
36 unsigned int freq_mode, cpuclk_freq;
37 const char *name, *fixedclk_name;
38 struct device *dev = &pdev->dev;
39 struct device_node *np = dev->of_node;
40 struct regmap *regmap;
44 regmap = syscon_node_to_regmap(syscon_node);
46 dev_err(dev, "cannot get regmap\n");
47 return PTR_ERR(regmap);
50 ret = regmap_read(regmap, AP806_SAR_REG, ®);
52 dev_err(dev, "cannot read from regmap\n");
56 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
92 dev_err(dev, "invalid SAR value\n");
96 /* Convert to hertz */
97 cpuclk_freq *= 1000 * 1000;
99 /* CPU clocks depend on the Sample At Reset configuration */
100 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
101 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
103 if (IS_ERR(ap806_clks[0])) {
104 ret = PTR_ERR(ap806_clks[0]);
108 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
109 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
111 if (IS_ERR(ap806_clks[1])) {
112 ret = PTR_ERR(ap806_clks[1]);
116 /* Fixed clock is always 1200 Mhz */
117 fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
118 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
119 0, 1200 * 1000 * 1000);
120 if (IS_ERR(ap806_clks[2])) {
121 ret = PTR_ERR(ap806_clks[2]);
125 /* MSS Clock is fixed clock divided by 6 */
126 name = ap_cp_unique_name(dev, syscon_node, "mss");
127 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
129 if (IS_ERR(ap806_clks[3])) {
130 ret = PTR_ERR(ap806_clks[3]);
134 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
135 name = ap_cp_unique_name(dev, syscon_node, "sdio");
136 ap806_clks[4] = clk_register_fixed_factor(NULL, name,
139 if (IS_ERR(ap806_clks[4])) {
140 ret = PTR_ERR(ap806_clks[4]);
144 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
151 clk_unregister_fixed_factor(ap806_clks[4]);
153 clk_unregister_fixed_factor(ap806_clks[3]);
155 clk_unregister_fixed_rate(ap806_clks[2]);
157 clk_unregister_fixed_rate(ap806_clks[1]);
159 clk_unregister_fixed_rate(ap806_clks[0]);
164 static int ap806_syscon_legacy_probe(struct platform_device *pdev)
166 dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
167 dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
168 dev_warn(&pdev->dev, FW_WARN
169 "This binding won't be supported in future kernel\n");
171 return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
175 static int ap806_clock_probe(struct platform_device *pdev)
177 return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
180 static const struct of_device_id ap806_syscon_legacy_of_match[] = {
181 { .compatible = "marvell,ap806-system-controller", },
185 static struct platform_driver ap806_syscon_legacy_driver = {
186 .probe = ap806_syscon_legacy_probe,
188 .name = "marvell-ap806-system-controller",
189 .of_match_table = ap806_syscon_legacy_of_match,
190 .suppress_bind_attrs = true,
193 builtin_platform_driver(ap806_syscon_legacy_driver);
195 static const struct of_device_id ap806_clock_of_match[] = {
196 { .compatible = "marvell,ap806-clock", },
200 static struct platform_driver ap806_clock_driver = {
201 .probe = ap806_clock_probe,
203 .name = "marvell-ap806-clock",
204 .of_match_table = ap806_clock_of_match,
205 .suppress_bind_attrs = true,
208 builtin_platform_driver(ap806_clock_driver);