1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/export.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
15 #include <asm/div64.h>
20 #define PLL_OUTCTRL BIT(0)
21 #define PLL_BYPASSNL BIT(1)
22 #define PLL_RESET_N BIT(2)
24 static int clk_pll_enable(struct clk_hw *hw)
26 struct clk_pll *pll = to_clk_pll(hw);
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
35 /* Skip if already enabled or in FSM mode */
36 if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
39 /* Disable PLL bypass mode. */
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
46 * H/W requires a 5us delay between disabling the bypass and
47 * de-asserting the reset. Delay 10us just to be safe.
51 /* De-assert active-low PLL reset. */
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
57 /* Wait until PLL is locked. */
60 /* Enable PLL output. */
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
65 static void clk_pll_disable(struct clk_hw *hw)
67 struct clk_pll *pll = to_clk_pll(hw);
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
72 /* Skip if in FSM mode */
73 if (val & PLL_VOTE_FSM_ENA)
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
76 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
80 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
82 struct clk_pll *pll = to_clk_pll(hw);
87 regmap_read(pll->clkr.regmap, pll->l_reg, &l);
88 regmap_read(pll->clkr.regmap, pll->m_reg, &m);
89 regmap_read(pll->clkr.regmap, pll->n_reg, &n);
95 rate = parent_rate * l;
102 if (pll->post_div_width) {
103 regmap_read(pll->clkr.regmap, pll->config_reg, &config);
104 config >>= pll->post_div_shift;
105 config &= BIT(pll->post_div_width) - 1;
113 struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
126 clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
128 struct clk_pll *pll = to_clk_pll(hw);
129 const struct pll_freq_tbl *f;
131 f = find_freq(pll->freq_tbl, req->rate);
133 req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
141 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
143 struct clk_pll *pll = to_clk_pll(hw);
144 const struct pll_freq_tbl *f;
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
149 f = find_freq(pll->freq_tbl, rate);
153 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
154 enabled = (mode & enable_mask) == enable_mask;
159 regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
160 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
161 regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
162 regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
170 const struct clk_ops clk_pll_ops = {
171 .enable = clk_pll_enable,
172 .disable = clk_pll_disable,
173 .recalc_rate = clk_pll_recalc_rate,
174 .determine_rate = clk_pll_determine_rate,
175 .set_rate = clk_pll_set_rate,
177 EXPORT_SYMBOL_GPL(clk_pll_ops);
179 static int wait_for_pll(struct clk_pll *pll)
184 const char *name = clk_hw_get_name(&pll->clkr.hw);
186 /* Wait for pll to enable. */
187 for (count = 200; count > 0; count--) {
188 ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
191 if (val & BIT(pll->status_bit))
196 WARN(1, "%s didn't enable after voting for it!\n", name);
200 static int clk_pll_vote_enable(struct clk_hw *hw)
203 struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw));
205 ret = clk_enable_regmap(hw);
209 return wait_for_pll(p);
212 const struct clk_ops clk_pll_vote_ops = {
213 .enable = clk_pll_vote_enable,
214 .disable = clk_disable_regmap,
216 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
219 const struct pll_config *config)
224 regmap_write(regmap, pll->l_reg, config->l);
225 regmap_write(regmap, pll->m_reg, config->m);
226 regmap_write(regmap, pll->n_reg, config->n);
228 val = config->vco_val;
229 val |= config->pre_div_val;
230 val |= config->post_div_val;
231 val |= config->mn_ena_mask;
232 val |= config->main_output_mask;
233 val |= config->aux_output_mask;
235 mask = config->vco_mask;
236 mask |= config->pre_div_mask;
237 mask |= config->post_div_mask;
238 mask |= config->mn_ena_mask;
239 mask |= config->main_output_mask;
240 mask |= config->aux_output_mask;
242 regmap_update_bits(regmap, pll->config_reg, mask, val);
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
246 const struct pll_config *config, bool fsm_mode)
248 clk_pll_configure(pll, regmap, config);
250 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
252 EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
254 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
255 const struct pll_config *config, bool fsm_mode)
257 clk_pll_configure(pll, regmap, config);
259 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
261 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
263 static int clk_pll_sr2_enable(struct clk_hw *hw)
265 struct clk_pll *pll = to_clk_pll(hw);
269 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
273 /* Disable PLL bypass mode. */
274 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
280 * H/W requires a 5us delay between disabling the bypass and
281 * de-asserting the reset. Delay 10us just to be safe.
285 /* De-assert active-low PLL reset. */
286 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
291 ret = wait_for_pll(pll);
295 /* Enable PLL output. */
296 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
301 clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
303 struct clk_pll *pll = to_clk_pll(hw);
304 const struct pll_freq_tbl *f;
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
309 f = find_freq(pll->freq_tbl, rate);
313 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
314 enabled = (mode & enable_mask) == enable_mask;
319 regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
320 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
321 regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
324 clk_pll_sr2_enable(hw);
329 const struct clk_ops clk_pll_sr2_ops = {
330 .enable = clk_pll_sr2_enable,
331 .disable = clk_pll_disable,
332 .set_rate = clk_pll_sr2_set_rate,
333 .recalc_rate = clk_pll_recalc_rate,
334 .determine_rate = clk_pll_determine_rate,
336 EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);