1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
16 #include "clk-regmap-divider.h"
23 P_CORE_BI_PLL_TEST_SE,
24 P_DISP_CC_PLL0_OUT_EVEN,
25 P_DISP_CC_PLL0_OUT_MAIN,
26 P_DP_PHY_PLL_LINK_CLK,
27 P_DP_PHY_PLL_VCO_DIV_CLK,
28 P_DSI0_PHY_PLL_OUT_BYTECLK,
29 P_DSI0_PHY_PLL_OUT_DSICLK,
33 static const struct pll_vco fabia_vco[] = {
34 { 249600000, 2000000000, 0 },
37 static struct clk_alpha_pll disp_cc_pll0 = {
39 .vco_table = fabia_vco,
40 .num_vco = ARRAY_SIZE(fabia_vco),
41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
43 .hw.init = &(struct clk_init_data){
44 .name = "disp_cc_pll0",
45 .parent_data = &(const struct clk_parent_data){
49 .ops = &clk_alpha_pll_fabia_ops,
54 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
59 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
62 .post_div_table = post_div_table_disp_cc_pll0_out_even,
63 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
66 .clkr.hw.init = &(struct clk_init_data){
67 .name = "disp_cc_pll0_out_even",
68 .parent_data = &(const struct clk_parent_data){
69 .hw = &disp_cc_pll0.clkr.hw,
72 .flags = CLK_SET_RATE_PARENT,
73 .ops = &clk_alpha_pll_postdiv_fabia_ops,
77 static const struct parent_map disp_cc_parent_map_0[] = {
81 static const struct clk_parent_data disp_cc_parent_data_0[] = {
82 { .fw_name = "bi_tcxo" },
85 static const struct parent_map disp_cc_parent_map_1[] = {
87 { P_DP_PHY_PLL_LINK_CLK, 1 },
88 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
91 static const struct clk_parent_data disp_cc_parent_data_1[] = {
92 { .fw_name = "bi_tcxo" },
93 { .fw_name = "dp_phy_pll_link_clk" },
94 { .fw_name = "dp_phy_pll_vco_div_clk" },
97 static const struct parent_map disp_cc_parent_map_2[] = {
99 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
102 static const struct clk_parent_data disp_cc_parent_data_2[] = {
103 { .fw_name = "bi_tcxo" },
104 { .fw_name = "dsi0_phy_pll_out_byteclk" },
107 static const struct parent_map disp_cc_parent_map_3[] = {
109 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
110 { P_GPLL0_OUT_MAIN, 4 },
111 { P_DISP_CC_PLL0_OUT_EVEN, 5 },
114 static const struct clk_parent_data disp_cc_parent_data_3[] = {
115 { .fw_name = "bi_tcxo" },
116 { .hw = &disp_cc_pll0.clkr.hw },
117 { .fw_name = "gcc_disp_gpll0_clk_src" },
118 { .hw = &disp_cc_pll0_out_even.clkr.hw },
121 static const struct parent_map disp_cc_parent_map_4[] = {
123 { P_GPLL0_OUT_MAIN, 4 },
126 static const struct clk_parent_data disp_cc_parent_data_4[] = {
127 { .fw_name = "bi_tcxo" },
128 { .fw_name = "gcc_disp_gpll0_clk_src" },
131 static const struct parent_map disp_cc_parent_map_5[] = {
133 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
136 static const struct clk_parent_data disp_cc_parent_data_5[] = {
137 { .fw_name = "bi_tcxo" },
138 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
141 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
142 F(19200000, P_BI_TCXO, 1, 0, 0),
143 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
144 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
148 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
152 .parent_map = disp_cc_parent_map_4,
153 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
154 .clkr.hw.init = &(struct clk_init_data){
155 .name = "disp_cc_mdss_ahb_clk_src",
156 .parent_data = disp_cc_parent_data_4,
157 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
158 .flags = CLK_SET_RATE_PARENT,
159 .ops = &clk_rcg2_shared_ops,
163 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
167 .parent_map = disp_cc_parent_map_2,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "disp_cc_mdss_byte0_clk_src",
170 .parent_data = disp_cc_parent_data_2,
171 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
172 .flags = CLK_SET_RATE_PARENT,
173 .ops = &clk_byte2_ops,
177 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
178 F(19200000, P_BI_TCXO, 1, 0, 0),
182 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
186 .parent_map = disp_cc_parent_map_0,
187 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "disp_cc_mdss_dp_aux_clk_src",
190 .parent_data = disp_cc_parent_data_0,
191 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
192 .ops = &clk_rcg2_ops,
196 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
200 .parent_map = disp_cc_parent_map_1,
201 .clkr.hw.init = &(struct clk_init_data){
202 .name = "disp_cc_mdss_dp_crypto_clk_src",
203 .parent_data = disp_cc_parent_data_1,
204 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
205 .flags = CLK_SET_RATE_PARENT,
206 .ops = &clk_byte2_ops,
210 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
214 .parent_map = disp_cc_parent_map_1,
215 .clkr.hw.init = &(struct clk_init_data){
216 .name = "disp_cc_mdss_dp_link_clk_src",
217 .parent_data = disp_cc_parent_data_1,
218 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
219 .flags = CLK_SET_RATE_PARENT,
220 .ops = &clk_byte2_ops,
224 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
228 .parent_map = disp_cc_parent_map_1,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "disp_cc_mdss_dp_pixel_clk_src",
231 .parent_data = disp_cc_parent_data_1,
232 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
233 .flags = CLK_SET_RATE_PARENT,
238 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
242 .parent_map = disp_cc_parent_map_2,
243 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
244 .clkr.hw.init = &(struct clk_init_data){
245 .name = "disp_cc_mdss_esc0_clk_src",
246 .parent_data = disp_cc_parent_data_2,
247 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
248 .ops = &clk_rcg2_ops,
252 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
253 F(19200000, P_BI_TCXO, 1, 0, 0),
254 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
255 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
256 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
257 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
261 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
265 .parent_map = disp_cc_parent_map_3,
266 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "disp_cc_mdss_mdp_clk_src",
269 .parent_data = disp_cc_parent_data_3,
270 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
271 .ops = &clk_rcg2_shared_ops,
275 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
279 .parent_map = disp_cc_parent_map_5,
280 .clkr.hw.init = &(struct clk_init_data){
281 .name = "disp_cc_mdss_pclk0_clk_src",
282 .parent_data = disp_cc_parent_data_5,
283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
284 .flags = CLK_SET_RATE_PARENT,
285 .ops = &clk_pixel_ops,
289 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
293 .parent_map = disp_cc_parent_map_3,
294 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
295 .clkr.hw.init = &(struct clk_init_data){
296 .name = "disp_cc_mdss_rot_clk_src",
297 .parent_data = disp_cc_parent_data_3,
298 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
299 .ops = &clk_rcg2_shared_ops,
303 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
307 .parent_map = disp_cc_parent_map_0,
308 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "disp_cc_mdss_vsync_clk_src",
311 .parent_data = disp_cc_parent_data_0,
312 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
313 .ops = &clk_rcg2_shared_ops,
317 static struct clk_branch disp_cc_mdss_ahb_clk = {
319 .halt_check = BRANCH_HALT,
321 .enable_reg = 0x2080,
322 .enable_mask = BIT(0),
323 .hw.init = &(struct clk_init_data){
324 .name = "disp_cc_mdss_ahb_clk",
325 .parent_data = &(const struct clk_parent_data){
326 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
329 .flags = CLK_SET_RATE_PARENT,
330 .ops = &clk_branch2_ops,
335 static struct clk_branch disp_cc_mdss_byte0_clk = {
337 .halt_check = BRANCH_HALT,
339 .enable_reg = 0x2028,
340 .enable_mask = BIT(0),
341 .hw.init = &(struct clk_init_data){
342 .name = "disp_cc_mdss_byte0_clk",
343 .parent_data = &(const struct clk_parent_data){
344 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
347 .flags = CLK_SET_RATE_PARENT,
348 .ops = &clk_branch2_ops,
353 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
357 .clkr.hw.init = &(struct clk_init_data) {
358 .name = "disp_cc_mdss_byte0_div_clk_src",
359 .parent_data = &(const struct clk_parent_data){
360 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
363 .ops = &clk_regmap_div_ops,
367 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
371 .clkr.hw.init = &(struct clk_init_data) {
372 .name = "disp_cc_mdss_dp_link_div_clk_src",
373 .parent_data = &(const struct clk_parent_data){
374 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
377 .ops = &clk_regmap_div_ops,
381 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
383 .halt_check = BRANCH_HALT,
385 .enable_reg = 0x202c,
386 .enable_mask = BIT(0),
387 .hw.init = &(struct clk_init_data){
388 .name = "disp_cc_mdss_byte0_intf_clk",
389 .parent_data = &(const struct clk_parent_data){
390 .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
393 .flags = CLK_SET_RATE_PARENT,
394 .ops = &clk_branch2_ops,
399 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
401 .halt_check = BRANCH_HALT,
403 .enable_reg = 0x2054,
404 .enable_mask = BIT(0),
405 .hw.init = &(struct clk_init_data){
406 .name = "disp_cc_mdss_dp_aux_clk",
407 .parent_data = &(const struct clk_parent_data){
408 .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
411 .flags = CLK_SET_RATE_PARENT,
412 .ops = &clk_branch2_ops,
417 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
419 .halt_check = BRANCH_HALT,
421 .enable_reg = 0x2048,
422 .enable_mask = BIT(0),
423 .hw.init = &(struct clk_init_data){
424 .name = "disp_cc_mdss_dp_crypto_clk",
425 .parent_data = &(const struct clk_parent_data){
426 .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
429 .flags = CLK_SET_RATE_PARENT,
430 .ops = &clk_branch2_ops,
435 static struct clk_branch disp_cc_mdss_dp_link_clk = {
437 .halt_check = BRANCH_HALT,
439 .enable_reg = 0x2040,
440 .enable_mask = BIT(0),
441 .hw.init = &(struct clk_init_data){
442 .name = "disp_cc_mdss_dp_link_clk",
443 .parent_data = &(const struct clk_parent_data){
444 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
447 .flags = CLK_SET_RATE_PARENT,
448 .ops = &clk_branch2_ops,
453 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
455 .halt_check = BRANCH_HALT,
457 .enable_reg = 0x2044,
458 .enable_mask = BIT(0),
459 .hw.init = &(struct clk_init_data){
460 .name = "disp_cc_mdss_dp_link_intf_clk",
461 .parent_data = &(const struct clk_parent_data){
462 .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
465 .ops = &clk_branch2_ops,
470 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
472 .halt_check = BRANCH_HALT,
474 .enable_reg = 0x204c,
475 .enable_mask = BIT(0),
476 .hw.init = &(struct clk_init_data){
477 .name = "disp_cc_mdss_dp_pixel_clk",
478 .parent_data = &(const struct clk_parent_data){
479 .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
482 .flags = CLK_SET_RATE_PARENT,
483 .ops = &clk_branch2_ops,
488 static struct clk_branch disp_cc_mdss_esc0_clk = {
490 .halt_check = BRANCH_HALT,
492 .enable_reg = 0x2038,
493 .enable_mask = BIT(0),
494 .hw.init = &(struct clk_init_data){
495 .name = "disp_cc_mdss_esc0_clk",
496 .parent_data = &(const struct clk_parent_data){
497 .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
500 .flags = CLK_SET_RATE_PARENT,
501 .ops = &clk_branch2_ops,
506 static struct clk_branch disp_cc_mdss_mdp_clk = {
508 .halt_check = BRANCH_HALT,
510 .enable_reg = 0x200c,
511 .enable_mask = BIT(0),
512 .hw.init = &(struct clk_init_data){
513 .name = "disp_cc_mdss_mdp_clk",
514 .parent_data = &(const struct clk_parent_data){
515 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
518 .flags = CLK_SET_RATE_PARENT,
519 .ops = &clk_branch2_ops,
524 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
526 .halt_check = BRANCH_VOTED,
528 .enable_reg = 0x201c,
529 .enable_mask = BIT(0),
530 .hw.init = &(struct clk_init_data){
531 .name = "disp_cc_mdss_mdp_lut_clk",
532 .parent_data = &(const struct clk_parent_data){
533 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
536 .ops = &clk_branch2_ops,
541 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
543 .halt_check = BRANCH_VOTED,
545 .enable_reg = 0x4004,
546 .enable_mask = BIT(0),
547 .hw.init = &(struct clk_init_data){
548 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
549 .parent_data = &(const struct clk_parent_data){
550 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
553 .flags = CLK_SET_RATE_PARENT,
554 .ops = &clk_branch2_ops,
559 static struct clk_branch disp_cc_mdss_pclk0_clk = {
561 .halt_check = BRANCH_HALT,
563 .enable_reg = 0x2004,
564 .enable_mask = BIT(0),
565 .hw.init = &(struct clk_init_data){
566 .name = "disp_cc_mdss_pclk0_clk",
567 .parent_data = &(const struct clk_parent_data){
568 .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_branch2_ops,
577 static struct clk_branch disp_cc_mdss_rot_clk = {
579 .halt_check = BRANCH_HALT,
581 .enable_reg = 0x2014,
582 .enable_mask = BIT(0),
583 .hw.init = &(struct clk_init_data){
584 .name = "disp_cc_mdss_rot_clk",
585 .parent_data = &(const struct clk_parent_data){
586 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
589 .flags = CLK_SET_RATE_PARENT,
590 .ops = &clk_branch2_ops,
595 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
597 .halt_check = BRANCH_HALT,
599 .enable_reg = 0x400c,
600 .enable_mask = BIT(0),
601 .hw.init = &(struct clk_init_data){
602 .name = "disp_cc_mdss_rscc_ahb_clk",
603 .parent_data = &(const struct clk_parent_data){
604 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
607 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
608 .ops = &clk_branch2_ops,
613 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
615 .halt_check = BRANCH_HALT,
617 .enable_reg = 0x4008,
618 .enable_mask = BIT(0),
619 .hw.init = &(struct clk_init_data){
620 .name = "disp_cc_mdss_rscc_vsync_clk",
621 .parent_data = &(const struct clk_parent_data){
622 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
625 .flags = CLK_SET_RATE_PARENT,
626 .ops = &clk_branch2_ops,
631 static struct clk_branch disp_cc_mdss_vsync_clk = {
633 .halt_check = BRANCH_HALT,
635 .enable_reg = 0x2024,
636 .enable_mask = BIT(0),
637 .hw.init = &(struct clk_init_data){
638 .name = "disp_cc_mdss_vsync_clk",
639 .parent_data = &(const struct clk_parent_data){
640 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
643 .flags = CLK_SET_RATE_PARENT,
644 .ops = &clk_branch2_ops,
649 static struct gdsc mdss_gdsc = {
654 .pwrsts = PWRSTS_OFF_ON,
658 static struct gdsc *disp_cc_sc7180_gdscs[] = {
659 [MDSS_GDSC] = &mdss_gdsc,
662 static struct clk_regmap *disp_cc_sc7180_clocks[] = {
663 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
664 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
665 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
666 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
667 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
668 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
669 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
670 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
671 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
672 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
673 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
674 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
675 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
676 &disp_cc_mdss_dp_link_div_clk_src.clkr,
677 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
678 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
679 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
680 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
681 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
682 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
683 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
684 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
685 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
686 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
687 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
688 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
689 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
690 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
691 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
692 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
693 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
694 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
695 [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
698 static const struct regmap_config disp_cc_sc7180_regmap_config = {
702 .max_register = 0x10000,
706 static const struct qcom_cc_desc disp_cc_sc7180_desc = {
707 .config = &disp_cc_sc7180_regmap_config,
708 .clks = disp_cc_sc7180_clocks,
709 .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
710 .gdscs = disp_cc_sc7180_gdscs,
711 .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
714 static const struct of_device_id disp_cc_sc7180_match_table[] = {
715 { .compatible = "qcom,sc7180-dispcc" },
718 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
720 static int disp_cc_sc7180_probe(struct platform_device *pdev)
722 struct regmap *regmap;
723 struct alpha_pll_config disp_cc_pll_config = {};
725 regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
727 return PTR_ERR(regmap);
729 /* 1380MHz configuration */
730 disp_cc_pll_config.l = 0x47;
731 disp_cc_pll_config.alpha = 0xe000;
732 disp_cc_pll_config.user_ctl_val = 0x00000001;
733 disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
735 clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
737 return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
740 static struct platform_driver disp_cc_sc7180_driver = {
741 .probe = disp_cc_sc7180_probe,
743 .name = "sc7180-dispcc",
744 .of_match_table = disp_cc_sc7180_match_table,
748 static int __init disp_cc_sc7180_init(void)
750 return platform_driver_register(&disp_cc_sc7180_driver);
752 subsys_initcall(disp_cc_sc7180_init);
754 static void __exit disp_cc_sc7180_exit(void)
756 platform_driver_unregister(&disp_cc_sc7180_driver);
758 module_exit(disp_cc_sc7180_exit);
760 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
761 MODULE_LICENSE("GPL v2");