drivers/clk/qcom/dispcc-sc7180.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "clk-branch.h"
  15 #include "clk-rcg.h"
  16 #include "clk-regmap-divider.h"
  17 #include "common.h"
  18 #include "gdsc.h"
  19
  20 enum {
  21         P_BI_TCXO,
  22         P_CHIP_SLEEP_CLK,
  23         P_CORE_BI_PLL_TEST_SE,
  24         P_DISP_CC_PLL0_OUT_EVEN,
  25         P_DISP_CC_PLL0_OUT_MAIN,
  26         P_DP_PHY_PLL_LINK_CLK,
  27         P_DP_PHY_PLL_VCO_DIV_CLK,
  28         P_DSI0_PHY_PLL_OUT_BYTECLK,
  29         P_DSI0_PHY_PLL_OUT_DSICLK,
  30         P_GPLL0_OUT_MAIN,
  31 };
  32
  33 static const struct pll_vco fabia_vco[] = {
  34         { 249600000, 2000000000, 0 },
  35 };
  36
  37 static struct clk_alpha_pll disp_cc_pll0 = {
  38         .offset = 0x0,
  39         .vco_table = fabia_vco,
  40         .num_vco = ARRAY_SIZE(fabia_vco),
  41         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  42         .clkr = {
  43                 .hw.init = &(struct clk_init_data){
  44                         .name = "disp_cc_pll0",
  45                         .parent_data = &(const struct clk_parent_data){
  46                                 .fw_name = "bi_tcxo",
  47                         },
  48                         .num_parents = 1,
  49                         .ops = &clk_alpha_pll_fabia_ops,
  50                 },
  51         },
  52 };
  53
  54 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
  55         { 0x0, 1 },
  56         { }
  57 };
  58
  59 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
  60         .offset = 0x0,
  61         .post_div_shift = 8,
  62         .post_div_table = post_div_table_disp_cc_pll0_out_even,
  63         .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
  64         .width = 4,
  65         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  66         .clkr.hw.init = &(struct clk_init_data){
  67                 .name = "disp_cc_pll0_out_even",
  68                 .parent_data = &(const struct clk_parent_data){
  69                         .hw = &disp_cc_pll0.clkr.hw,
  70                 },
  71                 .num_parents = 1,
  72                 .flags = CLK_SET_RATE_PARENT,
  73                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  74         },
  75 };
  76
  77 static const struct parent_map disp_cc_parent_map_0[] = {
  78         { P_BI_TCXO, 0 },
  79         { P_CORE_BI_PLL_TEST_SE, 7 },
  80 };
  81
  82 static const struct clk_parent_data disp_cc_parent_data_0[] = {
  83         { .fw_name = "bi_tcxo" },
  84         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  85 };
  86
  87 static const struct parent_map disp_cc_parent_map_1[] = {
  88         { P_BI_TCXO, 0 },
  89         { P_DP_PHY_PLL_LINK_CLK, 1 },
  90         { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
  91         { P_CORE_BI_PLL_TEST_SE, 7 },
  92 };
  93
  94 static const struct clk_parent_data disp_cc_parent_data_1[] = {
  95         { .fw_name = "bi_tcxo" },
  96         { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" },
  97         { .fw_name = "dp_phy_pll_vco_div_clk",
  98                                 .name = "dp_phy_pll_vco_div_clk"},
  99         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 100 };
 101
 102 static const struct parent_map disp_cc_parent_map_2[] = {
 103         { P_BI_TCXO, 0 },
 104         { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 105         { P_CORE_BI_PLL_TEST_SE, 7 },
 106 };
 107
 108 static const struct clk_parent_data disp_cc_parent_data_2[] = {
 109         { .fw_name = "bi_tcxo" },
 110         { .fw_name = "dsi0_phy_pll_out_byteclk",
 111                                 .name = "dsi0_phy_pll_out_byteclk" },
 112         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 113 };
 114
 115 static const struct parent_map disp_cc_parent_map_3[] = {
 116         { P_BI_TCXO, 0 },
 117         { P_DISP_CC_PLL0_OUT_MAIN, 1 },
 118         { P_GPLL0_OUT_MAIN, 4 },
 119         { P_DISP_CC_PLL0_OUT_EVEN, 5 },
 120         { P_CORE_BI_PLL_TEST_SE, 7 },
 121 };
 122
 123 static const struct clk_parent_data disp_cc_parent_data_3[] = {
 124         { .fw_name = "bi_tcxo" },
 125         { .hw = &disp_cc_pll0.clkr.hw },
 126         { .fw_name = "gcc_disp_gpll0_clk_src" },
 127         { .hw = &disp_cc_pll0_out_even.clkr.hw },
 128         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 129 };
 130
 131 static const struct parent_map disp_cc_parent_map_4[] = {
 132         { P_BI_TCXO, 0 },
 133         { P_GPLL0_OUT_MAIN, 4 },
 134         { P_CORE_BI_PLL_TEST_SE, 7 },
 135 };
 136
 137 static const struct clk_parent_data disp_cc_parent_data_4[] = {
 138         { .fw_name = "bi_tcxo" },
 139         { .fw_name = "gcc_disp_gpll0_clk_src" },
 140         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 141 };
 142
 143 static const struct parent_map disp_cc_parent_map_5[] = {
 144         { P_BI_TCXO, 0 },
 145         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 146         { P_CORE_BI_PLL_TEST_SE, 7 },
 147 };
 148
 149 static const struct clk_parent_data disp_cc_parent_data_5[] = {
 150         { .fw_name = "bi_tcxo" },
 151         { .fw_name = "dsi0_phy_pll_out_dsiclk",
 152                                 .name = "dsi0_phy_pll_out_dsiclk" },
 153         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 154 };
 155
 156 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 157         F(19200000, P_BI_TCXO, 1, 0, 0),
 158         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 159         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 160         { }
 161 };
 162
 163 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 164         .cmd_rcgr = 0x22bc,
 165         .mnd_width = 0,
 166         .hid_width = 5,
 167         .parent_map = disp_cc_parent_map_4,
 168         .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 169         .clkr.hw.init = &(struct clk_init_data){
 170                 .name = "disp_cc_mdss_ahb_clk_src",
 171                 .parent_data = disp_cc_parent_data_4,
 172                 .num_parents = 3,
 173                 .flags = CLK_SET_RATE_PARENT,
 174                 .ops = &clk_rcg2_shared_ops,
 175         },
 176 };
 177
 178 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 179         .cmd_rcgr = 0x2110,
 180         .mnd_width = 0,
 181         .hid_width = 5,
 182         .parent_map = disp_cc_parent_map_2,
 183         .clkr.hw.init = &(struct clk_init_data){
 184                 .name = "disp_cc_mdss_byte0_clk_src",
 185                 .parent_data = disp_cc_parent_data_2,
 186                 .num_parents = 3,
 187                 .flags = CLK_SET_RATE_PARENT,
 188                 .ops = &clk_byte2_ops,
 189         },
 190 };
 191
 192 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
 193         F(19200000, P_BI_TCXO, 1, 0, 0),
 194         { }
 195 };
 196
 197 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
 198         .cmd_rcgr = 0x21dc,
 199         .mnd_width = 0,
 200         .hid_width = 5,
 201         .parent_map = disp_cc_parent_map_0,
 202         .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 203         .clkr.hw.init = &(struct clk_init_data){
 204                 .name = "disp_cc_mdss_dp_aux_clk_src",
 205                 .parent_data = disp_cc_parent_data_0,
 206                 .num_parents = 2,
 207                 .ops = &clk_rcg2_ops,
 208         },
 209 };
 210
 211 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
 212         .cmd_rcgr = 0x2194,
 213         .mnd_width = 0,
 214         .hid_width = 5,
 215         .parent_map = disp_cc_parent_map_1,
 216         .clkr.hw.init = &(struct clk_init_data){
 217                 .name = "disp_cc_mdss_dp_crypto_clk_src",
 218                 .parent_data = disp_cc_parent_data_1,
 219                 .num_parents = 4,
 220                 .flags = CLK_SET_RATE_PARENT,
 221                 .ops = &clk_byte2_ops,
 222         },
 223 };
 224
 225 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
 226         .cmd_rcgr = 0x2178,
 227         .mnd_width = 0,
 228         .hid_width = 5,
 229         .parent_map = disp_cc_parent_map_1,
 230         .clkr.hw.init = &(struct clk_init_data){
 231                 .name = "disp_cc_mdss_dp_link_clk_src",
 232                 .parent_data = disp_cc_parent_data_1,
 233                 .num_parents = 4,
 234                 .flags = CLK_SET_RATE_PARENT,
 235                 .ops = &clk_byte2_ops,
 236         },
 237 };
 238
 239 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
 240         .cmd_rcgr = 0x21ac,
 241         .mnd_width = 16,
 242         .hid_width = 5,
 243         .parent_map = disp_cc_parent_map_1,
 244         .clkr.hw.init = &(struct clk_init_data){
 245                 .name = "disp_cc_mdss_dp_pixel_clk_src",
 246                 .parent_data = disp_cc_parent_data_1,
 247                 .num_parents = 4,
 248                 .flags = CLK_SET_RATE_PARENT,
 249                 .ops = &clk_dp_ops,
 250         },
 251 };
 252
 253 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 254         .cmd_rcgr = 0x2148,
 255         .mnd_width = 0,
 256         .hid_width = 5,
 257         .parent_map = disp_cc_parent_map_2,
 258         .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 259         .clkr.hw.init = &(struct clk_init_data){
 260                 .name = "disp_cc_mdss_esc0_clk_src",
 261                 .parent_data = disp_cc_parent_data_2,
 262                 .num_parents = 3,
 263                 .ops = &clk_rcg2_ops,
 264         },
 265 };
 266
 267 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 268         F(19200000, P_BI_TCXO, 1, 0, 0),
 269         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 270         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 271         F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 272         F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 273         { }
 274 };
 275
 276 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 277         .cmd_rcgr = 0x20c8,
 278         .mnd_width = 0,
 279         .hid_width = 5,
 280         .parent_map = disp_cc_parent_map_3,
 281         .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 282         .clkr.hw.init = &(struct clk_init_data){
 283                 .name = "disp_cc_mdss_mdp_clk_src",
 284                 .parent_data = disp_cc_parent_data_3,
 285                 .num_parents = 5,
 286                 .ops = &clk_rcg2_shared_ops,
 287         },
 288 };
 289
 290 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 291         .cmd_rcgr = 0x2098,
 292         .mnd_width = 8,
 293         .hid_width = 5,
 294         .parent_map = disp_cc_parent_map_5,
 295         .clkr.hw.init = &(struct clk_init_data){
 296                 .name = "disp_cc_mdss_pclk0_clk_src",
 297                 .parent_data = disp_cc_parent_data_5,
 298                 .num_parents = 3,
 299                 .flags = CLK_SET_RATE_PARENT,
 300                 .ops = &clk_pixel_ops,
 301         },
 302 };
 303
 304 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
 305         .cmd_rcgr = 0x20e0,
 306         .mnd_width = 0,
 307         .hid_width = 5,
 308         .parent_map = disp_cc_parent_map_3,
 309         .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 310         .clkr.hw.init = &(struct clk_init_data){
 311                 .name = "disp_cc_mdss_rot_clk_src",
 312                 .parent_data = disp_cc_parent_data_3,
 313                 .num_parents = 5,
 314                 .ops = &clk_rcg2_shared_ops,
 315         },
 316 };
 317
 318 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 319         .cmd_rcgr = 0x20f8,
 320         .mnd_width = 0,
 321         .hid_width = 5,
 322         .parent_map = disp_cc_parent_map_0,
 323         .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 324         .clkr.hw.init = &(struct clk_init_data){
 325                 .name = "disp_cc_mdss_vsync_clk_src",
 326                 .parent_data = disp_cc_parent_data_0,
 327                 .num_parents = 2,
 328                 .ops = &clk_rcg2_shared_ops,
 329         },
 330 };
 331
 332 static struct clk_branch disp_cc_mdss_ahb_clk = {
 333         .halt_reg = 0x2080,
 334         .halt_check = BRANCH_HALT,
 335         .clkr = {
 336                 .enable_reg = 0x2080,
 337                 .enable_mask = BIT(0),
 338                 .hw.init = &(struct clk_init_data){
 339                         .name = "disp_cc_mdss_ahb_clk",
 340                         .parent_data = &(const struct clk_parent_data){
 341                                 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 342                         },
 343                         .num_parents = 1,
 344                         .flags = CLK_SET_RATE_PARENT,
 345                         .ops = &clk_branch2_ops,
 346                 },
 347         },
 348 };
 349
 350 static struct clk_branch disp_cc_mdss_byte0_clk = {
 351         .halt_reg = 0x2028,
 352         .halt_check = BRANCH_HALT,
 353         .clkr = {
 354                 .enable_reg = 0x2028,
 355                 .enable_mask = BIT(0),
 356                 .hw.init = &(struct clk_init_data){
 357                         .name = "disp_cc_mdss_byte0_clk",
 358                         .parent_data = &(const struct clk_parent_data){
 359                                 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
 360                         },
 361                         .num_parents = 1,
 362                         .flags = CLK_SET_RATE_PARENT,
 363                         .ops = &clk_branch2_ops,
 364                 },
 365         },
 366 };
 367
 368 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 369         .reg = 0x2128,
 370         .shift = 0,
 371         .width = 2,
 372         .clkr.hw.init = &(struct clk_init_data) {
 373                 .name = "disp_cc_mdss_byte0_div_clk_src",
 374                 .parent_data = &(const struct clk_parent_data){
 375                         .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
 376                 },
 377                 .num_parents = 1,
 378                 .ops = &clk_regmap_div_ops,
 379         },
 380 };
 381
 382 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
 383         .reg = 0x2190,
 384         .shift = 0,
 385         .width = 2,
 386         .clkr.hw.init = &(struct clk_init_data) {
 387                 .name = "disp_cc_mdss_dp_link_div_clk_src",
 388                 .parent_data = &(const struct clk_parent_data){
 389                         .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
 390                 },
 391                 .num_parents = 1,
 392                 .ops = &clk_regmap_div_ops,
 393         },
 394 };
 395
 396 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
 397         .halt_reg = 0x202c,
 398         .halt_check = BRANCH_HALT,
 399         .clkr = {
 400                 .enable_reg = 0x202c,
 401                 .enable_mask = BIT(0),
 402                 .hw.init = &(struct clk_init_data){
 403                         .name = "disp_cc_mdss_byte0_intf_clk",
 404                         .parent_data = &(const struct clk_parent_data){
 405                                 .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 406                         },
 407                         .num_parents = 1,
 408                         .flags = CLK_SET_RATE_PARENT,
 409                         .ops = &clk_branch2_ops,
 410                 },
 411         },
 412 };
 413
 414 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
 415         .halt_reg = 0x2054,
 416         .halt_check = BRANCH_HALT,
 417         .clkr = {
 418                 .enable_reg = 0x2054,
 419                 .enable_mask = BIT(0),
 420                 .hw.init = &(struct clk_init_data){
 421                         .name = "disp_cc_mdss_dp_aux_clk",
 422                         .parent_data = &(const struct clk_parent_data){
 423                                 .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
 424                         },
 425                         .num_parents = 1,
 426                         .flags = CLK_SET_RATE_PARENT,
 427                         .ops = &clk_branch2_ops,
 428                 },
 429         },
 430 };
 431
 432 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
 433         .halt_reg = 0x2048,
 434         .halt_check = BRANCH_HALT,
 435         .clkr = {
 436                 .enable_reg = 0x2048,
 437                 .enable_mask = BIT(0),
 438                 .hw.init = &(struct clk_init_data){
 439                         .name = "disp_cc_mdss_dp_crypto_clk",
 440                         .parent_data = &(const struct clk_parent_data){
 441                                 .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
 442                         },
 443                         .num_parents = 1,
 444                         .flags = CLK_SET_RATE_PARENT,
 445                         .ops = &clk_branch2_ops,
 446                 },
 447         },
 448 };
 449
 450 static struct clk_branch disp_cc_mdss_dp_link_clk = {
 451         .halt_reg = 0x2040,
 452         .halt_check = BRANCH_HALT,
 453         .clkr = {
 454                 .enable_reg = 0x2040,
 455                 .enable_mask = BIT(0),
 456                 .hw.init = &(struct clk_init_data){
 457                         .name = "disp_cc_mdss_dp_link_clk",
 458                         .parent_data = &(const struct clk_parent_data){
 459                                 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 460                         },
 461                         .num_parents = 1,
 462                         .flags = CLK_SET_RATE_PARENT,
 463                         .ops = &clk_branch2_ops,
 464                 },
 465         },
 466 };
 467
 468 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
 469         .halt_reg = 0x2044,
 470         .halt_check = BRANCH_HALT,
 471         .clkr = {
 472                 .enable_reg = 0x2044,
 473                 .enable_mask = BIT(0),
 474                 .hw.init = &(struct clk_init_data){
 475                         .name = "disp_cc_mdss_dp_link_intf_clk",
 476                         .parent_data = &(const struct clk_parent_data){
 477                                 .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
 478                         },
 479                         .num_parents = 1,
 480                         .ops = &clk_branch2_ops,
 481                 },
 482         },
 483 };
 484
 485 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
 486         .halt_reg = 0x204c,
 487         .halt_check = BRANCH_HALT,
 488         .clkr = {
 489                 .enable_reg = 0x204c,
 490                 .enable_mask = BIT(0),
 491                 .hw.init = &(struct clk_init_data){
 492                         .name = "disp_cc_mdss_dp_pixel_clk",
 493                         .parent_data = &(const struct clk_parent_data){
 494                                 .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
 495                         },
 496                         .num_parents = 1,
 497                         .flags = CLK_SET_RATE_PARENT,
 498                         .ops = &clk_branch2_ops,
 499                 },
 500         },
 501 };
 502
 503 static struct clk_branch disp_cc_mdss_esc0_clk = {
 504         .halt_reg = 0x2038,
 505         .halt_check = BRANCH_HALT,
 506         .clkr = {
 507                 .enable_reg = 0x2038,
 508                 .enable_mask = BIT(0),
 509                 .hw.init = &(struct clk_init_data){
 510                         .name = "disp_cc_mdss_esc0_clk",
 511                         .parent_data = &(const struct clk_parent_data){
 512                                 .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
 513                         },
 514                         .num_parents = 1,
 515                         .flags = CLK_SET_RATE_PARENT,
 516                         .ops = &clk_branch2_ops,
 517                 },
 518         },
 519 };
 520
 521 static struct clk_branch disp_cc_mdss_mdp_clk = {
 522         .halt_reg = 0x200c,
 523         .halt_check = BRANCH_HALT,
 524         .clkr = {
 525                 .enable_reg = 0x200c,
 526                 .enable_mask = BIT(0),
 527                 .hw.init = &(struct clk_init_data){
 528                         .name = "disp_cc_mdss_mdp_clk",
 529                         .parent_data = &(const struct clk_parent_data){
 530                                 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
 531                         },
 532                         .num_parents = 1,
 533                         .flags = CLK_SET_RATE_PARENT,
 534                         .ops = &clk_branch2_ops,
 535                 },
 536         },
 537 };
 538
 539 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
 540         .halt_reg = 0x201c,
 541         .halt_check = BRANCH_VOTED,
 542         .clkr = {
 543                 .enable_reg = 0x201c,
 544                 .enable_mask = BIT(0),
 545                 .hw.init = &(struct clk_init_data){
 546                         .name = "disp_cc_mdss_mdp_lut_clk",
 547                         .parent_data = &(const struct clk_parent_data){
 548                                 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
 549                         },
 550                         .num_parents = 1,
 551                         .ops = &clk_branch2_ops,
 552                 },
 553         },
 554 };
 555
 556 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
 557         .halt_reg = 0x4004,
 558         .halt_check = BRANCH_VOTED,
 559         .clkr = {
 560                 .enable_reg = 0x4004,
 561                 .enable_mask = BIT(0),
 562                 .hw.init = &(struct clk_init_data){
 563                         .name = "disp_cc_mdss_non_gdsc_ahb_clk",
 564                         .parent_data = &(const struct clk_parent_data){
 565                                 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 566                         },
 567                         .num_parents = 1,
 568                         .flags = CLK_SET_RATE_PARENT,
 569                         .ops = &clk_branch2_ops,
 570                 },
 571         },
 572 };
 573
 574 static struct clk_branch disp_cc_mdss_pclk0_clk = {
 575         .halt_reg = 0x2004,
 576         .halt_check = BRANCH_HALT,
 577         .clkr = {
 578                 .enable_reg = 0x2004,
 579                 .enable_mask = BIT(0),
 580                 .hw.init = &(struct clk_init_data){
 581                         .name = "disp_cc_mdss_pclk0_clk",
 582                         .parent_data = &(const struct clk_parent_data){
 583                                 .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
 584                         },
 585                         .num_parents = 1,
 586                         .flags = CLK_SET_RATE_PARENT,
 587                         .ops = &clk_branch2_ops,
 588                 },
 589         },
 590 };
 591
 592 static struct clk_branch disp_cc_mdss_rot_clk = {
 593         .halt_reg = 0x2014,
 594         .halt_check = BRANCH_HALT,
 595         .clkr = {
 596                 .enable_reg = 0x2014,
 597                 .enable_mask = BIT(0),
 598                 .hw.init = &(struct clk_init_data){
 599                         .name = "disp_cc_mdss_rot_clk",
 600                         .parent_data = &(const struct clk_parent_data){
 601                                 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
 602                         },
 603                         .num_parents = 1,
 604                         .flags = CLK_SET_RATE_PARENT,
 605                         .ops = &clk_branch2_ops,
 606                 },
 607         },
 608 };
 609
 610 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
 611         .halt_reg = 0x400c,
 612         .halt_check = BRANCH_HALT,
 613         .clkr = {
 614                 .enable_reg = 0x400c,
 615                 .enable_mask = BIT(0),
 616                 .hw.init = &(struct clk_init_data){
 617                         .name = "disp_cc_mdss_rscc_ahb_clk",
 618                         .parent_data = &(const struct clk_parent_data){
 619                                 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 620                         },
 621                         .num_parents = 1,
 622                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
 623                         .ops = &clk_branch2_ops,
 624                 },
 625         },
 626 };
 627
 628 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
 629         .halt_reg = 0x4008,
 630         .halt_check = BRANCH_HALT,
 631         .clkr = {
 632                 .enable_reg = 0x4008,
 633                 .enable_mask = BIT(0),
 634                 .hw.init = &(struct clk_init_data){
 635                         .name = "disp_cc_mdss_rscc_vsync_clk",
 636                         .parent_data = &(const struct clk_parent_data){
 637                                 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
 638                         },
 639                         .num_parents = 1,
 640                         .flags = CLK_SET_RATE_PARENT,
 641                         .ops = &clk_branch2_ops,
 642                 },
 643         },
 644 };
 645
 646 static struct clk_branch disp_cc_mdss_vsync_clk = {
 647         .halt_reg = 0x2024,
 648         .halt_check = BRANCH_HALT,
 649         .clkr = {
 650                 .enable_reg = 0x2024,
 651                 .enable_mask = BIT(0),
 652                 .hw.init = &(struct clk_init_data){
 653                         .name = "disp_cc_mdss_vsync_clk",
 654                         .parent_data = &(const struct clk_parent_data){
 655                                 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
 656                         },
 657                         .num_parents = 1,
 658                         .flags = CLK_SET_RATE_PARENT,
 659                         .ops = &clk_branch2_ops,
 660                 },
 661         },
 662 };
 663
 664 static struct gdsc mdss_gdsc = {
 665         .gdscr = 0x3000,
 666         .pd = {
 667                 .name = "mdss_gdsc",
 668         },
 669         .pwrsts = PWRSTS_OFF_ON,
 670         .flags = HW_CTRL,
 671 };
 672
 673 static struct gdsc *disp_cc_sc7180_gdscs[] = {
 674         [MDSS_GDSC] = &mdss_gdsc,
 675 };
 676
 677 static struct clk_regmap *disp_cc_sc7180_clocks[] = {
 678         [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
 679         [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
 680         [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
 681         [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
 682         [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
 683         [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
 684         [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
 685         [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
 686         [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
 687         [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
 688         [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
 689         [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
 690         [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
 691                                 &disp_cc_mdss_dp_link_div_clk_src.clkr,
 692         [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
 693         [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
 694         [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
 695         [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
 696         [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
 697         [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
 698         [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
 699         [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
 700         [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
 701         [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
 702         [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
 703         [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
 704         [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
 705         [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
 706         [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
 707         [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
 708         [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
 709         [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
 710         [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
 711 };
 712
 713 static const struct regmap_config disp_cc_sc7180_regmap_config = {
 714         .reg_bits = 32,
 715         .reg_stride = 4,
 716         .val_bits = 32,
 717         .max_register = 0x10000,
 718         .fast_io = true,
 719 };
 720
 721 static const struct qcom_cc_desc disp_cc_sc7180_desc = {
 722         .config = &disp_cc_sc7180_regmap_config,
 723         .clks = disp_cc_sc7180_clocks,
 724         .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
 725         .gdscs = disp_cc_sc7180_gdscs,
 726         .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
 727 };
 728
 729 static const struct of_device_id disp_cc_sc7180_match_table[] = {
 730         { .compatible = "qcom,sc7180-dispcc" },
 731         { }
 732 };
 733 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
 734
 735 static int disp_cc_sc7180_probe(struct platform_device *pdev)
 736 {
 737         struct regmap *regmap;
 738         struct alpha_pll_config disp_cc_pll_config = {};
 739
 740         regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
 741         if (IS_ERR(regmap))
 742                 return PTR_ERR(regmap);
 743
 744         /* 1380MHz configuration */
 745         disp_cc_pll_config.l = 0x47;
 746         disp_cc_pll_config.alpha = 0xe000;
 747         disp_cc_pll_config.user_ctl_val = 0x00000001;
 748         disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
 749
 750         clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
 751
 752         return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
 753 }
 754
 755 static struct platform_driver disp_cc_sc7180_driver = {
 756         .probe = disp_cc_sc7180_probe,
 757         .driver = {
 758                 .name = "sc7180-dispcc",
 759                 .of_match_table = disp_cc_sc7180_match_table,
 760         },
 761 };
 762
 763 static int __init disp_cc_sc7180_init(void)
 764 {
 765         return platform_driver_register(&disp_cc_sc7180_driver);
 766 }
 767 subsys_initcall(disp_cc_sc7180_init);
 768
 769 static void __exit disp_cc_sc7180_exit(void)
 770 {
 771         platform_driver_unregister(&disp_cc_sc7180_driver);
 772 }
 773 module_exit(disp_cc_sc7180_exit);
 774
 775 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
 776 MODULE_LICENSE("GPL v2");