1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
30 P_CORE_BI_PLL_TEST_SE,
33 P_PLL0_EARLY_DIV_CLK_SRC,
38 static const struct parent_map gcc_parent_map_0[] = {
40 { P_GPLL0_OUT_MAIN, 1 },
41 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
42 { P_CORE_BI_PLL_TEST_SE, 7 },
45 static const char * const gcc_parent_names_0[] = {
49 "core_bi_pll_test_se",
52 static const struct parent_map gcc_parent_map_1[] = {
54 { P_GPLL0_OUT_MAIN, 1 },
55 { P_CORE_BI_PLL_TEST_SE, 7 },
58 static const char * const gcc_parent_names_1[] = {
61 "core_bi_pll_test_se",
64 static const struct parent_map gcc_parent_map_2[] = {
66 { P_GPLL0_OUT_MAIN, 1 },
68 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
69 { P_CORE_BI_PLL_TEST_SE, 7 },
72 static const char * const gcc_parent_names_2[] = {
77 "core_bi_pll_test_se",
80 static const struct parent_map gcc_parent_map_3[] = {
83 { P_CORE_BI_PLL_TEST_SE, 7 },
86 static const char * const gcc_parent_names_3[] = {
89 "core_bi_pll_test_se",
92 static const struct parent_map gcc_parent_map_4[] = {
94 { P_GPLL0_OUT_MAIN, 1 },
95 { P_GPLL4_OUT_MAIN, 5 },
96 { P_CORE_BI_PLL_TEST_SE, 7 },
99 static const char * const gcc_parent_names_4[] = {
103 "core_bi_pll_test_se",
106 static const struct parent_map gcc_parent_map_5[] = {
108 { P_GPLL0_OUT_MAIN, 1 },
109 { P_AUD_REF_CLK, 2 },
110 { P_CORE_BI_PLL_TEST_SE, 7 },
113 static const char * const gcc_parent_names_5[] = {
117 "core_bi_pll_test_se",
120 static struct clk_fixed_factor xo = {
123 .hw.init = &(struct clk_init_data){
125 .parent_names = (const char *[]){ "xo_board" },
127 .ops = &clk_fixed_factor_ops,
131 static struct pll_vco fabia_vco[] = {
132 { 250000000, 2000000000, 0 },
133 { 125000000, 1000000000, 1 },
136 static struct clk_alpha_pll gpll0 = {
138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
139 .vco_table = fabia_vco,
140 .num_vco = ARRAY_SIZE(fabia_vco),
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
144 .hw.init = &(struct clk_init_data){
146 .parent_names = (const char *[]){ "xo" },
148 .ops = &clk_alpha_pll_ops,
153 static struct clk_alpha_pll_postdiv gpll0_out_even = {
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
156 .clkr.hw.init = &(struct clk_init_data){
157 .name = "gpll0_out_even",
158 .parent_names = (const char *[]){ "gpll0" },
160 .ops = &clk_alpha_pll_postdiv_ops,
164 static struct clk_alpha_pll_postdiv gpll0_out_main = {
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
167 .clkr.hw.init = &(struct clk_init_data){
168 .name = "gpll0_out_main",
169 .parent_names = (const char *[]){ "gpll0" },
171 .ops = &clk_alpha_pll_postdiv_ops,
175 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
178 .clkr.hw.init = &(struct clk_init_data){
179 .name = "gpll0_out_odd",
180 .parent_names = (const char *[]){ "gpll0" },
182 .ops = &clk_alpha_pll_postdiv_ops,
186 static struct clk_alpha_pll_postdiv gpll0_out_test = {
188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
189 .clkr.hw.init = &(struct clk_init_data){
190 .name = "gpll0_out_test",
191 .parent_names = (const char *[]){ "gpll0" },
193 .ops = &clk_alpha_pll_postdiv_ops,
197 static struct clk_alpha_pll gpll1 = {
199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
200 .vco_table = fabia_vco,
201 .num_vco = ARRAY_SIZE(fabia_vco),
203 .enable_reg = 0x52000,
204 .enable_mask = BIT(1),
205 .hw.init = &(struct clk_init_data){
207 .parent_names = (const char *[]){ "xo" },
209 .ops = &clk_alpha_pll_ops,
214 static struct clk_alpha_pll_postdiv gpll1_out_even = {
216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "gpll1_out_even",
219 .parent_names = (const char *[]){ "gpll1" },
221 .ops = &clk_alpha_pll_postdiv_ops,
225 static struct clk_alpha_pll_postdiv gpll1_out_main = {
227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
228 .clkr.hw.init = &(struct clk_init_data){
229 .name = "gpll1_out_main",
230 .parent_names = (const char *[]){ "gpll1" },
232 .ops = &clk_alpha_pll_postdiv_ops,
236 static struct clk_alpha_pll_postdiv gpll1_out_odd = {
238 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "gpll1_out_odd",
241 .parent_names = (const char *[]){ "gpll1" },
243 .ops = &clk_alpha_pll_postdiv_ops,
247 static struct clk_alpha_pll_postdiv gpll1_out_test = {
249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "gpll1_out_test",
252 .parent_names = (const char *[]){ "gpll1" },
254 .ops = &clk_alpha_pll_postdiv_ops,
258 static struct clk_alpha_pll gpll2 = {
260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
261 .vco_table = fabia_vco,
262 .num_vco = ARRAY_SIZE(fabia_vco),
264 .enable_reg = 0x52000,
265 .enable_mask = BIT(2),
266 .hw.init = &(struct clk_init_data){
268 .parent_names = (const char *[]){ "xo" },
270 .ops = &clk_alpha_pll_ops,
275 static struct clk_alpha_pll_postdiv gpll2_out_even = {
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "gpll2_out_even",
280 .parent_names = (const char *[]){ "gpll2" },
282 .ops = &clk_alpha_pll_postdiv_ops,
286 static struct clk_alpha_pll_postdiv gpll2_out_main = {
288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "gpll2_out_main",
291 .parent_names = (const char *[]){ "gpll2" },
293 .ops = &clk_alpha_pll_postdiv_ops,
297 static struct clk_alpha_pll_postdiv gpll2_out_odd = {
299 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "gpll2_out_odd",
302 .parent_names = (const char *[]){ "gpll2" },
304 .ops = &clk_alpha_pll_postdiv_ops,
308 static struct clk_alpha_pll_postdiv gpll2_out_test = {
310 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
311 .clkr.hw.init = &(struct clk_init_data){
312 .name = "gpll2_out_test",
313 .parent_names = (const char *[]){ "gpll2" },
315 .ops = &clk_alpha_pll_postdiv_ops,
319 static struct clk_alpha_pll gpll3 = {
321 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
322 .vco_table = fabia_vco,
323 .num_vco = ARRAY_SIZE(fabia_vco),
325 .enable_reg = 0x52000,
326 .enable_mask = BIT(3),
327 .hw.init = &(struct clk_init_data){
329 .parent_names = (const char *[]){ "xo" },
331 .ops = &clk_alpha_pll_ops,
336 static struct clk_alpha_pll_postdiv gpll3_out_even = {
338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "gpll3_out_even",
341 .parent_names = (const char *[]){ "gpll3" },
343 .ops = &clk_alpha_pll_postdiv_ops,
347 static struct clk_alpha_pll_postdiv gpll3_out_main = {
349 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "gpll3_out_main",
352 .parent_names = (const char *[]){ "gpll3" },
354 .ops = &clk_alpha_pll_postdiv_ops,
358 static struct clk_alpha_pll_postdiv gpll3_out_odd = {
360 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
361 .clkr.hw.init = &(struct clk_init_data){
362 .name = "gpll3_out_odd",
363 .parent_names = (const char *[]){ "gpll3" },
365 .ops = &clk_alpha_pll_postdiv_ops,
369 static struct clk_alpha_pll_postdiv gpll3_out_test = {
371 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
372 .clkr.hw.init = &(struct clk_init_data){
373 .name = "gpll3_out_test",
374 .parent_names = (const char *[]){ "gpll3" },
376 .ops = &clk_alpha_pll_postdiv_ops,
380 static struct clk_alpha_pll gpll4 = {
382 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
383 .vco_table = fabia_vco,
384 .num_vco = ARRAY_SIZE(fabia_vco),
386 .enable_reg = 0x52000,
387 .enable_mask = BIT(4),
388 .hw.init = &(struct clk_init_data){
390 .parent_names = (const char *[]){ "xo" },
392 .ops = &clk_alpha_pll_ops,
397 static struct clk_alpha_pll_postdiv gpll4_out_even = {
399 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "gpll4_out_even",
402 .parent_names = (const char *[]){ "gpll4" },
404 .ops = &clk_alpha_pll_postdiv_ops,
408 static struct clk_alpha_pll_postdiv gpll4_out_main = {
410 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gpll4_out_main",
413 .parent_names = (const char *[]){ "gpll4" },
415 .ops = &clk_alpha_pll_postdiv_ops,
419 static struct clk_alpha_pll_postdiv gpll4_out_odd = {
421 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
422 .clkr.hw.init = &(struct clk_init_data){
423 .name = "gpll4_out_odd",
424 .parent_names = (const char *[]){ "gpll4" },
426 .ops = &clk_alpha_pll_postdiv_ops,
430 static struct clk_alpha_pll_postdiv gpll4_out_test = {
432 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
433 .clkr.hw.init = &(struct clk_init_data){
434 .name = "gpll4_out_test",
435 .parent_names = (const char *[]){ "gpll4" },
437 .ops = &clk_alpha_pll_postdiv_ops,
441 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
442 F(19200000, P_XO, 1, 0, 0),
443 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
447 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
451 .parent_map = gcc_parent_map_1,
452 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
453 .clkr.hw.init = &(struct clk_init_data){
454 .name = "blsp1_qup1_i2c_apps_clk_src",
455 .parent_names = gcc_parent_names_1,
457 .ops = &clk_rcg2_ops,
461 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
462 F(960000, P_XO, 10, 1, 2),
463 F(4800000, P_XO, 4, 0, 0),
464 F(9600000, P_XO, 2, 0, 0),
465 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
466 F(19200000, P_XO, 1, 0, 0),
467 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
468 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
472 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
476 .parent_map = gcc_parent_map_0,
477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "blsp1_qup1_spi_apps_clk_src",
480 .parent_names = gcc_parent_names_0,
482 .ops = &clk_rcg2_ops,
486 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
490 .parent_map = gcc_parent_map_1,
491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "blsp1_qup2_i2c_apps_clk_src",
494 .parent_names = gcc_parent_names_1,
496 .ops = &clk_rcg2_ops,
500 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
504 .parent_map = gcc_parent_map_0,
505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "blsp1_qup2_spi_apps_clk_src",
508 .parent_names = gcc_parent_names_0,
510 .ops = &clk_rcg2_ops,
514 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
518 .parent_map = gcc_parent_map_1,
519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "blsp1_qup3_i2c_apps_clk_src",
522 .parent_names = gcc_parent_names_1,
524 .ops = &clk_rcg2_ops,
528 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
532 .parent_map = gcc_parent_map_0,
533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "blsp1_qup3_spi_apps_clk_src",
536 .parent_names = gcc_parent_names_0,
538 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
548 .clkr.hw.init = &(struct clk_init_data){
549 .name = "blsp1_qup4_i2c_apps_clk_src",
550 .parent_names = gcc_parent_names_1,
552 .ops = &clk_rcg2_ops,
556 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
560 .parent_map = gcc_parent_map_0,
561 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
562 .clkr.hw.init = &(struct clk_init_data){
563 .name = "blsp1_qup4_spi_apps_clk_src",
564 .parent_names = gcc_parent_names_0,
566 .ops = &clk_rcg2_ops,
570 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
574 .parent_map = gcc_parent_map_1,
575 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
576 .clkr.hw.init = &(struct clk_init_data){
577 .name = "blsp1_qup5_i2c_apps_clk_src",
578 .parent_names = gcc_parent_names_1,
580 .ops = &clk_rcg2_ops,
584 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
588 .parent_map = gcc_parent_map_0,
589 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
590 .clkr.hw.init = &(struct clk_init_data){
591 .name = "blsp1_qup5_spi_apps_clk_src",
592 .parent_names = gcc_parent_names_0,
594 .ops = &clk_rcg2_ops,
598 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
602 .parent_map = gcc_parent_map_1,
603 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
604 .clkr.hw.init = &(struct clk_init_data){
605 .name = "blsp1_qup6_i2c_apps_clk_src",
606 .parent_names = gcc_parent_names_1,
608 .ops = &clk_rcg2_ops,
612 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
616 .parent_map = gcc_parent_map_0,
617 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
618 .clkr.hw.init = &(struct clk_init_data){
619 .name = "blsp1_qup6_spi_apps_clk_src",
620 .parent_names = gcc_parent_names_0,
622 .ops = &clk_rcg2_ops,
626 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
627 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
628 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
629 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
630 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
631 F(19200000, P_XO, 1, 0, 0),
632 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
633 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
634 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
635 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
636 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
637 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
638 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
639 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
640 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
641 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
645 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
649 .parent_map = gcc_parent_map_0,
650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "blsp1_uart1_apps_clk_src",
653 .parent_names = gcc_parent_names_0,
655 .ops = &clk_rcg2_ops,
659 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
663 .parent_map = gcc_parent_map_0,
664 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "blsp1_uart2_apps_clk_src",
667 .parent_names = gcc_parent_names_0,
669 .ops = &clk_rcg2_ops,
673 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
677 .parent_map = gcc_parent_map_0,
678 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
679 .clkr.hw.init = &(struct clk_init_data){
680 .name = "blsp1_uart3_apps_clk_src",
681 .parent_names = gcc_parent_names_0,
683 .ops = &clk_rcg2_ops,
687 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
691 .parent_map = gcc_parent_map_1,
692 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
693 .clkr.hw.init = &(struct clk_init_data){
694 .name = "blsp2_qup1_i2c_apps_clk_src",
695 .parent_names = gcc_parent_names_1,
697 .ops = &clk_rcg2_ops,
701 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
705 .parent_map = gcc_parent_map_0,
706 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
707 .clkr.hw.init = &(struct clk_init_data){
708 .name = "blsp2_qup1_spi_apps_clk_src",
709 .parent_names = gcc_parent_names_0,
711 .ops = &clk_rcg2_ops,
715 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
719 .parent_map = gcc_parent_map_1,
720 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
721 .clkr.hw.init = &(struct clk_init_data){
722 .name = "blsp2_qup2_i2c_apps_clk_src",
723 .parent_names = gcc_parent_names_1,
725 .ops = &clk_rcg2_ops,
729 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
733 .parent_map = gcc_parent_map_0,
734 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
735 .clkr.hw.init = &(struct clk_init_data){
736 .name = "blsp2_qup2_spi_apps_clk_src",
737 .parent_names = gcc_parent_names_0,
739 .ops = &clk_rcg2_ops,
743 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
747 .parent_map = gcc_parent_map_1,
748 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "blsp2_qup3_i2c_apps_clk_src",
751 .parent_names = gcc_parent_names_1,
753 .ops = &clk_rcg2_ops,
757 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
761 .parent_map = gcc_parent_map_0,
762 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "blsp2_qup3_spi_apps_clk_src",
765 .parent_names = gcc_parent_names_0,
767 .ops = &clk_rcg2_ops,
771 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
775 .parent_map = gcc_parent_map_1,
776 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
777 .clkr.hw.init = &(struct clk_init_data){
778 .name = "blsp2_qup4_i2c_apps_clk_src",
779 .parent_names = gcc_parent_names_1,
781 .ops = &clk_rcg2_ops,
785 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
789 .parent_map = gcc_parent_map_0,
790 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
791 .clkr.hw.init = &(struct clk_init_data){
792 .name = "blsp2_qup4_spi_apps_clk_src",
793 .parent_names = gcc_parent_names_0,
795 .ops = &clk_rcg2_ops,
799 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
803 .parent_map = gcc_parent_map_1,
804 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
805 .clkr.hw.init = &(struct clk_init_data){
806 .name = "blsp2_qup5_i2c_apps_clk_src",
807 .parent_names = gcc_parent_names_1,
809 .ops = &clk_rcg2_ops,
813 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
817 .parent_map = gcc_parent_map_0,
818 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
819 .clkr.hw.init = &(struct clk_init_data){
820 .name = "blsp2_qup5_spi_apps_clk_src",
821 .parent_names = gcc_parent_names_0,
823 .ops = &clk_rcg2_ops,
827 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
831 .parent_map = gcc_parent_map_1,
832 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "blsp2_qup6_i2c_apps_clk_src",
835 .parent_names = gcc_parent_names_1,
837 .ops = &clk_rcg2_ops,
841 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
845 .parent_map = gcc_parent_map_0,
846 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
847 .clkr.hw.init = &(struct clk_init_data){
848 .name = "blsp2_qup6_spi_apps_clk_src",
849 .parent_names = gcc_parent_names_0,
851 .ops = &clk_rcg2_ops,
855 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
859 .parent_map = gcc_parent_map_0,
860 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
861 .clkr.hw.init = &(struct clk_init_data){
862 .name = "blsp2_uart1_apps_clk_src",
863 .parent_names = gcc_parent_names_0,
865 .ops = &clk_rcg2_ops,
869 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
873 .parent_map = gcc_parent_map_0,
874 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
875 .clkr.hw.init = &(struct clk_init_data){
876 .name = "blsp2_uart2_apps_clk_src",
877 .parent_names = gcc_parent_names_0,
879 .ops = &clk_rcg2_ops,
883 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
887 .parent_map = gcc_parent_map_0,
888 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "blsp2_uart3_apps_clk_src",
891 .parent_names = gcc_parent_names_0,
893 .ops = &clk_rcg2_ops,
897 static const struct freq_tbl ftbl_gp1_clk_src[] = {
898 F(19200000, P_XO, 1, 0, 0),
899 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
900 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
904 static struct clk_rcg2 gp1_clk_src = {
908 .parent_map = gcc_parent_map_2,
909 .freq_tbl = ftbl_gp1_clk_src,
910 .clkr.hw.init = &(struct clk_init_data){
911 .name = "gp1_clk_src",
912 .parent_names = gcc_parent_names_2,
914 .ops = &clk_rcg2_ops,
918 static struct clk_rcg2 gp2_clk_src = {
922 .parent_map = gcc_parent_map_2,
923 .freq_tbl = ftbl_gp1_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "gp2_clk_src",
926 .parent_names = gcc_parent_names_2,
928 .ops = &clk_rcg2_ops,
932 static struct clk_rcg2 gp3_clk_src = {
936 .parent_map = gcc_parent_map_2,
937 .freq_tbl = ftbl_gp1_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "gp3_clk_src",
940 .parent_names = gcc_parent_names_2,
942 .ops = &clk_rcg2_ops,
946 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
947 F(19200000, P_XO, 1, 0, 0),
948 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
949 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
953 static struct clk_rcg2 hmss_ahb_clk_src = {
957 .parent_map = gcc_parent_map_1,
958 .freq_tbl = ftbl_hmss_ahb_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "hmss_ahb_clk_src",
961 .parent_names = gcc_parent_names_1,
963 .ops = &clk_rcg2_ops,
967 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
968 F(19200000, P_XO, 1, 0, 0),
972 static struct clk_rcg2 hmss_rbcpr_clk_src = {
976 .parent_map = gcc_parent_map_1,
977 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
978 .clkr.hw.init = &(struct clk_init_data){
979 .name = "hmss_rbcpr_clk_src",
980 .parent_names = gcc_parent_names_1,
982 .ops = &clk_rcg2_ops,
986 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
987 F(1010526, P_XO, 1, 1, 19),
991 static struct clk_rcg2 pcie_aux_clk_src = {
995 .parent_map = gcc_parent_map_3,
996 .freq_tbl = ftbl_pcie_aux_clk_src,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "pcie_aux_clk_src",
999 .parent_names = gcc_parent_names_3,
1001 .ops = &clk_rcg2_ops,
1005 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1006 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1010 static struct clk_rcg2 pdm2_clk_src = {
1011 .cmd_rcgr = 0x33010,
1014 .parent_map = gcc_parent_map_1,
1015 .freq_tbl = ftbl_pdm2_clk_src,
1016 .clkr.hw.init = &(struct clk_init_data){
1017 .name = "pdm2_clk_src",
1018 .parent_names = gcc_parent_names_1,
1020 .ops = &clk_rcg2_ops,
1024 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1025 F(144000, P_XO, 16, 3, 25),
1026 F(400000, P_XO, 12, 1, 4),
1027 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1028 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1029 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1030 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1031 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1035 static struct clk_rcg2 sdcc2_apps_clk_src = {
1036 .cmd_rcgr = 0x14010,
1039 .parent_map = gcc_parent_map_4,
1040 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "sdcc2_apps_clk_src",
1043 .parent_names = gcc_parent_names_4,
1045 .ops = &clk_rcg2_floor_ops,
1049 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1050 F(144000, P_XO, 16, 3, 25),
1051 F(400000, P_XO, 12, 1, 4),
1052 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1053 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1054 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1055 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1059 static struct clk_rcg2 sdcc4_apps_clk_src = {
1060 .cmd_rcgr = 0x16010,
1063 .parent_map = gcc_parent_map_1,
1064 .freq_tbl = ftbl_sdcc4_apps_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "sdcc4_apps_clk_src",
1067 .parent_names = gcc_parent_names_1,
1069 .ops = &clk_rcg2_floor_ops,
1073 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1074 F(105495, P_XO, 1, 1, 182),
1078 static struct clk_rcg2 tsif_ref_clk_src = {
1079 .cmd_rcgr = 0x36010,
1082 .parent_map = gcc_parent_map_5,
1083 .freq_tbl = ftbl_tsif_ref_clk_src,
1084 .clkr.hw.init = &(struct clk_init_data){
1085 .name = "tsif_ref_clk_src",
1086 .parent_names = gcc_parent_names_5,
1088 .ops = &clk_rcg2_ops,
1092 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1093 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1094 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1095 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1099 static struct clk_rcg2 ufs_axi_clk_src = {
1100 .cmd_rcgr = 0x75018,
1103 .parent_map = gcc_parent_map_0,
1104 .freq_tbl = ftbl_ufs_axi_clk_src,
1105 .clkr.hw.init = &(struct clk_init_data){
1106 .name = "ufs_axi_clk_src",
1107 .parent_names = gcc_parent_names_0,
1109 .ops = &clk_rcg2_ops,
1113 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1114 F(19200000, P_XO, 1, 0, 0),
1115 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1116 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1117 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1121 static struct clk_rcg2 usb30_master_clk_src = {
1125 .parent_map = gcc_parent_map_0,
1126 .freq_tbl = ftbl_usb30_master_clk_src,
1127 .clkr.hw.init = &(struct clk_init_data){
1128 .name = "usb30_master_clk_src",
1129 .parent_names = gcc_parent_names_0,
1131 .ops = &clk_rcg2_ops,
1135 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1139 .parent_map = gcc_parent_map_0,
1140 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1141 .clkr.hw.init = &(struct clk_init_data){
1142 .name = "usb30_mock_utmi_clk_src",
1143 .parent_names = gcc_parent_names_0,
1145 .ops = &clk_rcg2_ops,
1149 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1150 F(1200000, P_XO, 16, 0, 0),
1154 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1155 .cmd_rcgr = 0x5000c,
1158 .parent_map = gcc_parent_map_3,
1159 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1160 .clkr.hw.init = &(struct clk_init_data){
1161 .name = "usb3_phy_aux_clk_src",
1162 .parent_names = gcc_parent_names_3,
1164 .ops = &clk_rcg2_ops,
1168 static struct clk_branch gcc_aggre1_noc_xo_clk = {
1169 .halt_reg = 0x8202c,
1170 .halt_check = BRANCH_HALT,
1172 .enable_reg = 0x8202c,
1173 .enable_mask = BIT(0),
1174 .hw.init = &(struct clk_init_data){
1175 .name = "gcc_aggre1_noc_xo_clk",
1176 .ops = &clk_branch2_ops,
1181 static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1182 .halt_reg = 0x82028,
1183 .halt_check = BRANCH_HALT,
1185 .enable_reg = 0x82028,
1186 .enable_mask = BIT(0),
1187 .hw.init = &(struct clk_init_data){
1188 .name = "gcc_aggre1_ufs_axi_clk",
1189 .parent_names = (const char *[]){
1193 .flags = CLK_SET_RATE_PARENT,
1194 .ops = &clk_branch2_ops,
1199 static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1200 .halt_reg = 0x82024,
1201 .halt_check = BRANCH_HALT,
1203 .enable_reg = 0x82024,
1204 .enable_mask = BIT(0),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "gcc_aggre1_usb3_axi_clk",
1207 .parent_names = (const char *[]){
1208 "usb30_master_clk_src",
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1217 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1218 .halt_reg = 0x48090,
1219 .halt_check = BRANCH_HALT,
1221 .enable_reg = 0x48090,
1222 .enable_mask = BIT(0),
1223 .hw.init = &(struct clk_init_data){
1224 .name = "gcc_apss_qdss_tsctr_div2_clk",
1225 .ops = &clk_branch2_ops,
1230 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1231 .halt_reg = 0x48094,
1232 .halt_check = BRANCH_HALT,
1234 .enable_reg = 0x48094,
1235 .enable_mask = BIT(0),
1236 .hw.init = &(struct clk_init_data){
1237 .name = "gcc_apss_qdss_tsctr_div8_clk",
1238 .ops = &clk_branch2_ops,
1243 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1244 .halt_reg = 0x48004,
1245 .halt_check = BRANCH_HALT_VOTED,
1247 .enable_reg = 0x52004,
1248 .enable_mask = BIT(22),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "gcc_bimc_hmss_axi_clk",
1251 .ops = &clk_branch2_ops,
1256 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1257 .halt_reg = 0x4401c,
1258 .halt_check = BRANCH_HALT,
1260 .enable_reg = 0x4401c,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_bimc_mss_q6_axi_clk",
1264 .ops = &clk_branch2_ops,
1269 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1270 .halt_reg = 0x8a000,
1271 .halt_check = BRANCH_HALT,
1273 .enable_reg = 0x8a000,
1274 .enable_mask = BIT(0),
1275 .hw.init = &(struct clk_init_data){
1276 .name = "gcc_mss_cfg_ahb_clk",
1277 .ops = &clk_branch2_ops,
1282 static struct clk_branch gcc_mss_snoc_axi_clk = {
1283 .halt_reg = 0x8a03c,
1284 .halt_check = BRANCH_HALT,
1286 .enable_reg = 0x8a03c,
1287 .enable_mask = BIT(0),
1288 .hw.init = &(struct clk_init_data){
1289 .name = "gcc_mss_snoc_axi_clk",
1290 .ops = &clk_branch2_ops,
1295 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
1296 .halt_reg = 0x8a004,
1297 .halt_check = BRANCH_HALT,
1299 .enable_reg = 0x8a004,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "gcc_mss_mnoc_bimc_axi_clk",
1303 .ops = &clk_branch2_ops,
1308 static struct clk_branch gcc_boot_rom_ahb_clk = {
1309 .halt_reg = 0x38004,
1310 .halt_check = BRANCH_HALT_VOTED,
1311 .hwcg_reg = 0x38004,
1314 .enable_reg = 0x52004,
1315 .enable_mask = BIT(10),
1316 .hw.init = &(struct clk_init_data){
1317 .name = "gcc_boot_rom_ahb_clk",
1318 .ops = &clk_branch2_ops,
1323 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1324 .halt_check = BRANCH_HALT_DELAY,
1326 .enable_reg = 0x5200c,
1327 .enable_mask = BIT(2),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "gcc_mss_gpll0_div_clk_src",
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch gcc_blsp1_ahb_clk = {
1336 .halt_reg = 0x17004,
1337 .halt_check = BRANCH_HALT_VOTED,
1339 .enable_reg = 0x52004,
1340 .enable_mask = BIT(17),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_blsp1_ahb_clk",
1343 .ops = &clk_branch2_ops,
1348 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1349 .halt_reg = 0x19008,
1350 .halt_check = BRANCH_HALT,
1352 .enable_reg = 0x19008,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1356 .parent_names = (const char *[]){
1357 "blsp1_qup1_i2c_apps_clk_src",
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1366 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1367 .halt_reg = 0x19004,
1368 .halt_check = BRANCH_HALT,
1370 .enable_reg = 0x19004,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "gcc_blsp1_qup1_spi_apps_clk",
1374 .parent_names = (const char *[]){
1375 "blsp1_qup1_spi_apps_clk_src",
1378 .flags = CLK_SET_RATE_PARENT,
1379 .ops = &clk_branch2_ops,
1384 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1385 .halt_reg = 0x1b008,
1386 .halt_check = BRANCH_HALT,
1388 .enable_reg = 0x1b008,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1392 .parent_names = (const char *[]){
1393 "blsp1_qup2_i2c_apps_clk_src",
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1403 .halt_reg = 0x1b004,
1404 .halt_check = BRANCH_HALT,
1406 .enable_reg = 0x1b004,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "gcc_blsp1_qup2_spi_apps_clk",
1410 .parent_names = (const char *[]){
1411 "blsp1_qup2_spi_apps_clk_src",
1414 .flags = CLK_SET_RATE_PARENT,
1415 .ops = &clk_branch2_ops,
1420 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1421 .halt_reg = 0x1d008,
1422 .halt_check = BRANCH_HALT,
1424 .enable_reg = 0x1d008,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1428 .parent_names = (const char *[]){
1429 "blsp1_qup3_i2c_apps_clk_src",
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_branch2_ops,
1438 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1439 .halt_reg = 0x1d004,
1440 .halt_check = BRANCH_HALT,
1442 .enable_reg = 0x1d004,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "gcc_blsp1_qup3_spi_apps_clk",
1446 .parent_names = (const char *[]){
1447 "blsp1_qup3_spi_apps_clk_src",
1450 .flags = CLK_SET_RATE_PARENT,
1451 .ops = &clk_branch2_ops,
1456 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1457 .halt_reg = 0x1f008,
1458 .halt_check = BRANCH_HALT,
1460 .enable_reg = 0x1f008,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1464 .parent_names = (const char *[]){
1465 "blsp1_qup4_i2c_apps_clk_src",
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1474 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1475 .halt_reg = 0x1f004,
1476 .halt_check = BRANCH_HALT,
1478 .enable_reg = 0x1f004,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "gcc_blsp1_qup4_spi_apps_clk",
1482 .parent_names = (const char *[]){
1483 "blsp1_qup4_spi_apps_clk_src",
1486 .flags = CLK_SET_RATE_PARENT,
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1493 .halt_reg = 0x21008,
1494 .halt_check = BRANCH_HALT,
1496 .enable_reg = 0x21008,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1500 .parent_names = (const char *[]){
1501 "blsp1_qup5_i2c_apps_clk_src",
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1511 .halt_reg = 0x21004,
1512 .halt_check = BRANCH_HALT,
1514 .enable_reg = 0x21004,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_blsp1_qup5_spi_apps_clk",
1518 .parent_names = (const char *[]){
1519 "blsp1_qup5_spi_apps_clk_src",
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1528 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1529 .halt_reg = 0x23008,
1530 .halt_check = BRANCH_HALT,
1532 .enable_reg = 0x23008,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1536 .parent_names = (const char *[]){
1537 "blsp1_qup6_i2c_apps_clk_src",
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1546 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1547 .halt_reg = 0x23004,
1548 .halt_check = BRANCH_HALT,
1550 .enable_reg = 0x23004,
1551 .enable_mask = BIT(0),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "gcc_blsp1_qup6_spi_apps_clk",
1554 .parent_names = (const char *[]){
1555 "blsp1_qup6_spi_apps_clk_src",
1558 .flags = CLK_SET_RATE_PARENT,
1559 .ops = &clk_branch2_ops,
1564 static struct clk_branch gcc_blsp1_sleep_clk = {
1565 .halt_reg = 0x17008,
1566 .halt_check = BRANCH_HALT_VOTED,
1568 .enable_reg = 0x52004,
1569 .enable_mask = BIT(16),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "gcc_blsp1_sleep_clk",
1572 .ops = &clk_branch2_ops,
1577 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1578 .halt_reg = 0x1a004,
1579 .halt_check = BRANCH_HALT,
1581 .enable_reg = 0x1a004,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "gcc_blsp1_uart1_apps_clk",
1585 .parent_names = (const char *[]){
1586 "blsp1_uart1_apps_clk_src",
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1596 .halt_reg = 0x1c004,
1597 .halt_check = BRANCH_HALT,
1599 .enable_reg = 0x1c004,
1600 .enable_mask = BIT(0),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "gcc_blsp1_uart2_apps_clk",
1603 .parent_names = (const char *[]){
1604 "blsp1_uart2_apps_clk_src",
1607 .flags = CLK_SET_RATE_PARENT,
1608 .ops = &clk_branch2_ops,
1613 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1614 .halt_reg = 0x1e004,
1615 .halt_check = BRANCH_HALT,
1617 .enable_reg = 0x1e004,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_blsp1_uart3_apps_clk",
1621 .parent_names = (const char *[]){
1622 "blsp1_uart3_apps_clk_src",
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1631 static struct clk_branch gcc_blsp2_ahb_clk = {
1632 .halt_reg = 0x25004,
1633 .halt_check = BRANCH_HALT_VOTED,
1635 .enable_reg = 0x52004,
1636 .enable_mask = BIT(15),
1637 .hw.init = &(struct clk_init_data){
1638 .name = "gcc_blsp2_ahb_clk",
1639 .ops = &clk_branch2_ops,
1644 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1645 .halt_reg = 0x26008,
1646 .halt_check = BRANCH_HALT,
1648 .enable_reg = 0x26008,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1652 .parent_names = (const char *[]){
1653 "blsp2_qup1_i2c_apps_clk_src",
1656 .flags = CLK_SET_RATE_PARENT,
1657 .ops = &clk_branch2_ops,
1662 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1663 .halt_reg = 0x26004,
1664 .halt_check = BRANCH_HALT,
1666 .enable_reg = 0x26004,
1667 .enable_mask = BIT(0),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "gcc_blsp2_qup1_spi_apps_clk",
1670 .parent_names = (const char *[]){
1671 "blsp2_qup1_spi_apps_clk_src",
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1681 .halt_reg = 0x28008,
1682 .halt_check = BRANCH_HALT,
1684 .enable_reg = 0x28008,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1688 .parent_names = (const char *[]){
1689 "blsp2_qup2_i2c_apps_clk_src",
1692 .flags = CLK_SET_RATE_PARENT,
1693 .ops = &clk_branch2_ops,
1698 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1699 .halt_reg = 0x28004,
1700 .halt_check = BRANCH_HALT,
1702 .enable_reg = 0x28004,
1703 .enable_mask = BIT(0),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "gcc_blsp2_qup2_spi_apps_clk",
1706 .parent_names = (const char *[]){
1707 "blsp2_qup2_spi_apps_clk_src",
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1716 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1717 .halt_reg = 0x2a008,
1718 .halt_check = BRANCH_HALT,
1720 .enable_reg = 0x2a008,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1724 .parent_names = (const char *[]){
1725 "blsp2_qup3_i2c_apps_clk_src",
1728 .flags = CLK_SET_RATE_PARENT,
1729 .ops = &clk_branch2_ops,
1734 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1735 .halt_reg = 0x2a004,
1736 .halt_check = BRANCH_HALT,
1738 .enable_reg = 0x2a004,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gcc_blsp2_qup3_spi_apps_clk",
1742 .parent_names = (const char *[]){
1743 "blsp2_qup3_spi_apps_clk_src",
1746 .flags = CLK_SET_RATE_PARENT,
1747 .ops = &clk_branch2_ops,
1752 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1753 .halt_reg = 0x2c008,
1754 .halt_check = BRANCH_HALT,
1756 .enable_reg = 0x2c008,
1757 .enable_mask = BIT(0),
1758 .hw.init = &(struct clk_init_data){
1759 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1760 .parent_names = (const char *[]){
1761 "blsp2_qup4_i2c_apps_clk_src",
1764 .flags = CLK_SET_RATE_PARENT,
1765 .ops = &clk_branch2_ops,
1770 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1771 .halt_reg = 0x2c004,
1772 .halt_check = BRANCH_HALT,
1774 .enable_reg = 0x2c004,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_blsp2_qup4_spi_apps_clk",
1778 .parent_names = (const char *[]){
1779 "blsp2_qup4_spi_apps_clk_src",
1782 .flags = CLK_SET_RATE_PARENT,
1783 .ops = &clk_branch2_ops,
1788 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1789 .halt_reg = 0x2e008,
1790 .halt_check = BRANCH_HALT,
1792 .enable_reg = 0x2e008,
1793 .enable_mask = BIT(0),
1794 .hw.init = &(struct clk_init_data){
1795 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1796 .parent_names = (const char *[]){
1797 "blsp2_qup5_i2c_apps_clk_src",
1800 .flags = CLK_SET_RATE_PARENT,
1801 .ops = &clk_branch2_ops,
1806 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1807 .halt_reg = 0x2e004,
1808 .halt_check = BRANCH_HALT,
1810 .enable_reg = 0x2e004,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "gcc_blsp2_qup5_spi_apps_clk",
1814 .parent_names = (const char *[]){
1815 "blsp2_qup5_spi_apps_clk_src",
1818 .flags = CLK_SET_RATE_PARENT,
1819 .ops = &clk_branch2_ops,
1824 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1825 .halt_reg = 0x30008,
1826 .halt_check = BRANCH_HALT,
1828 .enable_reg = 0x30008,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1832 .parent_names = (const char *[]){
1833 "blsp2_qup6_i2c_apps_clk_src",
1836 .flags = CLK_SET_RATE_PARENT,
1837 .ops = &clk_branch2_ops,
1842 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1843 .halt_reg = 0x30004,
1844 .halt_check = BRANCH_HALT,
1846 .enable_reg = 0x30004,
1847 .enable_mask = BIT(0),
1848 .hw.init = &(struct clk_init_data){
1849 .name = "gcc_blsp2_qup6_spi_apps_clk",
1850 .parent_names = (const char *[]){
1851 "blsp2_qup6_spi_apps_clk_src",
1854 .flags = CLK_SET_RATE_PARENT,
1855 .ops = &clk_branch2_ops,
1860 static struct clk_branch gcc_blsp2_sleep_clk = {
1861 .halt_reg = 0x25008,
1862 .halt_check = BRANCH_HALT_VOTED,
1864 .enable_reg = 0x52004,
1865 .enable_mask = BIT(14),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "gcc_blsp2_sleep_clk",
1868 .ops = &clk_branch2_ops,
1873 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1874 .halt_reg = 0x27004,
1875 .halt_check = BRANCH_HALT,
1877 .enable_reg = 0x27004,
1878 .enable_mask = BIT(0),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "gcc_blsp2_uart1_apps_clk",
1881 .parent_names = (const char *[]){
1882 "blsp2_uart1_apps_clk_src",
1885 .flags = CLK_SET_RATE_PARENT,
1886 .ops = &clk_branch2_ops,
1891 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1892 .halt_reg = 0x29004,
1893 .halt_check = BRANCH_HALT,
1895 .enable_reg = 0x29004,
1896 .enable_mask = BIT(0),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "gcc_blsp2_uart2_apps_clk",
1899 .parent_names = (const char *[]){
1900 "blsp2_uart2_apps_clk_src",
1903 .flags = CLK_SET_RATE_PARENT,
1904 .ops = &clk_branch2_ops,
1909 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1910 .halt_reg = 0x2b004,
1911 .halt_check = BRANCH_HALT,
1913 .enable_reg = 0x2b004,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "gcc_blsp2_uart3_apps_clk",
1917 .parent_names = (const char *[]){
1918 "blsp2_uart3_apps_clk_src",
1921 .flags = CLK_SET_RATE_PARENT,
1922 .ops = &clk_branch2_ops,
1927 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1929 .halt_check = BRANCH_HALT,
1931 .enable_reg = 0x5018,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "gcc_cfg_noc_usb3_axi_clk",
1935 .parent_names = (const char *[]){
1936 "usb30_master_clk_src",
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1945 static struct clk_branch gcc_gp1_clk = {
1946 .halt_reg = 0x64000,
1947 .halt_check = BRANCH_HALT,
1949 .enable_reg = 0x64000,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "gcc_gp1_clk",
1953 .parent_names = (const char *[]){
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1963 static struct clk_branch gcc_gp2_clk = {
1964 .halt_reg = 0x65000,
1965 .halt_check = BRANCH_HALT,
1967 .enable_reg = 0x65000,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "gcc_gp2_clk",
1971 .parent_names = (const char *[]){
1975 .flags = CLK_SET_RATE_PARENT,
1976 .ops = &clk_branch2_ops,
1981 static struct clk_branch gcc_gp3_clk = {
1982 .halt_reg = 0x66000,
1983 .halt_check = BRANCH_HALT,
1985 .enable_reg = 0x66000,
1986 .enable_mask = BIT(0),
1987 .hw.init = &(struct clk_init_data){
1988 .name = "gcc_gp3_clk",
1989 .parent_names = (const char *[]){
1993 .flags = CLK_SET_RATE_PARENT,
1994 .ops = &clk_branch2_ops,
1999 static struct clk_branch gcc_bimc_gfx_clk = {
2000 .halt_reg = 0x46040,
2001 .halt_check = BRANCH_HALT,
2003 .enable_reg = 0x46040,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "gcc_bimc_gfx_clk",
2007 .ops = &clk_branch2_ops,
2012 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
2013 .halt_reg = 0x71010,
2014 .halt_check = BRANCH_HALT,
2016 .enable_reg = 0x71010,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "gcc_gpu_bimc_gfx_clk",
2020 .ops = &clk_branch2_ops,
2025 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
2026 .halt_reg = 0x7100c,
2027 .halt_check = BRANCH_HALT,
2029 .enable_reg = 0x7100c,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_gpu_bimc_gfx_src_clk",
2033 .ops = &clk_branch2_ops,
2038 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2039 .halt_reg = 0x71004,
2040 .halt_check = BRANCH_HALT,
2042 .enable_reg = 0x71004,
2043 .enable_mask = BIT(0),
2044 .hw.init = &(struct clk_init_data){
2045 .name = "gcc_gpu_cfg_ahb_clk",
2046 .ops = &clk_branch2_ops,
2051 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2052 .halt_reg = 0x71018,
2053 .halt_check = BRANCH_HALT,
2055 .enable_reg = 0x71018,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "gcc_gpu_snoc_dvm_gfx_clk",
2059 .ops = &clk_branch2_ops,
2064 static struct clk_branch gcc_hmss_ahb_clk = {
2065 .halt_reg = 0x48000,
2066 .halt_check = BRANCH_HALT_VOTED,
2068 .enable_reg = 0x52004,
2069 .enable_mask = BIT(21),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "gcc_hmss_ahb_clk",
2072 .parent_names = (const char *[]){
2076 .flags = CLK_SET_RATE_PARENT,
2077 .ops = &clk_branch2_ops,
2082 static struct clk_branch gcc_hmss_at_clk = {
2083 .halt_reg = 0x48010,
2084 .halt_check = BRANCH_HALT,
2086 .enable_reg = 0x48010,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "gcc_hmss_at_clk",
2090 .ops = &clk_branch2_ops,
2095 static struct clk_branch gcc_hmss_rbcpr_clk = {
2096 .halt_reg = 0x48008,
2097 .halt_check = BRANCH_HALT,
2099 .enable_reg = 0x48008,
2100 .enable_mask = BIT(0),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "gcc_hmss_rbcpr_clk",
2103 .parent_names = (const char *[]){
2104 "hmss_rbcpr_clk_src",
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2113 static struct clk_branch gcc_hmss_trig_clk = {
2114 .halt_reg = 0x4800c,
2115 .halt_check = BRANCH_HALT,
2117 .enable_reg = 0x4800c,
2118 .enable_mask = BIT(0),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "gcc_hmss_trig_clk",
2121 .ops = &clk_branch2_ops,
2126 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2128 .halt_check = BRANCH_HALT,
2130 .enable_reg = 0x9004,
2131 .enable_mask = BIT(0),
2132 .hw.init = &(struct clk_init_data){
2133 .name = "gcc_mmss_noc_cfg_ahb_clk",
2134 .ops = &clk_branch2_ops,
2136 * Any access to mmss depends on this clock.
2137 * Gating this clock has been shown to crash the system
2138 * when mmssnoc_axi_rpm_clk is inited in rpmcc.
2140 .flags = CLK_IS_CRITICAL,
2145 static struct clk_branch gcc_mmss_qm_ahb_clk = {
2147 .halt_check = BRANCH_HALT,
2149 .enable_reg = 0x9030,
2150 .enable_mask = BIT(0),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_mmss_qm_ahb_clk",
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch gcc_mmss_qm_core_clk = {
2160 .halt_check = BRANCH_HALT,
2162 .enable_reg = 0x900c,
2163 .enable_mask = BIT(0),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gcc_mmss_qm_core_clk",
2166 .ops = &clk_branch2_ops,
2171 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2173 .halt_check = BRANCH_HALT,
2175 .enable_reg = 0x9000,
2176 .enable_mask = BIT(0),
2177 .hw.init = &(struct clk_init_data){
2178 .name = "gcc_mmss_sys_noc_axi_clk",
2179 .ops = &clk_branch2_ops,
2184 static struct clk_branch gcc_mss_at_clk = {
2185 .halt_reg = 0x8a00c,
2186 .halt_check = BRANCH_HALT,
2188 .enable_reg = 0x8a00c,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "gcc_mss_at_clk",
2192 .ops = &clk_branch2_ops,
2197 static struct clk_branch gcc_pcie_0_aux_clk = {
2198 .halt_reg = 0x6b014,
2199 .halt_check = BRANCH_HALT,
2201 .enable_reg = 0x6b014,
2202 .enable_mask = BIT(0),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "gcc_pcie_0_aux_clk",
2205 .parent_names = (const char *[]){
2209 .flags = CLK_SET_RATE_PARENT,
2210 .ops = &clk_branch2_ops,
2215 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2216 .halt_reg = 0x6b010,
2217 .halt_check = BRANCH_HALT,
2219 .enable_reg = 0x6b010,
2220 .enable_mask = BIT(0),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "gcc_pcie_0_cfg_ahb_clk",
2223 .ops = &clk_branch2_ops,
2228 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2229 .halt_reg = 0x6b00c,
2230 .halt_check = BRANCH_HALT,
2232 .enable_reg = 0x6b00c,
2233 .enable_mask = BIT(0),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "gcc_pcie_0_mstr_axi_clk",
2236 .ops = &clk_branch2_ops,
2241 static struct clk_branch gcc_pcie_0_pipe_clk = {
2242 .halt_reg = 0x6b018,
2243 .halt_check = BRANCH_HALT_SKIP,
2245 .enable_reg = 0x6b018,
2246 .enable_mask = BIT(0),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "gcc_pcie_0_pipe_clk",
2249 .ops = &clk_branch2_ops,
2254 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2255 .halt_reg = 0x6b008,
2256 .halt_check = BRANCH_HALT,
2258 .enable_reg = 0x6b008,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "gcc_pcie_0_slv_axi_clk",
2262 .ops = &clk_branch2_ops,
2267 static struct clk_branch gcc_pcie_phy_aux_clk = {
2268 .halt_reg = 0x6f004,
2269 .halt_check = BRANCH_HALT,
2271 .enable_reg = 0x6f004,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "gcc_pcie_phy_aux_clk",
2275 .parent_names = (const char *[]){
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2285 static struct clk_branch gcc_pdm2_clk = {
2286 .halt_reg = 0x3300c,
2287 .halt_check = BRANCH_HALT,
2289 .enable_reg = 0x3300c,
2290 .enable_mask = BIT(0),
2291 .hw.init = &(struct clk_init_data){
2292 .name = "gcc_pdm2_clk",
2293 .parent_names = (const char *[]){
2297 .flags = CLK_SET_RATE_PARENT,
2298 .ops = &clk_branch2_ops,
2303 static struct clk_branch gcc_pdm_ahb_clk = {
2304 .halt_reg = 0x33004,
2305 .halt_check = BRANCH_HALT,
2307 .enable_reg = 0x33004,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "gcc_pdm_ahb_clk",
2311 .ops = &clk_branch2_ops,
2316 static struct clk_branch gcc_pdm_xo4_clk = {
2317 .halt_reg = 0x33008,
2318 .halt_check = BRANCH_HALT,
2320 .enable_reg = 0x33008,
2321 .enable_mask = BIT(0),
2322 .hw.init = &(struct clk_init_data){
2323 .name = "gcc_pdm_xo4_clk",
2324 .ops = &clk_branch2_ops,
2329 static struct clk_branch gcc_prng_ahb_clk = {
2330 .halt_reg = 0x34004,
2331 .halt_check = BRANCH_HALT_VOTED,
2333 .enable_reg = 0x52004,
2334 .enable_mask = BIT(13),
2335 .hw.init = &(struct clk_init_data){
2336 .name = "gcc_prng_ahb_clk",
2337 .ops = &clk_branch2_ops,
2342 static struct clk_branch gcc_sdcc2_ahb_clk = {
2343 .halt_reg = 0x14008,
2344 .halt_check = BRANCH_HALT,
2346 .enable_reg = 0x14008,
2347 .enable_mask = BIT(0),
2348 .hw.init = &(struct clk_init_data){
2349 .name = "gcc_sdcc2_ahb_clk",
2350 .ops = &clk_branch2_ops,
2355 static struct clk_branch gcc_sdcc2_apps_clk = {
2356 .halt_reg = 0x14004,
2357 .halt_check = BRANCH_HALT,
2359 .enable_reg = 0x14004,
2360 .enable_mask = BIT(0),
2361 .hw.init = &(struct clk_init_data){
2362 .name = "gcc_sdcc2_apps_clk",
2363 .parent_names = (const char *[]){
2364 "sdcc2_apps_clk_src",
2367 .flags = CLK_SET_RATE_PARENT,
2368 .ops = &clk_branch2_ops,
2373 static struct clk_branch gcc_sdcc4_ahb_clk = {
2374 .halt_reg = 0x16008,
2375 .halt_check = BRANCH_HALT,
2377 .enable_reg = 0x16008,
2378 .enable_mask = BIT(0),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "gcc_sdcc4_ahb_clk",
2381 .ops = &clk_branch2_ops,
2386 static struct clk_branch gcc_sdcc4_apps_clk = {
2387 .halt_reg = 0x16004,
2388 .halt_check = BRANCH_HALT,
2390 .enable_reg = 0x16004,
2391 .enable_mask = BIT(0),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "gcc_sdcc4_apps_clk",
2394 .parent_names = (const char *[]){
2395 "sdcc4_apps_clk_src",
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_branch2_ops,
2404 static struct clk_branch gcc_tsif_ahb_clk = {
2405 .halt_reg = 0x36004,
2406 .halt_check = BRANCH_HALT,
2408 .enable_reg = 0x36004,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_tsif_ahb_clk",
2412 .ops = &clk_branch2_ops,
2417 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2418 .halt_reg = 0x3600c,
2419 .halt_check = BRANCH_HALT,
2421 .enable_reg = 0x3600c,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_tsif_inactivity_timers_clk",
2425 .ops = &clk_branch2_ops,
2430 static struct clk_branch gcc_tsif_ref_clk = {
2431 .halt_reg = 0x36008,
2432 .halt_check = BRANCH_HALT,
2434 .enable_reg = 0x36008,
2435 .enable_mask = BIT(0),
2436 .hw.init = &(struct clk_init_data){
2437 .name = "gcc_tsif_ref_clk",
2438 .parent_names = (const char *[]){
2442 .flags = CLK_SET_RATE_PARENT,
2443 .ops = &clk_branch2_ops,
2448 static struct clk_branch gcc_ufs_ahb_clk = {
2449 .halt_reg = 0x7500c,
2450 .halt_check = BRANCH_HALT,
2452 .enable_reg = 0x7500c,
2453 .enable_mask = BIT(0),
2454 .hw.init = &(struct clk_init_data){
2455 .name = "gcc_ufs_ahb_clk",
2456 .ops = &clk_branch2_ops,
2461 static struct clk_branch gcc_ufs_axi_clk = {
2462 .halt_reg = 0x75008,
2463 .halt_check = BRANCH_HALT,
2465 .enable_reg = 0x75008,
2466 .enable_mask = BIT(0),
2467 .hw.init = &(struct clk_init_data){
2468 .name = "gcc_ufs_axi_clk",
2469 .parent_names = (const char *[]){
2473 .flags = CLK_SET_RATE_PARENT,
2474 .ops = &clk_branch2_ops,
2479 static struct clk_branch gcc_ufs_ice_core_clk = {
2480 .halt_reg = 0x7600c,
2481 .halt_check = BRANCH_HALT,
2483 .enable_reg = 0x7600c,
2484 .enable_mask = BIT(0),
2485 .hw.init = &(struct clk_init_data){
2486 .name = "gcc_ufs_ice_core_clk",
2487 .ops = &clk_branch2_ops,
2492 static struct clk_branch gcc_ufs_phy_aux_clk = {
2493 .halt_reg = 0x76040,
2494 .halt_check = BRANCH_HALT,
2496 .enable_reg = 0x76040,
2497 .enable_mask = BIT(0),
2498 .hw.init = &(struct clk_init_data){
2499 .name = "gcc_ufs_phy_aux_clk",
2500 .ops = &clk_branch2_ops,
2505 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2506 .halt_reg = 0x75014,
2507 .halt_check = BRANCH_HALT_SKIP,
2509 .enable_reg = 0x75014,
2510 .enable_mask = BIT(0),
2511 .hw.init = &(struct clk_init_data){
2512 .name = "gcc_ufs_rx_symbol_0_clk",
2513 .ops = &clk_branch2_ops,
2518 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2519 .halt_reg = 0x7605c,
2520 .halt_check = BRANCH_HALT_SKIP,
2522 .enable_reg = 0x7605c,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "gcc_ufs_rx_symbol_1_clk",
2526 .ops = &clk_branch2_ops,
2531 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2532 .halt_reg = 0x75010,
2533 .halt_check = BRANCH_HALT_SKIP,
2535 .enable_reg = 0x75010,
2536 .enable_mask = BIT(0),
2537 .hw.init = &(struct clk_init_data){
2538 .name = "gcc_ufs_tx_symbol_0_clk",
2539 .ops = &clk_branch2_ops,
2544 static struct clk_branch gcc_ufs_unipro_core_clk = {
2545 .halt_reg = 0x76008,
2546 .halt_check = BRANCH_HALT,
2548 .enable_reg = 0x76008,
2549 .enable_mask = BIT(0),
2550 .hw.init = &(struct clk_init_data){
2551 .name = "gcc_ufs_unipro_core_clk",
2552 .ops = &clk_branch2_ops,
2557 static struct clk_branch gcc_usb30_master_clk = {
2559 .halt_check = BRANCH_HALT,
2561 .enable_reg = 0xf008,
2562 .enable_mask = BIT(0),
2563 .hw.init = &(struct clk_init_data){
2564 .name = "gcc_usb30_master_clk",
2565 .parent_names = (const char *[]){
2566 "usb30_master_clk_src",
2569 .flags = CLK_SET_RATE_PARENT,
2570 .ops = &clk_branch2_ops,
2575 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2577 .halt_check = BRANCH_HALT,
2579 .enable_reg = 0xf010,
2580 .enable_mask = BIT(0),
2581 .hw.init = &(struct clk_init_data){
2582 .name = "gcc_usb30_mock_utmi_clk",
2583 .parent_names = (const char *[]){
2584 "usb30_mock_utmi_clk_src",
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2593 static struct clk_branch gcc_usb30_sleep_clk = {
2595 .halt_check = BRANCH_HALT,
2597 .enable_reg = 0xf00c,
2598 .enable_mask = BIT(0),
2599 .hw.init = &(struct clk_init_data){
2600 .name = "gcc_usb30_sleep_clk",
2601 .ops = &clk_branch2_ops,
2606 static struct clk_branch gcc_usb3_phy_aux_clk = {
2607 .halt_reg = 0x50000,
2608 .halt_check = BRANCH_HALT,
2610 .enable_reg = 0x50000,
2611 .enable_mask = BIT(0),
2612 .hw.init = &(struct clk_init_data){
2613 .name = "gcc_usb3_phy_aux_clk",
2614 .parent_names = (const char *[]){
2615 "usb3_phy_aux_clk_src",
2618 .flags = CLK_SET_RATE_PARENT,
2619 .ops = &clk_branch2_ops,
2624 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2625 .halt_reg = 0x50004,
2626 .halt_check = BRANCH_HALT_SKIP,
2628 .enable_reg = 0x50004,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "gcc_usb3_phy_pipe_clk",
2632 .ops = &clk_branch2_ops,
2637 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2638 .halt_reg = 0x6a004,
2639 .halt_check = BRANCH_HALT,
2641 .enable_reg = 0x6a004,
2642 .enable_mask = BIT(0),
2643 .hw.init = &(struct clk_init_data){
2644 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2645 .ops = &clk_branch2_ops,
2650 static struct clk_branch gcc_hdmi_clkref_clk = {
2651 .halt_reg = 0x88000,
2653 .enable_reg = 0x88000,
2654 .enable_mask = BIT(0),
2655 .hw.init = &(struct clk_init_data){
2656 .name = "gcc_hdmi_clkref_clk",
2657 .parent_names = (const char *[]){ "xo" },
2659 .ops = &clk_branch2_ops,
2664 static struct clk_branch gcc_ufs_clkref_clk = {
2665 .halt_reg = 0x88004,
2667 .enable_reg = 0x88004,
2668 .enable_mask = BIT(0),
2669 .hw.init = &(struct clk_init_data){
2670 .name = "gcc_ufs_clkref_clk",
2671 .parent_names = (const char *[]){ "xo" },
2673 .ops = &clk_branch2_ops,
2678 static struct clk_branch gcc_usb3_clkref_clk = {
2679 .halt_reg = 0x88008,
2681 .enable_reg = 0x88008,
2682 .enable_mask = BIT(0),
2683 .hw.init = &(struct clk_init_data){
2684 .name = "gcc_usb3_clkref_clk",
2685 .parent_names = (const char *[]){ "xo" },
2687 .ops = &clk_branch2_ops,
2692 static struct clk_branch gcc_pcie_clkref_clk = {
2693 .halt_reg = 0x8800c,
2695 .enable_reg = 0x8800c,
2696 .enable_mask = BIT(0),
2697 .hw.init = &(struct clk_init_data){
2698 .name = "gcc_pcie_clkref_clk",
2699 .parent_names = (const char *[]){ "xo" },
2701 .ops = &clk_branch2_ops,
2706 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
2707 .halt_reg = 0x88014,
2709 .enable_reg = 0x88014,
2710 .enable_mask = BIT(0),
2711 .hw.init = &(struct clk_init_data){
2712 .name = "gcc_rx1_usb2_clkref_clk",
2713 .parent_names = (const char *[]){ "xo" },
2715 .ops = &clk_branch2_ops,
2720 static struct gdsc pcie_0_gdsc = {
2724 .name = "pcie_0_gdsc",
2726 .pwrsts = PWRSTS_OFF_ON,
2730 static struct gdsc ufs_gdsc = {
2736 .pwrsts = PWRSTS_OFF_ON,
2740 static struct gdsc usb_30_gdsc = {
2744 .name = "usb_30_gdsc",
2746 .pwrsts = PWRSTS_OFF_ON,
2750 static struct clk_regmap *gcc_msm8998_clocks[] = {
2751 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2752 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2753 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2754 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2755 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2756 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2757 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2758 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2759 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2760 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2761 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2762 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2763 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2764 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2765 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2766 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2767 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2768 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2769 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2770 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2771 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2772 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2773 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2774 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2775 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2776 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2777 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2778 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2779 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2780 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2781 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2782 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2783 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2784 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2785 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2786 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2787 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2788 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2789 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2790 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2791 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2792 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2793 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2794 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2795 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2796 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2797 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2798 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2799 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2800 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2801 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2802 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2803 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2804 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2805 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2806 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2807 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2808 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2809 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2810 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2811 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2812 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2813 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2814 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2815 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2816 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2817 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2818 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2819 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2820 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2821 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2822 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2823 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2824 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2825 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2826 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2827 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2828 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2829 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2830 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2831 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2832 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2833 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2834 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2835 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2836 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2837 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2838 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2839 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2840 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2841 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2842 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2843 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2844 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2845 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2846 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2847 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2848 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2849 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2850 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2851 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2852 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2853 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2854 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2855 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2856 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2857 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2858 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2859 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2860 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2861 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2862 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2863 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2864 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2865 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2866 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2867 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2868 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2869 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2870 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2871 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2872 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2873 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2874 [GPLL0] = &gpll0.clkr,
2875 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2876 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2877 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2878 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2879 [GPLL1] = &gpll1.clkr,
2880 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2881 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2882 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2883 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2884 [GPLL2] = &gpll2.clkr,
2885 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2886 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2887 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2888 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2889 [GPLL3] = &gpll3.clkr,
2890 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2891 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2892 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2893 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2894 [GPLL4] = &gpll4.clkr,
2895 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2896 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2897 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2898 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2899 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2900 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2901 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2902 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2903 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2904 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2905 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2906 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2907 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2908 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2909 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2910 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
2911 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2912 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2913 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
2914 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2915 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2916 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2917 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
2918 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2919 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2922 static struct gdsc *gcc_msm8998_gdscs[] = {
2923 [PCIE_0_GDSC] = &pcie_0_gdsc,
2924 [UFS_GDSC] = &ufs_gdsc,
2925 [USB_30_GDSC] = &usb_30_gdsc,
2928 static const struct qcom_reset_map gcc_msm8998_resets[] = {
2929 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
2930 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
2931 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
2932 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
2933 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
2934 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
2935 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
2936 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
2937 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
2938 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
2939 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
2940 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
2941 [GCC_PCIE_0_BCR] = { 0x6b000 },
2942 [GCC_PDM_BCR] = { 0x33000 },
2943 [GCC_SDCC2_BCR] = { 0x14000 },
2944 [GCC_SDCC4_BCR] = { 0x16000 },
2945 [GCC_TSIF_BCR] = { 0x36000 },
2946 [GCC_UFS_BCR] = { 0x75000 },
2947 [GCC_USB_30_BCR] = { 0xf000 },
2948 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
2949 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
2950 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
2951 [GCC_IMEM_BCR] = { 0x8000 },
2952 [GCC_PIMEM_BCR] = { 0xa000 },
2953 [GCC_MMSS_BCR] = { 0xb000 },
2954 [GCC_QDSS_BCR] = { 0xc000 },
2955 [GCC_WCSS_BCR] = { 0x11000 },
2956 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2957 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2958 [GCC_BLSP1_BCR] = { 0x17000 },
2959 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
2960 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
2961 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
2962 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
2963 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
2964 [GCC_BLSP2_BCR] = { 0x25000 },
2965 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
2966 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
2967 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
2968 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
2969 [GCC_PRNG_BCR] = { 0x34000 },
2970 [GCC_TSIF_0_RESET] = { 0x36024 },
2971 [GCC_TSIF_1_RESET] = { 0x36028 },
2972 [GCC_TCSR_BCR] = { 0x37000 },
2973 [GCC_BOOT_ROM_BCR] = { 0x38000 },
2974 [GCC_MSG_RAM_BCR] = { 0x39000 },
2975 [GCC_TLMM_BCR] = { 0x3a000 },
2976 [GCC_MPM_BCR] = { 0x3b000 },
2977 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
2978 [GCC_SPMI_BCR] = { 0x3f000 },
2979 [GCC_SPDM_BCR] = { 0x40000 },
2980 [GCC_CE1_BCR] = { 0x41000 },
2981 [GCC_BIMC_BCR] = { 0x44000 },
2982 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
2983 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
2984 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
2985 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
2986 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
2987 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
2988 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
2989 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
2990 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
2991 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
2992 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
2993 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
2994 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
2995 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
2996 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
2997 [GCC_APB2JTAG_BCR] = { 0x4c000 },
2998 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
2999 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3000 [GCC_USB3_PHY_BCR] = { 0x50020 },
3001 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3002 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
3003 [GCC_SSC_BCR] = { 0x63000 },
3004 [GCC_SSC_RESET] = { 0x63020 },
3005 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3006 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3007 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3008 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3009 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3010 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
3011 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
3012 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3013 [GCC_GPU_BCR] = { 0x71000 },
3014 [GCC_SPSS_BCR] = { 0x72000 },
3015 [GCC_OBT_ODT_BCR] = { 0x73000 },
3016 [GCC_MSS_RESTART] = { 0x79000 },
3017 [GCC_VS_BCR] = { 0x7a000 },
3018 [GCC_MSS_VS_RESET] = { 0x7a100 },
3019 [GCC_GPU_VS_RESET] = { 0x7a104 },
3020 [GCC_APC0_VS_RESET] = { 0x7a108 },
3021 [GCC_APC1_VS_RESET] = { 0x7a10c },
3022 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3023 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3024 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
3025 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
3026 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
3027 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
3028 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
3029 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
3030 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3031 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3032 [GCC_DCC_BCR] = { 0x84000 },
3033 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
3034 [GCC_IPA_BCR] = { 0x89000 },
3035 [GCC_GLM_BCR] = { 0x8b000 },
3036 [GCC_SKL_BCR] = { 0x8c000 },
3037 [GCC_MSMPU_BCR] = { 0x8d000 },
3040 static const struct regmap_config gcc_msm8998_regmap_config = {
3044 .max_register = 0x8f000,
3048 static struct clk_hw *gcc_msm8998_hws[] = {
3052 static const struct qcom_cc_desc gcc_msm8998_desc = {
3053 .config = &gcc_msm8998_regmap_config,
3054 .clks = gcc_msm8998_clocks,
3055 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
3056 .resets = gcc_msm8998_resets,
3057 .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
3058 .gdscs = gcc_msm8998_gdscs,
3059 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
3060 .clk_hws = gcc_msm8998_hws,
3061 .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
3064 static int gcc_msm8998_probe(struct platform_device *pdev)
3066 struct regmap *regmap;
3069 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
3071 return PTR_ERR(regmap);
3074 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3075 * turned off by hardware during certain apps low power modes.
3077 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3081 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
3084 static const struct of_device_id gcc_msm8998_match_table[] = {
3085 { .compatible = "qcom,gcc-msm8998" },
3088 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
3090 static struct platform_driver gcc_msm8998_driver = {
3091 .probe = gcc_msm8998_probe,
3093 .name = "gcc-msm8998",
3094 .of_match_table = gcc_msm8998_match_table,
3098 static int __init gcc_msm8998_init(void)
3100 return platform_driver_register(&gcc_msm8998_driver);
3102 core_initcall(gcc_msm8998_init);
3104 static void __exit gcc_msm8998_exit(void)
3106 platform_driver_unregister(&gcc_msm8998_driver);
3108 module_exit(gcc_msm8998_exit);
3110 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
3111 MODULE_LICENSE("GPL v2");
3112 MODULE_ALIAS("platform:gcc-msm8998");