1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 #include <linux/kernel.h>
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
11 #include <linux/of_device.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/slab.h>
16 #include "clk-krait.h"
18 static unsigned int sec_mux_map[] = {
23 static unsigned int pri_mux_map[] = {
30 * Notifier function for switching the muxes to safe parent
31 * while the hfpll is getting reprogrammed.
33 static int krait_notifier_cb(struct notifier_block *nb,
38 struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
40 /* Switch to safe parent */
41 if (event == PRE_RATE_CHANGE) {
42 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
43 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
44 mux->reparent = false;
46 * By the time POST_RATE_CHANGE notifier is called,
47 * clk framework itself would have changed the parent for the new rate.
48 * Only otherwise, put back to the old parent.
50 } else if (event == POST_RATE_CHANGE) {
52 ret = krait_mux_clk_ops.set_parent(&mux->hw,
56 return notifier_from_errno(ret);
59 static int krait_notifier_register(struct device *dev, struct clk *clk,
60 struct krait_mux_clk *mux)
64 mux->clk_nb.notifier_call = krait_notifier_cb;
65 ret = clk_notifier_register(clk, &mux->clk_nb);
67 dev_err(dev, "failed to register clock notifier: %d\n", ret);
73 krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
75 struct krait_div2_clk *div;
76 struct clk_init_data init = {
78 .ops = &krait_div2_clk_ops,
79 .flags = CLK_SET_RATE_PARENT,
81 const char *p_names[1];
84 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
94 init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
98 init.parent_names = p_names;
99 p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
105 clk = devm_clk_register(dev, &div->hw);
109 return PTR_ERR_OR_ZERO(clk);
113 krait_add_sec_mux(struct device *dev, int id, const char *s,
114 unsigned int offset, bool unique_aux)
117 struct krait_mux_clk *mux;
118 static const char *sec_mux_list[] = {
122 struct clk_init_data init = {
123 .parent_names = sec_mux_list,
124 .num_parents = ARRAY_SIZE(sec_mux_list),
125 .ops = &krait_mux_clk_ops,
126 .flags = CLK_SET_RATE_PARENT,
130 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
134 mux->offset = offset;
138 mux->parent_map = sec_mux_map;
139 mux->hw.init = &init;
142 init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
147 sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
148 if (!sec_mux_list[0]) {
149 clk = ERR_PTR(-ENOMEM);
154 clk = devm_clk_register(dev, &mux->hw);
156 ret = krait_notifier_register(dev, clk, mux);
162 kfree(sec_mux_list[0]);
165 return PTR_ERR_OR_ZERO(clk);
169 krait_add_pri_mux(struct device *dev, int id, const char *s,
173 struct krait_mux_clk *mux;
174 const char *p_names[3];
175 struct clk_init_data init = {
176 .parent_names = p_names,
177 .num_parents = ARRAY_SIZE(p_names),
178 .ops = &krait_mux_clk_ops,
179 .flags = CLK_SET_RATE_PARENT,
183 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
185 return ERR_PTR(-ENOMEM);
189 mux->offset = offset;
191 mux->parent_map = pri_mux_map;
192 mux->hw.init = &init;
195 init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
197 return ERR_PTR(-ENOMEM);
199 p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
201 clk = ERR_PTR(-ENOMEM);
205 p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
207 clk = ERR_PTR(-ENOMEM);
211 p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
213 clk = ERR_PTR(-ENOMEM);
217 clk = devm_clk_register(dev, &mux->hw);
219 ret = krait_notifier_register(dev, clk, mux);
233 /* id < 0 for L2, otherwise id == physical CPU number */
234 static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
243 offset = 0x4501 + (0x1000 * id);
244 s = p = kasprintf(GFP_KERNEL, "%d", id);
246 return ERR_PTR(-ENOMEM);
252 ret = krait_add_div(dev, id, s, offset);
258 ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
264 clk = krait_add_pri_mux(dev, id, s, offset);
270 static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
272 unsigned int idx = clkspec->args[0];
273 struct clk **clks = data;
276 pr_err("%s: invalid clock index %d\n", __func__, idx);
277 return ERR_PTR(-EINVAL);
280 return clks[idx] ? : ERR_PTR(-ENODEV);
283 static const struct of_device_id krait_cc_match_table[] = {
284 { .compatible = "qcom,krait-cc-v1", (void *)1UL },
285 { .compatible = "qcom,krait-cc-v2" },
288 MODULE_DEVICE_TABLE(of, krait_cc_match_table);
290 static int krait_cc_probe(struct platform_device *pdev)
292 struct device *dev = &pdev->dev;
293 const struct of_device_id *id;
294 unsigned long cur_rate, aux_rate;
298 struct clk *l2_pri_mux_clk;
300 id = of_match_device(krait_cc_match_table, dev);
304 /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
305 clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
310 clk = clk_register_fixed_factor(dev, "acpu_aux",
311 "gpll0_vote", 0, 1, 2);
316 /* Krait configurations have at most 4 CPUs and one L2 */
317 clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
321 for_each_possible_cpu(cpu) {
322 clk = krait_add_clks(dev, cpu, id->data);
328 l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
329 if (IS_ERR(l2_pri_mux_clk))
330 return PTR_ERR(l2_pri_mux_clk);
331 clks[4] = l2_pri_mux_clk;
334 * We don't want the CPU or L2 clocks to be turned off at late init
335 * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
336 * refcount of these clocks. Any cpufreq/hotplug manager can assume
337 * that the clocks have already been prepared and enabled by the time
340 for_each_online_cpu(cpu) {
341 clk_prepare_enable(l2_pri_mux_clk);
342 WARN(clk_prepare_enable(clks[cpu]),
343 "Unable to turn on CPU%d clock", cpu);
347 * Force reinit of HFPLLs and muxes to overwrite any potential
348 * incorrect configuration of HFPLLs and muxes by the bootloader.
349 * While at it, also make sure the cores are running at known rates
350 * and print the current rate.
352 * The clocks are set to aux clock rate first to make sure the
353 * secondary mux is not sourcing off of QSB. The rate is then set to
354 * two different rates to force a HFPLL reinit under all
357 cur_rate = clk_get_rate(l2_pri_mux_clk);
358 aux_rate = 384000000;
360 pr_info("L2 @ QSB rate. Forcing new rate.\n");
363 clk_set_rate(l2_pri_mux_clk, aux_rate);
364 clk_set_rate(l2_pri_mux_clk, 2);
365 clk_set_rate(l2_pri_mux_clk, cur_rate);
366 pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
367 for_each_possible_cpu(cpu) {
369 cur_rate = clk_get_rate(clk);
371 pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
375 clk_set_rate(clk, aux_rate);
376 clk_set_rate(clk, 2);
377 clk_set_rate(clk, cur_rate);
378 pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
381 of_clk_add_provider(dev->of_node, krait_of_get, clks);
386 static struct platform_driver krait_cc_driver = {
387 .probe = krait_cc_probe,
390 .of_match_table = krait_cc_match_table,
393 module_platform_driver(krait_cc_driver);
395 MODULE_DESCRIPTION("Krait CPU Clock Driver");
396 MODULE_LICENSE("GPL v2");
397 MODULE_ALIAS("platform:krait-cc");