1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * Copyright (c) BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/clk-provider.h>
16 #include <linux/regmap.h>
18 #include <dt-bindings/clock/qcom,lcc-mdm9615.h>
21 #include "clk-regmap.h"
24 #include "clk-branch.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-regmap-mux.h"
28 static struct clk_pll pll4 = {
36 .clkr.hw.init = &(struct clk_init_data){
38 .parent_names = (const char *[]){ "cxo" },
49 static const struct parent_map lcc_cxo_pll4_map[] = {
54 static const char * const lcc_cxo_pll4[] = {
59 static struct freq_tbl clk_tbl_aif_osr_492[] = {
60 { 512000, P_PLL4, 4, 1, 240 },
61 { 768000, P_PLL4, 4, 1, 160 },
62 { 1024000, P_PLL4, 4, 1, 120 },
63 { 1536000, P_PLL4, 4, 1, 80 },
64 { 2048000, P_PLL4, 4, 1, 60 },
65 { 3072000, P_PLL4, 4, 1, 40 },
66 { 4096000, P_PLL4, 4, 1, 30 },
67 { 6144000, P_PLL4, 4, 1, 20 },
68 { 8192000, P_PLL4, 4, 1, 15 },
69 { 12288000, P_PLL4, 4, 1, 10 },
70 { 24576000, P_PLL4, 4, 1, 5 },
71 { 27000000, P_CXO, 1, 0, 0 },
75 static struct freq_tbl clk_tbl_aif_osr_393[] = {
76 { 512000, P_PLL4, 4, 1, 192 },
77 { 768000, P_PLL4, 4, 1, 128 },
78 { 1024000, P_PLL4, 4, 1, 96 },
79 { 1536000, P_PLL4, 4, 1, 64 },
80 { 2048000, P_PLL4, 4, 1, 48 },
81 { 3072000, P_PLL4, 4, 1, 32 },
82 { 4096000, P_PLL4, 4, 1, 24 },
83 { 6144000, P_PLL4, 4, 1, 16 },
84 { 8192000, P_PLL4, 4, 1, 12 },
85 { 12288000, P_PLL4, 4, 1, 8 },
86 { 24576000, P_PLL4, 4, 1, 4 },
87 { 27000000, P_CXO, 1, 0, 0 },
91 static struct clk_rcg mi2s_osr_src = {
97 .mnctr_mode_shift = 5,
108 .parent_map = lcc_cxo_pll4_map,
110 .freq_tbl = clk_tbl_aif_osr_393,
113 .enable_mask = BIT(9),
114 .hw.init = &(struct clk_init_data){
115 .name = "mi2s_osr_src",
116 .parent_names = lcc_cxo_pll4,
119 .flags = CLK_SET_RATE_GATE,
124 static const char * const lcc_mi2s_parents[] = {
128 static struct clk_branch mi2s_osr_clk = {
131 .halt_check = BRANCH_HALT_ENABLE,
134 .enable_mask = BIT(17),
135 .hw.init = &(struct clk_init_data){
136 .name = "mi2s_osr_clk",
137 .parent_names = lcc_mi2s_parents,
139 .ops = &clk_branch_ops,
140 .flags = CLK_SET_RATE_PARENT,
145 static struct clk_regmap_div mi2s_div_clk = {
151 .enable_mask = BIT(15),
152 .hw.init = &(struct clk_init_data){
153 .name = "mi2s_div_clk",
154 .parent_names = lcc_mi2s_parents,
156 .ops = &clk_regmap_div_ops,
161 static struct clk_branch mi2s_bit_div_clk = {
164 .halt_check = BRANCH_HALT_ENABLE,
167 .enable_mask = BIT(15),
168 .hw.init = &(struct clk_init_data){
169 .name = "mi2s_bit_div_clk",
170 .parent_names = (const char *[]){ "mi2s_div_clk" },
172 .ops = &clk_branch_ops,
173 .flags = CLK_SET_RATE_PARENT,
178 static struct clk_regmap_mux mi2s_bit_clk = {
183 .hw.init = &(struct clk_init_data){
184 .name = "mi2s_bit_clk",
185 .parent_names = (const char *[]){
190 .ops = &clk_regmap_mux_closest_ops,
191 .flags = CLK_SET_RATE_PARENT,
196 #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
197 static struct clk_rcg prefix##_osr_src = { \
202 .mnctr_reset_bit = 7, \
203 .mnctr_mode_shift = 5, \
209 .pre_div_shift = 3, \
210 .pre_div_width = 2, \
213 .src_sel_shift = 0, \
214 .parent_map = lcc_cxo_pll4_map, \
216 .freq_tbl = clk_tbl_aif_osr_393, \
219 .enable_mask = BIT(9), \
220 .hw.init = &(struct clk_init_data){ \
221 .name = #prefix "_osr_src", \
222 .parent_names = lcc_cxo_pll4, \
224 .ops = &clk_rcg_ops, \
225 .flags = CLK_SET_RATE_GATE, \
230 static const char * const lcc_##prefix##_parents[] = { \
231 #prefix "_osr_src", \
234 static struct clk_branch prefix##_osr_clk = { \
237 .halt_check = BRANCH_HALT_ENABLE, \
240 .enable_mask = BIT(21), \
241 .hw.init = &(struct clk_init_data){ \
242 .name = #prefix "_osr_clk", \
243 .parent_names = lcc_##prefix##_parents, \
245 .ops = &clk_branch_ops, \
246 .flags = CLK_SET_RATE_PARENT, \
251 static struct clk_regmap_div prefix##_div_clk = { \
256 .hw.init = &(struct clk_init_data){ \
257 .name = #prefix "_div_clk", \
258 .parent_names = lcc_##prefix##_parents, \
260 .ops = &clk_regmap_div_ops, \
265 static struct clk_branch prefix##_bit_div_clk = { \
268 .halt_check = BRANCH_HALT_ENABLE, \
271 .enable_mask = BIT(19), \
272 .hw.init = &(struct clk_init_data){ \
273 .name = #prefix "_bit_div_clk", \
274 .parent_names = (const char *[]){ \
278 .ops = &clk_branch_ops, \
279 .flags = CLK_SET_RATE_PARENT, \
284 static struct clk_regmap_mux prefix##_bit_clk = { \
289 .hw.init = &(struct clk_init_data){ \
290 .name = #prefix "_bit_clk", \
291 .parent_names = (const char *[]){ \
292 #prefix "_bit_div_clk", \
293 #prefix "_codec_clk", \
296 .ops = &clk_regmap_mux_closest_ops, \
297 .flags = CLK_SET_RATE_PARENT, \
302 CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
303 CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
304 CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
305 CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
307 static struct freq_tbl clk_tbl_pcm_492[] = {
308 { 256000, P_PLL4, 4, 1, 480 },
309 { 512000, P_PLL4, 4, 1, 240 },
310 { 768000, P_PLL4, 4, 1, 160 },
311 { 1024000, P_PLL4, 4, 1, 120 },
312 { 1536000, P_PLL4, 4, 1, 80 },
313 { 2048000, P_PLL4, 4, 1, 60 },
314 { 3072000, P_PLL4, 4, 1, 40 },
315 { 4096000, P_PLL4, 4, 1, 30 },
316 { 6144000, P_PLL4, 4, 1, 20 },
317 { 8192000, P_PLL4, 4, 1, 15 },
318 { 12288000, P_PLL4, 4, 1, 10 },
319 { 24576000, P_PLL4, 4, 1, 5 },
320 { 27000000, P_CXO, 1, 0, 0 },
324 static struct freq_tbl clk_tbl_pcm_393[] = {
325 { 256000, P_PLL4, 4, 1, 384 },
326 { 512000, P_PLL4, 4, 1, 192 },
327 { 768000, P_PLL4, 4, 1, 128 },
328 { 1024000, P_PLL4, 4, 1, 96 },
329 { 1536000, P_PLL4, 4, 1, 64 },
330 { 2048000, P_PLL4, 4, 1, 48 },
331 { 3072000, P_PLL4, 4, 1, 32 },
332 { 4096000, P_PLL4, 4, 1, 24 },
333 { 6144000, P_PLL4, 4, 1, 16 },
334 { 8192000, P_PLL4, 4, 1, 12 },
335 { 12288000, P_PLL4, 4, 1, 8 },
336 { 24576000, P_PLL4, 4, 1, 4 },
337 { 27000000, P_CXO, 1, 0, 0 },
341 static struct clk_rcg pcm_src = {
346 .mnctr_reset_bit = 7,
347 .mnctr_mode_shift = 5,
358 .parent_map = lcc_cxo_pll4_map,
360 .freq_tbl = clk_tbl_pcm_393,
363 .enable_mask = BIT(9),
364 .hw.init = &(struct clk_init_data){
366 .parent_names = lcc_cxo_pll4,
369 .flags = CLK_SET_RATE_GATE,
374 static struct clk_branch pcm_clk_out = {
377 .halt_check = BRANCH_HALT_ENABLE,
380 .enable_mask = BIT(11),
381 .hw.init = &(struct clk_init_data){
382 .name = "pcm_clk_out",
383 .parent_names = (const char *[]){ "pcm_src" },
385 .ops = &clk_branch_ops,
386 .flags = CLK_SET_RATE_PARENT,
391 static struct clk_regmap_mux pcm_clk = {
396 .hw.init = &(struct clk_init_data){
398 .parent_names = (const char *[]){
403 .ops = &clk_regmap_mux_closest_ops,
404 .flags = CLK_SET_RATE_PARENT,
409 static struct clk_rcg slimbus_src = {
414 .mnctr_reset_bit = 7,
415 .mnctr_mode_shift = 5,
426 .parent_map = lcc_cxo_pll4_map,
428 .freq_tbl = clk_tbl_aif_osr_393,
431 .enable_mask = BIT(9),
432 .hw.init = &(struct clk_init_data){
433 .name = "slimbus_src",
434 .parent_names = lcc_cxo_pll4,
437 .flags = CLK_SET_RATE_GATE,
442 static const char * const lcc_slimbus_parents[] = {
446 static struct clk_branch audio_slimbus_clk = {
449 .halt_check = BRANCH_HALT_ENABLE,
452 .enable_mask = BIT(10),
453 .hw.init = &(struct clk_init_data){
454 .name = "audio_slimbus_clk",
455 .parent_names = lcc_slimbus_parents,
457 .ops = &clk_branch_ops,
458 .flags = CLK_SET_RATE_PARENT,
463 static struct clk_branch sps_slimbus_clk = {
466 .halt_check = BRANCH_HALT_ENABLE,
469 .enable_mask = BIT(12),
470 .hw.init = &(struct clk_init_data){
471 .name = "sps_slimbus_clk",
472 .parent_names = lcc_slimbus_parents,
474 .ops = &clk_branch_ops,
475 .flags = CLK_SET_RATE_PARENT,
480 static struct clk_regmap *lcc_mdm9615_clks[] = {
482 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
483 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
484 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
485 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
486 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
487 [PCM_SRC] = &pcm_src.clkr,
488 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
489 [PCM_CLK] = &pcm_clk.clkr,
490 [SLIMBUS_SRC] = &slimbus_src.clkr,
491 [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
492 [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
493 [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
494 [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
495 [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
496 [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
497 [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
498 [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
499 [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
500 [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
501 [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
502 [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
503 [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
504 [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
505 [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
506 [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
507 [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
508 [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
509 [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
510 [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
511 [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
512 [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
515 static const struct regmap_config lcc_mdm9615_regmap_config = {
519 .max_register = 0xfc,
523 static const struct qcom_cc_desc lcc_mdm9615_desc = {
524 .config = &lcc_mdm9615_regmap_config,
525 .clks = lcc_mdm9615_clks,
526 .num_clks = ARRAY_SIZE(lcc_mdm9615_clks),
529 static const struct of_device_id lcc_mdm9615_match_table[] = {
530 { .compatible = "qcom,lcc-mdm9615" },
533 MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table);
535 static int lcc_mdm9615_probe(struct platform_device *pdev)
538 struct regmap *regmap;
540 regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc);
542 return PTR_ERR(regmap);
544 /* Use the correct frequency plan depending on speed of PLL4 */
545 regmap_read(regmap, 0x4, &val);
547 slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
548 mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
549 codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
550 spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
551 codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
552 spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
553 pcm_src.freq_tbl = clk_tbl_pcm_492;
555 /* Enable PLL4 source on the LPASS Primary PLL Mux */
556 regmap_write(regmap, 0xc4, 0x1);
558 return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap);
561 static struct platform_driver lcc_mdm9615_driver = {
562 .probe = lcc_mdm9615_probe,
564 .name = "lcc-mdm9615",
565 .of_match_table = lcc_mdm9615_match_table,
568 module_platform_driver(lcc_mdm9615_driver);
570 MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver");
571 MODULE_LICENSE("GPL v2");
572 MODULE_ALIAS("platform:lcc-mdm9615");