1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
16 #include "clk-regmap.h"
23 P_CORE_BI_PLL_TEST_SE,
24 P_VIDEO_PLL0_OUT_EVEN,
25 P_VIDEO_PLL0_OUT_MAIN,
29 static const struct pll_vco fabia_vco[] = {
30 { 249600000, 2000000000, 0 },
33 static struct clk_alpha_pll video_pll0 = {
35 .vco_table = fabia_vco,
36 .num_vco = ARRAY_SIZE(fabia_vco),
37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
39 .hw.init = &(struct clk_init_data){
41 .parent_data = &(const struct clk_parent_data){
45 .ops = &clk_alpha_pll_fabia_ops,
50 static const struct parent_map video_cc_parent_map_1[] = {
52 { P_VIDEO_PLL0_OUT_MAIN, 1 },
53 { P_CORE_BI_PLL_TEST_SE, 7 },
56 static const struct clk_parent_data video_cc_parent_data_1[] = {
57 { .fw_name = "bi_tcxo" },
58 { .hw = &video_pll0.clkr.hw },
59 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
62 static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
63 F(19200000, P_BI_TCXO, 1, 0, 0),
64 F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
65 F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
66 F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
67 F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
68 F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
72 static struct clk_rcg2 video_cc_venus_clk_src = {
76 .parent_map = video_cc_parent_map_1,
77 .freq_tbl = ftbl_video_cc_venus_clk_src,
78 .clkr.hw.init = &(struct clk_init_data){
79 .name = "video_cc_venus_clk_src",
80 .parent_data = video_cc_parent_data_1,
82 .flags = CLK_SET_RATE_PARENT,
83 .ops = &clk_rcg2_shared_ops,
87 static struct clk_branch video_cc_vcodec0_axi_clk = {
89 .halt_check = BRANCH_HALT,
92 .enable_mask = BIT(0),
93 .hw.init = &(struct clk_init_data){
94 .name = "video_cc_vcodec0_axi_clk",
95 .ops = &clk_branch2_ops,
100 static struct clk_branch video_cc_vcodec0_core_clk = {
102 .halt_check = BRANCH_HALT,
105 .enable_mask = BIT(0),
106 .hw.init = &(struct clk_init_data){
107 .name = "video_cc_vcodec0_core_clk",
108 .parent_data = &(const struct clk_parent_data){
109 .hw = &video_cc_venus_clk_src.clkr.hw,
112 .flags = CLK_SET_RATE_PARENT,
113 .ops = &clk_branch2_ops,
118 static struct clk_branch video_cc_venus_ahb_clk = {
120 .halt_check = BRANCH_HALT,
123 .enable_mask = BIT(0),
124 .hw.init = &(struct clk_init_data){
125 .name = "video_cc_venus_ahb_clk",
126 .ops = &clk_branch2_ops,
131 static struct clk_branch video_cc_venus_ctl_axi_clk = {
133 .halt_check = BRANCH_HALT,
136 .enable_mask = BIT(0),
137 .hw.init = &(struct clk_init_data){
138 .name = "video_cc_venus_ctl_axi_clk",
139 .ops = &clk_branch2_ops,
144 static struct clk_branch video_cc_venus_ctl_core_clk = {
146 .halt_check = BRANCH_HALT,
149 .enable_mask = BIT(0),
150 .hw.init = &(struct clk_init_data){
151 .name = "video_cc_venus_ctl_core_clk",
152 .parent_data = &(const struct clk_parent_data){
153 .hw = &video_cc_venus_clk_src.clkr.hw,
156 .flags = CLK_SET_RATE_PARENT,
157 .ops = &clk_branch2_ops,
162 static struct gdsc venus_gdsc = {
165 .name = "venus_gdsc",
167 .pwrsts = PWRSTS_OFF_ON,
170 static struct gdsc vcodec0_gdsc = {
173 .name = "vcodec0_gdsc",
176 .pwrsts = PWRSTS_OFF_ON,
179 static struct clk_regmap *video_cc_sc7180_clocks[] = {
180 [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
181 [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
182 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
183 [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
184 [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
185 [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
186 [VIDEO_PLL0] = &video_pll0.clkr,
189 static struct gdsc *video_cc_sc7180_gdscs[] = {
190 [VENUS_GDSC] = &venus_gdsc,
191 [VCODEC0_GDSC] = &vcodec0_gdsc,
194 static const struct regmap_config video_cc_sc7180_regmap_config = {
198 .max_register = 0xb94,
202 static const struct qcom_cc_desc video_cc_sc7180_desc = {
203 .config = &video_cc_sc7180_regmap_config,
204 .clks = video_cc_sc7180_clocks,
205 .num_clks = ARRAY_SIZE(video_cc_sc7180_clocks),
206 .gdscs = video_cc_sc7180_gdscs,
207 .num_gdscs = ARRAY_SIZE(video_cc_sc7180_gdscs),
210 static const struct of_device_id video_cc_sc7180_match_table[] = {
211 { .compatible = "qcom,sc7180-videocc" },
214 MODULE_DEVICE_TABLE(of, video_cc_sc7180_match_table);
216 static int video_cc_sc7180_probe(struct platform_device *pdev)
218 struct regmap *regmap;
219 struct alpha_pll_config video_pll0_config = {};
221 regmap = qcom_cc_map(pdev, &video_cc_sc7180_desc);
223 return PTR_ERR(regmap);
225 video_pll0_config.l = 0x1f;
226 video_pll0_config.alpha = 0x4000;
227 video_pll0_config.user_ctl_val = 0x00000001;
228 video_pll0_config.user_ctl_hi_val = 0x00004805;
230 clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
232 /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
233 regmap_update_bits(regmap, 0x984, 0x1, 0x1);
235 return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap);
238 static struct platform_driver video_cc_sc7180_driver = {
239 .probe = video_cc_sc7180_probe,
241 .name = "sc7180-videocc",
242 .of_match_table = video_cc_sc7180_match_table,
246 static int __init video_cc_sc7180_init(void)
248 return platform_driver_register(&video_cc_sc7180_driver);
250 subsys_initcall(video_cc_sc7180_init);
252 static void __exit video_cc_sc7180_exit(void)
254 platform_driver_unregister(&video_cc_sc7180_driver);
256 module_exit(video_cc_sc7180_exit);
258 MODULE_LICENSE("GPL v2");
259 MODULE_DESCRIPTION("QTI VIDEOCC SC7180 Driver");