1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap.h"
23 P_CORE_BI_PLL_TEST_SE,
24 P_VIDEO_PLL0_OUT_EVEN,
25 P_VIDEO_PLL0_OUT_MAIN,
29 static const struct parent_map video_cc_parent_map_0[] = {
31 { P_VIDEO_PLL0_OUT_MAIN, 1 },
32 { P_VIDEO_PLL0_OUT_EVEN, 2 },
33 { P_VIDEO_PLL0_OUT_ODD, 3 },
34 { P_CORE_BI_PLL_TEST_SE, 4 },
37 static const char * const video_cc_parent_names_0[] = {
40 "video_pll0_out_even",
42 "core_bi_pll_test_se",
45 static const struct alpha_pll_config video_pll0_config = {
50 static struct clk_alpha_pll video_pll0 = {
52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
54 .hw.init = &(struct clk_init_data){
56 .parent_names = (const char *[]){ "bi_tcxo" },
58 .ops = &clk_alpha_pll_fabia_ops,
63 static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
64 F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
65 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
66 F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
67 F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
68 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
69 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
73 static struct clk_rcg2 video_cc_venus_clk_src = {
77 .parent_map = video_cc_parent_map_0,
78 .freq_tbl = ftbl_video_cc_venus_clk_src,
79 .clkr.hw.init = &(struct clk_init_data){
80 .name = "video_cc_venus_clk_src",
81 .parent_names = video_cc_parent_names_0,
83 .flags = CLK_SET_RATE_PARENT,
84 .ops = &clk_rcg2_shared_ops,
88 static struct clk_branch video_cc_apb_clk = {
90 .halt_check = BRANCH_HALT,
93 .enable_mask = BIT(0),
94 .hw.init = &(struct clk_init_data){
95 .name = "video_cc_apb_clk",
96 .ops = &clk_branch2_ops,
101 static struct clk_branch video_cc_at_clk = {
103 .halt_check = BRANCH_HALT,
106 .enable_mask = BIT(0),
107 .hw.init = &(struct clk_init_data){
108 .name = "video_cc_at_clk",
109 .ops = &clk_branch2_ops,
114 static struct clk_branch video_cc_qdss_trig_clk = {
116 .halt_check = BRANCH_HALT,
119 .enable_mask = BIT(0),
120 .hw.init = &(struct clk_init_data){
121 .name = "video_cc_qdss_trig_clk",
122 .ops = &clk_branch2_ops,
127 static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
129 .halt_check = BRANCH_HALT,
132 .enable_mask = BIT(0),
133 .hw.init = &(struct clk_init_data){
134 .name = "video_cc_qdss_tsctr_div8_clk",
135 .ops = &clk_branch2_ops,
140 static struct clk_branch video_cc_vcodec0_axi_clk = {
142 .halt_check = BRANCH_HALT,
145 .enable_mask = BIT(0),
146 .hw.init = &(struct clk_init_data){
147 .name = "video_cc_vcodec0_axi_clk",
148 .ops = &clk_branch2_ops,
153 static struct clk_branch video_cc_vcodec0_core_clk = {
155 .halt_check = BRANCH_VOTED,
158 .enable_mask = BIT(0),
159 .hw.init = &(struct clk_init_data){
160 .name = "video_cc_vcodec0_core_clk",
161 .parent_names = (const char *[]){
162 "video_cc_venus_clk_src",
165 .flags = CLK_SET_RATE_PARENT,
166 .ops = &clk_branch2_ops,
171 static struct clk_branch video_cc_vcodec1_axi_clk = {
173 .halt_check = BRANCH_HALT,
176 .enable_mask = BIT(0),
177 .hw.init = &(struct clk_init_data){
178 .name = "video_cc_vcodec1_axi_clk",
179 .ops = &clk_branch2_ops,
184 static struct clk_branch video_cc_vcodec1_core_clk = {
186 .halt_check = BRANCH_VOTED,
189 .enable_mask = BIT(0),
190 .hw.init = &(struct clk_init_data){
191 .name = "video_cc_vcodec1_core_clk",
192 .parent_names = (const char *[]){
193 "video_cc_venus_clk_src",
196 .flags = CLK_SET_RATE_PARENT,
197 .ops = &clk_branch2_ops,
202 static struct clk_branch video_cc_venus_ahb_clk = {
204 .halt_check = BRANCH_HALT,
207 .enable_mask = BIT(0),
208 .hw.init = &(struct clk_init_data){
209 .name = "video_cc_venus_ahb_clk",
210 .ops = &clk_branch2_ops,
215 static struct clk_branch video_cc_venus_ctl_axi_clk = {
217 .halt_check = BRANCH_HALT,
220 .enable_mask = BIT(0),
221 .hw.init = &(struct clk_init_data){
222 .name = "video_cc_venus_ctl_axi_clk",
223 .ops = &clk_branch2_ops,
228 static struct clk_branch video_cc_venus_ctl_core_clk = {
230 .halt_check = BRANCH_HALT,
233 .enable_mask = BIT(0),
234 .hw.init = &(struct clk_init_data){
235 .name = "video_cc_venus_ctl_core_clk",
236 .parent_names = (const char *[]){
237 "video_cc_venus_clk_src",
240 .flags = CLK_SET_RATE_PARENT,
241 .ops = &clk_branch2_ops,
246 static struct gdsc venus_gdsc = {
249 .name = "venus_gdsc",
251 .cxcs = (unsigned int []){ 0x850, 0x910 },
253 .pwrsts = PWRSTS_OFF_ON,
254 .flags = POLL_CFG_GDSCR,
257 static struct gdsc vcodec0_gdsc = {
260 .name = "vcodec0_gdsc",
262 .cxcs = (unsigned int []){ 0x890, 0x930 },
264 .flags = HW_CTRL | POLL_CFG_GDSCR,
265 .pwrsts = PWRSTS_OFF_ON,
268 static struct gdsc vcodec1_gdsc = {
271 .name = "vcodec1_gdsc",
273 .cxcs = (unsigned int []){ 0x8d0, 0x950 },
275 .flags = HW_CTRL | POLL_CFG_GDSCR,
276 .pwrsts = PWRSTS_OFF_ON,
279 static struct clk_regmap *video_cc_sdm845_clocks[] = {
280 [VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
281 [VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
282 [VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
283 [VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
284 [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
285 [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
286 [VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
287 [VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
288 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
289 [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
290 [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
291 [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
292 [VIDEO_PLL0] = &video_pll0.clkr,
295 static struct gdsc *video_cc_sdm845_gdscs[] = {
296 [VENUS_GDSC] = &venus_gdsc,
297 [VCODEC0_GDSC] = &vcodec0_gdsc,
298 [VCODEC1_GDSC] = &vcodec1_gdsc,
301 static const struct regmap_config video_cc_sdm845_regmap_config = {
305 .max_register = 0xb90,
309 static const struct qcom_cc_desc video_cc_sdm845_desc = {
310 .config = &video_cc_sdm845_regmap_config,
311 .clks = video_cc_sdm845_clocks,
312 .num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
313 .gdscs = video_cc_sdm845_gdscs,
314 .num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
317 static const struct of_device_id video_cc_sdm845_match_table[] = {
318 { .compatible = "qcom,sdm845-videocc" },
321 MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
323 static int video_cc_sdm845_probe(struct platform_device *pdev)
325 struct regmap *regmap;
327 regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
329 return PTR_ERR(regmap);
331 clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
333 return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
336 static struct platform_driver video_cc_sdm845_driver = {
337 .probe = video_cc_sdm845_probe,
339 .name = "sdm845-videocc",
340 .of_match_table = video_cc_sdm845_match_table,
344 static int __init video_cc_sdm845_init(void)
346 return platform_driver_register(&video_cc_sdm845_driver);
348 subsys_initcall(video_cc_sdm845_init);
350 static void __exit video_cc_sdm845_exit(void)
352 platform_driver_unregister(&video_cc_sdm845_driver);
354 module_exit(video_cc_sdm845_exit);
356 MODULE_LICENSE("GPL v2");