drivers/clk/renesas/rcar-gen3-cpg.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * R-Car Gen3 Clock Pulse Generator
   4  *
   5  * Copyright (C) 2015-2016 Glider bvba
   6  */
   7
   8 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
   9 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
  10
  11 enum rcar_gen3_clk_types {
  12         CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
  13         CLK_TYPE_GEN3_PLL0,
  14         CLK_TYPE_GEN3_PLL1,
  15         CLK_TYPE_GEN3_PLL2,
  16         CLK_TYPE_GEN3_PLL3,
  17         CLK_TYPE_GEN3_PLL4,
  18         CLK_TYPE_GEN3_SD,
  19         CLK_TYPE_GEN3_R,
  20         CLK_TYPE_GEN3_PE,
  21         CLK_TYPE_GEN3_Z,
  22         CLK_TYPE_GEN3_Z2,
  23 };
  24
  25 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
  26         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
  27
  28 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
  29                     _div_clean) \
  30         DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,                  \
  31                  (_parent_sscg) << 16 | (_parent_clean),        \
  32                  .div = (_div_sscg) << 16 | (_div_clean))
  33
  34 struct rcar_gen3_cpg_pll_config {
  35         u8 extal_div;
  36         u8 pll1_mult;
  37         u8 pll1_div;
  38         u8 pll3_mult;
  39         u8 pll3_div;
  40 };
  41
  42 #define CPG_RCKCR       0x240
  43
  44 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
  45         const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  46         struct clk **clks, void __iomem *base,
  47         struct raw_notifier_head *notifiers);
  48 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
  49                        unsigned int clk_extalr, u32 mode);
  50
  51 #endif