drivers/clk/tegra/clk-dfll.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * clk-dfll.c - Tegra DFLL clock source common code
   4  *
   5  * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
   6  *
   7  * Aleksandr Frid <afrid@nvidia.com>
   8  * Paul Walmsley <pwalmsley@nvidia.com>
   9  *
  10  * This library is for the DVCO and DFLL IP blocks on the Tegra124
  11  * SoC. These IP blocks together are also known at NVIDIA as
  12  * "CL-DVFS". To try to avoid confusion, this code refers to them
  13  * collectively as the "DFLL."
  14  *
  15  * The DFLL is a root clocksource which tolerates some amount of
  16  * supply voltage noise. Tegra124 uses it to clock the fast CPU
  17  * complex when the target CPU speed is above a particular rate. The
  18  * DFLL can be operated in either open-loop mode or closed-loop mode.
  19  * In open-loop mode, the DFLL generates an output clock appropriate
  20  * to the supply voltage. In closed-loop mode, when configured with a
  21  * target frequency, the DFLL minimizes supply voltage while
  22  * delivering an average frequency equal to the target.
  23  *
  24  * Devices clocked by the DFLL must be able to tolerate frequency
  25  * variation. In the case of the CPU, it's important to note that the
  26  * CPU cycle time will vary. This has implications for
  27  * performance-measurement code and any code that relies on the CPU
  28  * cycle time to delay for a certain length of time.
  29  */
  30
  31 #include <linux/clk.h>
  32 #include <linux/clk-provider.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/device.h>
  35 #include <linux/err.h>
  36 #include <linux/i2c.h>
  37 #include <linux/io.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/of.h>
  41 #include <linux/pinctrl/consumer.h>
  42 #include <linux/pm_opp.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/regmap.h>
  45 #include <linux/regulator/consumer.h>
  46 #include <linux/reset.h>
  47 #include <linux/seq_file.h>
  48
  49 #include "clk-dfll.h"
  50 #include "cvb.h"
  51
  52 /*
  53  * DFLL control registers - access via dfll_{readl,writel}
  54  */
  55
  56 /* DFLL_CTRL: DFLL control register */
  57 #define DFLL_CTRL                       0x00
  58 #define DFLL_CTRL_MODE_MASK             0x03
  59
  60 /* DFLL_CONFIG: DFLL sample rate control */
  61 #define DFLL_CONFIG                     0x04
  62 #define DFLL_CONFIG_DIV_MASK            0xff
  63 #define DFLL_CONFIG_DIV_PRESCALE        32
  64
  65 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */
  66 #define DFLL_PARAMS                     0x08
  67 #define DFLL_PARAMS_CG_SCALE            (0x1 << 24)
  68 #define DFLL_PARAMS_FORCE_MODE_SHIFT    22
  69 #define DFLL_PARAMS_FORCE_MODE_MASK     (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT)
  70 #define DFLL_PARAMS_CF_PARAM_SHIFT      16
  71 #define DFLL_PARAMS_CF_PARAM_MASK       (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT)
  72 #define DFLL_PARAMS_CI_PARAM_SHIFT      8
  73 #define DFLL_PARAMS_CI_PARAM_MASK       (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT)
  74 #define DFLL_PARAMS_CG_PARAM_SHIFT      0
  75 #define DFLL_PARAMS_CG_PARAM_MASK       (0xff << DFLL_PARAMS_CG_PARAM_SHIFT)
  76
  77 /* DFLL_TUNE0: delay line configuration register 0 */
  78 #define DFLL_TUNE0                      0x0c
  79
  80 /* DFLL_TUNE1: delay line configuration register 1 */
  81 #define DFLL_TUNE1                      0x10
  82
  83 /* DFLL_FREQ_REQ: target DFLL frequency control */
  84 #define DFLL_FREQ_REQ                   0x14
  85 #define DFLL_FREQ_REQ_FORCE_ENABLE      (0x1 << 28)
  86 #define DFLL_FREQ_REQ_FORCE_SHIFT       16
  87 #define DFLL_FREQ_REQ_FORCE_MASK        (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT)
  88 #define FORCE_MAX                       2047
  89 #define FORCE_MIN                       -2048
  90 #define DFLL_FREQ_REQ_SCALE_SHIFT       8
  91 #define DFLL_FREQ_REQ_SCALE_MASK        (0xff << DFLL_FREQ_REQ_SCALE_SHIFT)
  92 #define DFLL_FREQ_REQ_SCALE_MAX         256
  93 #define DFLL_FREQ_REQ_FREQ_VALID        (0x1 << 7)
  94 #define DFLL_FREQ_REQ_MULT_SHIFT        0
  95 #define DFLL_FREQ_REG_MULT_MASK         (0x7f << DFLL_FREQ_REQ_MULT_SHIFT)
  96 #define FREQ_MAX                        127
  97
  98 /* DFLL_DROOP_CTRL: droop prevention control */
  99 #define DFLL_DROOP_CTRL                 0x1c
 100
 101 /* DFLL_OUTPUT_CFG: closed loop mode control registers */
 102 /* NOTE: access via dfll_i2c_{readl,writel} */
 103 #define DFLL_OUTPUT_CFG                 0x20
 104 #define DFLL_OUTPUT_CFG_I2C_ENABLE      (0x1 << 30)
 105 #define OUT_MASK                        0x3f
 106 #define DFLL_OUTPUT_CFG_SAFE_SHIFT      24
 107 #define DFLL_OUTPUT_CFG_SAFE_MASK       \
 108                 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT)
 109 #define DFLL_OUTPUT_CFG_MAX_SHIFT       16
 110 #define DFLL_OUTPUT_CFG_MAX_MASK        \
 111                 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT)
 112 #define DFLL_OUTPUT_CFG_MIN_SHIFT       8
 113 #define DFLL_OUTPUT_CFG_MIN_MASK        \
 114                 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT)
 115 #define DFLL_OUTPUT_CFG_PWM_DELTA       (0x1 << 7)
 116 #define DFLL_OUTPUT_CFG_PWM_ENABLE      (0x1 << 6)
 117 #define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT   0
 118 #define DFLL_OUTPUT_CFG_PWM_DIV_MASK    \
 119                 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
 120
 121 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */
 122 #define DFLL_OUTPUT_FORCE               0x24
 123 #define DFLL_OUTPUT_FORCE_ENABLE        (0x1 << 6)
 124 #define DFLL_OUTPUT_FORCE_VALUE_SHIFT   0
 125 #define DFLL_OUTPUT_FORCE_VALUE_MASK    \
 126                 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT)
 127
 128 /* DFLL_MONITOR_CTRL: internal monitor data source control */
 129 #define DFLL_MONITOR_CTRL               0x28
 130 #define DFLL_MONITOR_CTRL_FREQ          6
 131
 132 /* DFLL_MONITOR_DATA: internal monitor data output */
 133 #define DFLL_MONITOR_DATA               0x2c
 134 #define DFLL_MONITOR_DATA_NEW_MASK      (0x1 << 16)
 135 #define DFLL_MONITOR_DATA_VAL_SHIFT     0
 136 #define DFLL_MONITOR_DATA_VAL_MASK      (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT)
 137
 138 /*
 139  * I2C output control registers - access via dfll_i2c_{readl,writel}
 140  */
 141
 142 /* DFLL_I2C_CFG: I2C controller configuration register */
 143 #define DFLL_I2C_CFG                    0x40
 144 #define DFLL_I2C_CFG_ARB_ENABLE         (0x1 << 20)
 145 #define DFLL_I2C_CFG_HS_CODE_SHIFT      16
 146 #define DFLL_I2C_CFG_HS_CODE_MASK       (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT)
 147 #define DFLL_I2C_CFG_PACKET_ENABLE      (0x1 << 15)
 148 #define DFLL_I2C_CFG_SIZE_SHIFT         12
 149 #define DFLL_I2C_CFG_SIZE_MASK          (0x7 << DFLL_I2C_CFG_SIZE_SHIFT)
 150 #define DFLL_I2C_CFG_SLAVE_ADDR_10      (0x1 << 10)
 151 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT      1
 152 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT     0
 153
 154 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */
 155 #define DFLL_I2C_VDD_REG_ADDR           0x44
 156
 157 /* DFLL_I2C_STS: I2C controller status */
 158 #define DFLL_I2C_STS                    0x48
 159 #define DFLL_I2C_STS_I2C_LAST_SHIFT     1
 160 #define DFLL_I2C_STS_I2C_REQ_PENDING    0x1
 161
 162 /* DFLL_INTR_STS: DFLL interrupt status register */
 163 #define DFLL_INTR_STS                   0x5c
 164
 165 /* DFLL_INTR_EN: DFLL interrupt enable register */
 166 #define DFLL_INTR_EN                    0x60
 167 #define DFLL_INTR_MIN_MASK              0x1
 168 #define DFLL_INTR_MAX_MASK              0x2
 169
 170 /*
 171  * Integrated I2C controller registers - relative to td->i2c_controller_base
 172  */
 173
 174 /* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */
 175 #define DFLL_I2C_CLK_DIVISOR            0x6c
 176 #define DFLL_I2C_CLK_DIVISOR_MASK       0xffff
 177 #define DFLL_I2C_CLK_DIVISOR_FS_SHIFT   16
 178 #define DFLL_I2C_CLK_DIVISOR_HS_SHIFT   0
 179 #define DFLL_I2C_CLK_DIVISOR_PREDIV     8
 180 #define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV      12
 181
 182 /*
 183  * Other constants
 184  */
 185
 186 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
 187 #define MAX_DFLL_VOLTAGES               33
 188
 189 /*
 190  * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware
 191  *    integrates the DVCO counter over - used for debug rate monitoring and
 192  *    droop control
 193  */
 194 #define REF_CLK_CYC_PER_DVCO_SAMPLE     4
 195
 196 /*
 197  * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this
 198  * driver, in Hz
 199  */
 200 #define REF_CLOCK_RATE                  51000000UL
 201
 202 #define DVCO_RATE_TO_MULT(rate, ref_rate)       ((rate) / ((ref_rate) / 2))
 203 #define MULT_TO_DVCO_RATE(mult, ref_rate)       ((mult) * ((ref_rate) / 2))
 204
 205 /**
 206  * enum dfll_ctrl_mode - DFLL hardware operating mode
 207  * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)
 208  * @DFLL_DISABLED: DFLL not generating an output clock
 209  * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage
 210  * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match
 211  *                    the requested rate
 212  *
 213  * The integer corresponding to the last two states, minus one, is
 214  * written to the DFLL hardware to change operating modes.
 215  */
 216 enum dfll_ctrl_mode {
 217         DFLL_UNINITIALIZED = 0,
 218         DFLL_DISABLED = 1,
 219         DFLL_OPEN_LOOP = 2,
 220         DFLL_CLOSED_LOOP = 3,
 221 };
 222
 223 /**
 224  * enum dfll_tune_range - voltage range that the driver believes it's in
 225  * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed
 226  * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)
 227  *
 228  * Some DFLL tuning parameters may need to change depending on the
 229  * DVCO's voltage; these states represent the ranges that the driver
 230  * supports. These are software states; these values are never
 231  * written into registers.
 232  */
 233 enum dfll_tune_range {
 234         DFLL_TUNE_UNINITIALIZED = 0,
 235         DFLL_TUNE_LOW = 1,
 236 };
 237
 238
 239 enum tegra_dfll_pmu_if {
 240         TEGRA_DFLL_PMU_I2C = 0,
 241         TEGRA_DFLL_PMU_PWM = 1,
 242 };
 243
 244 /**
 245  * struct dfll_rate_req - target DFLL rate request data
 246  * @rate: target frequency, after the postscaling
 247  * @dvco_target_rate: target frequency, after the postscaling
 248  * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
 249  * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register
 250  * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register
 251  */
 252 struct dfll_rate_req {
 253         unsigned long rate;
 254         unsigned long dvco_target_rate;
 255         int lut_index;
 256         u8 mult_bits;
 257         u8 scale_bits;
 258 };
 259
 260 struct tegra_dfll {
 261         struct device                   *dev;
 262         struct tegra_dfll_soc_data      *soc;
 263
 264         void __iomem                    *base;
 265         void __iomem                    *i2c_base;
 266         void __iomem                    *i2c_controller_base;
 267         void __iomem                    *lut_base;
 268
 269         struct regulator                *vdd_reg;
 270         struct clk                      *soc_clk;
 271         struct clk                      *ref_clk;
 272         struct clk                      *i2c_clk;
 273         struct clk                      *dfll_clk;
 274         struct reset_control            *dvco_rst;
 275         unsigned long                   ref_rate;
 276         unsigned long                   i2c_clk_rate;
 277         unsigned long                   dvco_rate_min;
 278
 279         enum dfll_ctrl_mode             mode;
 280         enum dfll_tune_range            tune_range;
 281         struct dentry                   *debugfs_dir;
 282         struct clk_hw                   dfll_clk_hw;
 283         const char                      *output_clock_name;
 284         struct dfll_rate_req            last_req;
 285         unsigned long                   last_unrounded_rate;
 286
 287         /* Parameters from DT */
 288         u32                             droop_ctrl;
 289         u32                             sample_rate;
 290         u32                             force_mode;
 291         u32                             cf;
 292         u32                             ci;
 293         u32                             cg;
 294         bool                            cg_scale;
 295
 296         /* I2C interface parameters */
 297         u32                             i2c_fs_rate;
 298         u32                             i2c_reg;
 299         u32                             i2c_slave_addr;
 300
 301         /* lut array entries are regulator framework selectors or PWM values*/
 302         unsigned                        lut[MAX_DFLL_VOLTAGES];
 303         unsigned long                   lut_uv[MAX_DFLL_VOLTAGES];
 304         int                             lut_size;
 305         u8                              lut_bottom, lut_min, lut_max, lut_safe;
 306
 307         /* PWM interface */
 308         enum tegra_dfll_pmu_if          pmu_if;
 309         unsigned long                   pwm_rate;
 310         struct pinctrl                  *pwm_pin;
 311         struct pinctrl_state            *pwm_enable_state;
 312         struct pinctrl_state            *pwm_disable_state;
 313         u32                             reg_init_uV;
 314 };
 315
 316 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
 317
 318 /* mode_name: map numeric DFLL modes to names for friendly console messages */
 319 static const char * const mode_name[] = {
 320         [DFLL_UNINITIALIZED] = "uninitialized",
 321         [DFLL_DISABLED] = "disabled",
 322         [DFLL_OPEN_LOOP] = "open_loop",
 323         [DFLL_CLOSED_LOOP] = "closed_loop",
 324 };
 325
 326 /*
 327  * Register accessors
 328  */
 329
 330 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)
 331 {
 332         return __raw_readl(td->base + offs);
 333 }
 334
 335 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)
 336 {
 337         WARN_ON(offs >= DFLL_I2C_CFG);
 338         __raw_writel(val, td->base + offs);
 339 }
 340
 341 static inline void dfll_wmb(struct tegra_dfll *td)
 342 {
 343         dfll_readl(td, DFLL_CTRL);
 344 }
 345
 346 /* I2C output control registers - for addresses above DFLL_I2C_CFG */
 347
 348 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)
 349 {
 350         return __raw_readl(td->i2c_base + offs);
 351 }
 352
 353 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)
 354 {
 355         __raw_writel(val, td->i2c_base + offs);
 356 }
 357
 358 static inline void dfll_i2c_wmb(struct tegra_dfll *td)
 359 {
 360         dfll_i2c_readl(td, DFLL_I2C_CFG);
 361 }
 362
 363 /**
 364  * dfll_is_running - is the DFLL currently generating a clock?
 365  * @td: DFLL instance
 366  *
 367  * If the DFLL is currently generating an output clock signal, return
 368  * true; otherwise return false.
 369  */
 370 static bool dfll_is_running(struct tegra_dfll *td)
 371 {
 372         return td->mode >= DFLL_OPEN_LOOP;
 373 }
 374
 375 /*
 376  * Runtime PM suspend/resume callbacks
 377  */
 378
 379 /**
 380  * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL
 381  * @dev: DFLL device *
 382  *
 383  * Enable all clocks needed by the DFLL. Assumes that clk_prepare()
 384  * has already been called on all the clocks.
 385  *
 386  * XXX Should also handle context restore when returning from off.
 387  */
 388 int tegra_dfll_runtime_resume(struct device *dev)
 389 {
 390         struct tegra_dfll *td = dev_get_drvdata(dev);
 391         int ret;
 392
 393         ret = clk_enable(td->ref_clk);
 394         if (ret) {
 395                 dev_err(dev, "could not enable ref clock: %d\n", ret);
 396                 return ret;
 397         }
 398
 399         ret = clk_enable(td->soc_clk);
 400         if (ret) {
 401                 dev_err(dev, "could not enable register clock: %d\n", ret);
 402                 clk_disable(td->ref_clk);
 403                 return ret;
 404         }
 405
 406         ret = clk_enable(td->i2c_clk);
 407         if (ret) {
 408                 dev_err(dev, "could not enable i2c clock: %d\n", ret);
 409                 clk_disable(td->soc_clk);
 410                 clk_disable(td->ref_clk);
 411                 return ret;
 412         }
 413
 414         return 0;
 415 }
 416 EXPORT_SYMBOL(tegra_dfll_runtime_resume);
 417
 418 /**
 419  * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL
 420  * @dev: DFLL device *
 421  *
 422  * Disable all clocks needed by the DFLL. Assumes that other code
 423  * will later call clk_unprepare().
 424  */
 425 int tegra_dfll_runtime_suspend(struct device *dev)
 426 {
 427         struct tegra_dfll *td = dev_get_drvdata(dev);
 428
 429         clk_disable(td->ref_clk);
 430         clk_disable(td->soc_clk);
 431         clk_disable(td->i2c_clk);
 432
 433         return 0;
 434 }
 435 EXPORT_SYMBOL(tegra_dfll_runtime_suspend);
 436
 437 /*
 438  * DFLL tuning operations (per-voltage-range tuning settings)
 439  */
 440
 441 /**
 442  * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage
 443  * @td: DFLL instance
 444  *
 445  * Tune the DFLL oscillator parameters and the CPU clock shaper for
 446  * the low-voltage range. These settings are valid for any voltage,
 447  * but may not be optimal.
 448  */
 449 static void dfll_tune_low(struct tegra_dfll *td)
 450 {
 451         td->tune_range = DFLL_TUNE_LOW;
 452
 453         dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
 454         dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
 455         dfll_wmb(td);
 456
 457         if (td->soc->set_clock_trimmers_low)
 458                 td->soc->set_clock_trimmers_low();
 459 }
 460
 461 /*
 462  * Output clock scaler helpers
 463  */
 464
 465 /**
 466  * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
 467  * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field)
 468  * @dvco_rate: the DVCO rate
 469  *
 470  * Apply the same scaling formula that the DFLL hardware uses to scale
 471  * the DVCO rate.
 472  */
 473 static unsigned long dfll_scale_dvco_rate(int scale_bits,
 474                                           unsigned long dvco_rate)
 475 {
 476         return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
 477 }
 478
 479 /*
 480  * DFLL mode switching
 481  */
 482
 483 /**
 484  * dfll_set_mode - change the DFLL control mode
 485  * @td: DFLL instance
 486  * @mode: DFLL control mode (see enum dfll_ctrl_mode)
 487  *
 488  * Change the DFLL's operating mode between disabled, open-loop mode,
 489  * and closed-loop mode, or vice versa.
 490  */
 491 static void dfll_set_mode(struct tegra_dfll *td,
 492                           enum dfll_ctrl_mode mode)
 493 {
 494         td->mode = mode;
 495         dfll_writel(td, mode - 1, DFLL_CTRL);
 496         dfll_wmb(td);
 497 }
 498
 499 /*
 500  * DVCO rate control
 501  */
 502
 503 static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
 504 {
 505         struct dev_pm_opp *opp;
 506         unsigned long rate, prev_rate;
 507         unsigned long uv, min_uv;
 508
 509         min_uv = td->lut_uv[out_min];
 510         for (rate = 0, prev_rate = 0; ; rate++) {
 511                 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
 512                 if (IS_ERR(opp))
 513                         break;
 514
 515                 uv = dev_pm_opp_get_voltage(opp);
 516                 dev_pm_opp_put(opp);
 517
 518                 if (uv && uv > min_uv)
 519                         return prev_rate;
 520
 521                 prev_rate = rate;
 522         }
 523
 524         return prev_rate;
 525 }
 526
 527 /*
 528  * DFLL-to-I2C controller interface
 529  */
 530
 531 /**
 532  * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests
 533  * @td: DFLL instance
 534  * @enable: whether to enable or disable the I2C voltage requests
 535  *
 536  * Set the master enable control for I2C control value updates. If disabled,
 537  * then I2C control messages are inhibited, regardless of the DFLL mode.
 538  */
 539 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
 540 {
 541         u32 val;
 542
 543         val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);
 544
 545         if (enable)
 546                 val |= DFLL_OUTPUT_CFG_I2C_ENABLE;
 547         else
 548                 val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE;
 549
 550         dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
 551         dfll_i2c_wmb(td);
 552
 553         return 0;
 554 }
 555
 556
 557 /*
 558  * DFLL-to-PWM controller interface
 559  */
 560
 561 /**
 562  * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests
 563  * @td: DFLL instance
 564  * @enable: whether to enable or disable the PWM voltage requests
 565  *
 566  * Set the master enable control for PWM control value updates. If disabled,
 567  * then the PWM signal is not driven. Also configure the PWM output pad
 568  * to the appropriate state.
 569  */
 570 static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)
 571 {
 572         int ret;
 573         u32 val, div;
 574
 575         if (enable) {
 576                 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);
 577                 if (ret < 0) {
 578                         dev_err(td->dev, "setting enable state failed\n");
 579                         return -EINVAL;
 580                 }
 581                 val = dfll_readl(td, DFLL_OUTPUT_CFG);
 582                 val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK;
 583                 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);
 584                 val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
 585                                 & DFLL_OUTPUT_CFG_PWM_DIV_MASK;
 586                 dfll_writel(td, val, DFLL_OUTPUT_CFG);
 587                 dfll_wmb(td);
 588
 589                 val |= DFLL_OUTPUT_CFG_PWM_ENABLE;
 590                 dfll_writel(td, val, DFLL_OUTPUT_CFG);
 591                 dfll_wmb(td);
 592         } else {
 593                 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);
 594                 if (ret < 0)
 595                         dev_warn(td->dev, "setting disable state failed\n");
 596
 597                 val = dfll_readl(td, DFLL_OUTPUT_CFG);
 598                 val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE;
 599                 dfll_writel(td, val, DFLL_OUTPUT_CFG);
 600                 dfll_wmb(td);
 601         }
 602
 603         return 0;
 604 }
 605
 606 /**
 607  * dfll_set_force_output_value - set fixed value for force output
 608  * @td: DFLL instance
 609  * @out_val: value to force output
 610  *
 611  * Set the fixed value for force output, DFLL will output this value when
 612  * force output is enabled.
 613  */
 614 static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)
 615 {
 616         u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
 617
 618         val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK);
 619         dfll_writel(td, val, DFLL_OUTPUT_FORCE);
 620         dfll_wmb(td);
 621
 622         return dfll_readl(td, DFLL_OUTPUT_FORCE);
 623 }
 624
 625 /**
 626  * dfll_set_force_output_enabled - enable/disable force output
 627  * @td: DFLL instance
 628  * @enable: whether to enable or disable the force output
 629  *
 630  * Set the enable control for fouce output with fixed value.
 631  */
 632 static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)
 633 {
 634         u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
 635
 636         if (enable)
 637                 val |= DFLL_OUTPUT_FORCE_ENABLE;
 638         else
 639                 val &= ~DFLL_OUTPUT_FORCE_ENABLE;
 640
 641         dfll_writel(td, val, DFLL_OUTPUT_FORCE);
 642         dfll_wmb(td);
 643 }
 644
 645 /**
 646  * dfll_force_output - force output a fixed value
 647  * @td: DFLL instance
 648  * @out_sel: value to force output
 649  *
 650  * Set the fixed value for force output, DFLL will output this value.
 651  */
 652 static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
 653 {
 654         u32 val;
 655
 656         if (out_sel > OUT_MASK)
 657                 return -EINVAL;
 658
 659         val = dfll_set_force_output_value(td, out_sel);
 660         if ((td->mode < DFLL_CLOSED_LOOP) &&
 661             !(val & DFLL_OUTPUT_FORCE_ENABLE)) {
 662                 dfll_set_force_output_enabled(td, true);
 663         }
 664
 665         return 0;
 666 }
 667
 668 /**
 669  * dfll_load_lut - load the voltage lookup table
 670  * @td: struct tegra_dfll *
 671  *
 672  * Load the voltage-to-PMIC register value lookup table into the DFLL
 673  * IP block memory. Look-up tables can be loaded at any time.
 674  */
 675 static void dfll_load_i2c_lut(struct tegra_dfll *td)
 676 {
 677         int i, lut_index;
 678         u32 val;
 679
 680         for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
 681                 if (i < td->lut_min)
 682                         lut_index = td->lut_min;
 683                 else if (i > td->lut_max)
 684                         lut_index = td->lut_max;
 685                 else
 686                         lut_index = i;
 687
 688                 val = regulator_list_hardware_vsel(td->vdd_reg,
 689                                                      td->lut[lut_index]);
 690                 __raw_writel(val, td->lut_base + i * 4);
 691         }
 692
 693         dfll_i2c_wmb(td);
 694 }
 695
 696 /**
 697  * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface
 698  * @td: DFLL instance
 699  *
 700  * During DFLL driver initialization, program the DFLL-I2C interface
 701  * with the PMU slave address, vdd register offset, and transfer mode.
 702  * This data is used by the DFLL to automatically construct I2C
 703  * voltage-set commands, which are then passed to the DFLL's internal
 704  * I2C controller.
 705  */
 706 static void dfll_init_i2c_if(struct tegra_dfll *td)
 707 {
 708         u32 val;
 709
 710         if (td->i2c_slave_addr > 0x7f) {
 711                 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;
 712                 val |= DFLL_I2C_CFG_SLAVE_ADDR_10;
 713         } else {
 714                 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;
 715         }
 716         val |= DFLL_I2C_CFG_SIZE_MASK;
 717         val |= DFLL_I2C_CFG_ARB_ENABLE;
 718         dfll_i2c_writel(td, val, DFLL_I2C_CFG);
 719
 720         dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);
 721
 722         val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);
 723         BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK));
 724         val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT;
 725
 726         /* default hs divisor just in case */
 727         val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT;
 728         __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
 729         dfll_i2c_wmb(td);
 730 }
 731
 732 /**
 733  * dfll_init_out_if - prepare DFLL-to-PMIC interface
 734  * @td: DFLL instance
 735  *
 736  * During DFLL driver initialization or resume from context loss,
 737  * disable the I2C command output to the PMIC, set safe voltage and
 738  * output limits, and disable and clear limit interrupts.
 739  */
 740 static void dfll_init_out_if(struct tegra_dfll *td)
 741 {
 742         u32 val;
 743
 744         td->lut_min = td->lut_bottom;
 745         td->lut_max = td->lut_size - 1;
 746         td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);
 747
 748         /* clear DFLL_OUTPUT_CFG before setting new value */
 749         dfll_writel(td, 0, DFLL_OUTPUT_CFG);
 750         dfll_wmb(td);
 751
 752         val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
 753               (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
 754               (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
 755         dfll_writel(td, val, DFLL_OUTPUT_CFG);
 756         dfll_wmb(td);
 757
 758         dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
 759         dfll_i2c_writel(td, 0, DFLL_INTR_EN);
 760         dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
 761                         DFLL_INTR_STS);
 762
 763         if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {
 764                 u32 vinit = td->reg_init_uV;
 765                 int vstep = td->soc->alignment.step_uv;
 766                 unsigned long vmin = td->lut_uv[0];
 767
 768                 /* set initial voltage */
 769                 if ((vinit >= vmin) && vstep) {
 770                         unsigned int vsel;
 771
 772                         vsel = DIV_ROUND_UP((vinit - vmin), vstep);
 773                         dfll_force_output(td, vsel);
 774                 }
 775         } else {
 776                 dfll_load_i2c_lut(td);
 777                 dfll_init_i2c_if(td);
 778         }
 779 }
 780
 781 /*
 782  * Set/get the DFLL's targeted output clock rate
 783  */
 784
 785 /**
 786  * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
 787  * @td: DFLL instance
 788  * @rate: clock rate
 789  *
 790  * Determines the index of a I2C LUT entry for a voltage that approximately
 791  * produces the given DFLL clock rate. This is used when forcing a value
 792  * to the integrator during rate changes. Returns -ENOENT if a suitable
 793  * LUT index is not found.
 794  */
 795 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
 796 {
 797         struct dev_pm_opp *opp;
 798         int i, align_step;
 799
 800         opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
 801         if (IS_ERR(opp))
 802                 return PTR_ERR(opp);
 803
 804         align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
 805         dev_pm_opp_put(opp);
 806
 807         for (i = td->lut_bottom; i < td->lut_size; i++) {
 808                 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
 809                         return i;
 810         }
 811
 812         return -ENOENT;
 813 }
 814
 815 /**
 816  * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
 817  * @td: DFLL instance
 818  * @req: DFLL-rate-request structure
 819  * @rate: the desired DFLL rate
 820  *
 821  * Populate the DFLL-rate-request record @req fields with the scale_bits
 822  * and mult_bits fields, based on the target input rate. Returns 0 upon
 823  * success, or -EINVAL if the requested rate in req->rate is too high
 824  * or low for the DFLL to generate.
 825  */
 826 static int dfll_calculate_rate_request(struct tegra_dfll *td,
 827                                        struct dfll_rate_req *req,
 828                                        unsigned long rate)
 829 {
 830         u32 val;
 831
 832         /*
 833          * If requested rate is below the minimum DVCO rate, active the scaler.
 834          * In the future the DVCO minimum voltage should be selected based on
 835          * chip temperature and the actual minimum rate should be calibrated
 836          * at runtime.
 837          */
 838         req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1;
 839         if (rate < td->dvco_rate_min) {
 840                 int scale;
 841
 842                 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX,
 843                                           td->dvco_rate_min / 1000);
 844                 if (!scale) {
 845                         dev_err(td->dev, "%s: Rate %lu is too low\n",
 846                                 __func__, rate);
 847                         return -EINVAL;
 848                 }
 849                 req->scale_bits = scale - 1;
 850                 rate = td->dvco_rate_min;
 851         }
 852
 853         /* Convert requested rate into frequency request and scale settings */
 854         val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
 855         if (val > FREQ_MAX) {
 856                 dev_err(td->dev, "%s: Rate %lu is above dfll range\n",
 857                         __func__, rate);
 858                 return -EINVAL;
 859         }
 860         req->mult_bits = val;
 861         req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);
 862         req->rate = dfll_scale_dvco_rate(req->scale_bits,
 863                                          req->dvco_target_rate);
 864         req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);
 865         if (req->lut_index < 0)
 866                 return req->lut_index;
 867
 868         return 0;
 869 }
 870
 871 /**
 872  * dfll_set_frequency_request - start the frequency change operation
 873  * @td: DFLL instance
 874  * @req: rate request structure
 875  *
 876  * Tell the DFLL to try to change its output frequency to the
 877  * frequency represented by @req. DFLL must be in closed-loop mode.
 878  */
 879 static void dfll_set_frequency_request(struct tegra_dfll *td,
 880                                        struct dfll_rate_req *req)
 881 {
 882         u32 val = 0;
 883         int force_val;
 884         int coef = 128; /* FIXME: td->cg_scale? */;
 885
 886         force_val = (req->lut_index - td->lut_safe) * coef / td->cg;
 887         force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);
 888
 889         val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT;
 890         val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT;
 891         val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) &
 892                 DFLL_FREQ_REQ_FORCE_MASK;
 893         val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE;
 894
 895         dfll_writel(td, val, DFLL_FREQ_REQ);
 896         dfll_wmb(td);
 897 }
 898
 899 /**
 900  * tegra_dfll_request_rate - set the next rate for the DFLL to tune to
 901  * @td: DFLL instance
 902  * @rate: clock rate to target
 903  *
 904  * Convert the requested clock rate @rate into the DFLL control logic
 905  * settings. In closed-loop mode, update new settings immediately to
 906  * adjust DFLL output rate accordingly. Otherwise, just save them
 907  * until the next switch to closed loop. Returns 0 upon success,
 908  * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL
 909  * if @rate is outside the DFLL's tunable range.
 910  */
 911 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
 912 {
 913         int ret;
 914         struct dfll_rate_req req;
 915
 916         if (td->mode == DFLL_UNINITIALIZED) {
 917                 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
 918                         __func__, mode_name[td->mode]);
 919                 return -EPERM;
 920         }
 921
 922         ret = dfll_calculate_rate_request(td, &req, rate);
 923         if (ret)
 924                 return ret;
 925
 926         td->last_unrounded_rate = rate;
 927         td->last_req = req;
 928
 929         if (td->mode == DFLL_CLOSED_LOOP)
 930                 dfll_set_frequency_request(td, &td->last_req);
 931
 932         return 0;
 933 }
 934
 935 /*
 936  * DFLL enable/disable & open-loop <-> closed-loop transitions
 937  */
 938
 939 /**
 940  * dfll_disable - switch from open-loop mode to disabled mode
 941  * @td: DFLL instance
 942  *
 943  * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success
 944  * or -EPERM if the DFLL is not currently in open-loop mode.
 945  */
 946 static int dfll_disable(struct tegra_dfll *td)
 947 {
 948         if (td->mode != DFLL_OPEN_LOOP) {
 949                 dev_err(td->dev, "cannot disable DFLL in %s mode\n",
 950                         mode_name[td->mode]);
 951                 return -EINVAL;
 952         }
 953
 954         dfll_set_mode(td, DFLL_DISABLED);
 955         pm_runtime_put_sync(td->dev);
 956
 957         return 0;
 958 }
 959
 960 /**
 961  * dfll_enable - switch a disabled DFLL to open-loop mode
 962  * @td: DFLL instance
 963  *
 964  * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success
 965  * or -EPERM if the DFLL is not currently disabled.
 966  */
 967 static int dfll_enable(struct tegra_dfll *td)
 968 {
 969         if (td->mode != DFLL_DISABLED) {
 970                 dev_err(td->dev, "cannot enable DFLL in %s mode\n",
 971                         mode_name[td->mode]);
 972                 return -EPERM;
 973         }
 974
 975         pm_runtime_get_sync(td->dev);
 976         dfll_set_mode(td, DFLL_OPEN_LOOP);
 977
 978         return 0;
 979 }
 980
 981 /**
 982  * dfll_set_open_loop_config - prepare to switch to open-loop mode
 983  * @td: DFLL instance
 984  *
 985  * Prepare to switch the DFLL to open-loop mode. This switches the
 986  * DFLL to the low-voltage tuning range, ensures that I2C output
 987  * forcing is disabled, and disables the output clock rate scaler.
 988  * The DFLL's low-voltage tuning range parameters must be
 989  * characterized to keep the downstream device stable at any DVCO
 990  * input voltage. No return value.
 991  */
 992 static void dfll_set_open_loop_config(struct tegra_dfll *td)
 993 {
 994         u32 val;
 995
 996         /* always tune low (safe) in open loop */
 997         if (td->tune_range != DFLL_TUNE_LOW)
 998                 dfll_tune_low(td);
 999
1000         val = dfll_readl(td, DFLL_FREQ_REQ);
1001         val |= DFLL_FREQ_REQ_SCALE_MASK;
1002         val &= ~DFLL_FREQ_REQ_FORCE_ENABLE;
1003         dfll_writel(td, val, DFLL_FREQ_REQ);
1004         dfll_wmb(td);
1005 }
1006
1007 /**
1008  * tegra_dfll_lock - switch from open-loop to closed-loop mode
1009  * @td: DFLL instance
1010  *
1011  * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success,
1012  * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
1013  * DFLL is not currently in open-loop mode.
1014  */
1015 static int dfll_lock(struct tegra_dfll *td)
1016 {
1017         struct dfll_rate_req *req = &td->last_req;
1018
1019         switch (td->mode) {
1020         case DFLL_CLOSED_LOOP:
1021                 return 0;
1022
1023         case DFLL_OPEN_LOOP:
1024                 if (req->rate == 0) {
1025                         dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
1026                                 __func__);
1027                         return -EINVAL;
1028                 }
1029
1030                 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1031                         dfll_pwm_set_output_enabled(td, true);
1032                 else
1033                         dfll_i2c_set_output_enabled(td, true);
1034
1035                 dfll_set_mode(td, DFLL_CLOSED_LOOP);
1036                 dfll_set_frequency_request(td, req);
1037                 dfll_set_force_output_enabled(td, false);
1038                 return 0;
1039
1040         default:
1041                 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1042                 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",
1043                         __func__, mode_name[td->mode]);
1044                 return -EPERM;
1045         }
1046 }
1047
1048 /**
1049  * tegra_dfll_unlock - switch from closed-loop to open-loop mode
1050  * @td: DFLL instance
1051  *
1052  * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success,
1053  * or -EPERM if the DFLL is not currently in open-loop mode.
1054  */
1055 static int dfll_unlock(struct tegra_dfll *td)
1056 {
1057         switch (td->mode) {
1058         case DFLL_CLOSED_LOOP:
1059                 dfll_set_open_loop_config(td);
1060                 dfll_set_mode(td, DFLL_OPEN_LOOP);
1061                 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1062                         dfll_pwm_set_output_enabled(td, false);
1063                 else
1064                         dfll_i2c_set_output_enabled(td, false);
1065                 return 0;
1066
1067         case DFLL_OPEN_LOOP:
1068                 return 0;
1069
1070         default:
1071                 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1072                 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",
1073                         __func__, mode_name[td->mode]);
1074                 return -EPERM;
1075         }
1076 }
1077
1078 /*
1079  * Clock framework integration
1080  *
1081  * When the DFLL is being controlled by the CCF, always enter closed loop
1082  * mode when the clk is enabled. This requires that a DFLL rate request
1083  * has been set beforehand, which implies that a clk_set_rate() call is
1084  * always required before a clk_enable().
1085  */
1086
1087 static int dfll_clk_is_enabled(struct clk_hw *hw)
1088 {
1089         struct tegra_dfll *td = clk_hw_to_dfll(hw);
1090
1091         return dfll_is_running(td);
1092 }
1093
1094 static int dfll_clk_enable(struct clk_hw *hw)
1095 {
1096         struct tegra_dfll *td = clk_hw_to_dfll(hw);
1097         int ret;
1098
1099         ret = dfll_enable(td);
1100         if (ret)
1101                 return ret;
1102
1103         ret = dfll_lock(td);
1104         if (ret)
1105                 dfll_disable(td);
1106
1107         return ret;
1108 }
1109
1110 static void dfll_clk_disable(struct clk_hw *hw)
1111 {
1112         struct tegra_dfll *td = clk_hw_to_dfll(hw);
1113         int ret;
1114
1115         ret = dfll_unlock(td);
1116         if (!ret)
1117                 dfll_disable(td);
1118 }
1119
1120 static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
1121                                           unsigned long parent_rate)
1122 {
1123         struct tegra_dfll *td = clk_hw_to_dfll(hw);
1124
1125         return td->last_unrounded_rate;
1126 }
1127
1128 /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
1129 static int dfll_clk_determine_rate(struct clk_hw *hw,
1130                                    struct clk_rate_request *clk_req)
1131 {
1132         struct tegra_dfll *td = clk_hw_to_dfll(hw);
1133         struct dfll_rate_req req;
1134         int ret;
1135
1136         ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
1137         if (ret)
1138                 return ret;
1139
1140         /*
1141          * Don't set the rounded rate, since it doesn't really matter as
1142          * the output rate will be voltage controlled anyway, and cpufreq
1143          * freaks out if any rounding happens.
1144          */
1145
1146         return 0;
1147 }
1148
1149 static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1150                              unsigned long parent_rate)
1151 {
1152         struct tegra_dfll *td = clk_hw_to_dfll(hw);
1153
1154         return dfll_request_rate(td, rate);
1155 }
1156
1157 static const struct clk_ops dfll_clk_ops = {
1158         .is_enabled     = dfll_clk_is_enabled,
1159         .enable         = dfll_clk_enable,
1160         .disable        = dfll_clk_disable,
1161         .recalc_rate    = dfll_clk_recalc_rate,
1162         .determine_rate = dfll_clk_determine_rate,
1163         .set_rate       = dfll_clk_set_rate,
1164 };
1165
1166 static struct clk_init_data dfll_clk_init_data = {
1167         .ops            = &dfll_clk_ops,
1168         .num_parents    = 0,
1169 };
1170
1171 /**
1172  * dfll_register_clk - register the DFLL output clock with the clock framework
1173  * @td: DFLL instance
1174  *
1175  * Register the DFLL's output clock with the Linux clock framework and register
1176  * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL
1177  * or -ENOMEM upon failure.
1178  */
1179 static int dfll_register_clk(struct tegra_dfll *td)
1180 {
1181         int ret;
1182
1183         dfll_clk_init_data.name = td->output_clock_name;
1184         td->dfll_clk_hw.init = &dfll_clk_init_data;
1185
1186         td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);
1187         if (IS_ERR(td->dfll_clk)) {
1188                 dev_err(td->dev, "DFLL clock registration error\n");
1189                 return -EINVAL;
1190         }
1191
1192         ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,
1193                                   td->dfll_clk);
1194         if (ret) {
1195                 dev_err(td->dev, "of_clk_add_provider() failed\n");
1196
1197                 clk_unregister(td->dfll_clk);
1198                 return ret;
1199         }
1200
1201         return 0;
1202 }
1203
1204 /**
1205  * dfll_unregister_clk - unregister the DFLL output clock
1206  * @td: DFLL instance
1207  *
1208  * Unregister the DFLL's output clock from the Linux clock framework
1209  * and from clkdev. No return value.
1210  */
1211 static void dfll_unregister_clk(struct tegra_dfll *td)
1212 {
1213         of_clk_del_provider(td->dev->of_node);
1214         clk_unregister(td->dfll_clk);
1215         td->dfll_clk = NULL;
1216 }
1217
1218 /*
1219  * Debugfs interface
1220  */
1221
1222 #ifdef CONFIG_DEBUG_FS
1223 /*
1224  * Monitor control
1225  */
1226
1227 /**
1228  * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
1229  * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
1230  * @ref_rate: DFLL reference clock rate
1231  *
1232  * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
1233  * per second. Returns the converted value.
1234  */
1235 static u64 dfll_calc_monitored_rate(u32 monitor_data,
1236                                     unsigned long ref_rate)
1237 {
1238         return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
1239 }
1240
1241 /**
1242  * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
1243  * @td: DFLL instance
1244  *
1245  * If the DFLL is enabled, return the last rate reported by the DFLL's
1246  * internal monitoring hardware. This works in both open-loop and
1247  * closed-loop mode, and takes the output scaler setting into account.
1248  * Assumes that the monitor was programmed to monitor frequency before
1249  * the sample period started. If the driver believes that the DFLL is
1250  * currently uninitialized or disabled, it will return 0, since
1251  * otherwise the DFLL monitor data register will return the last
1252  * measured rate from when the DFLL was active.
1253  */
1254 static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
1255 {
1256         u32 v, s;
1257         u64 pre_scaler_rate, post_scaler_rate;
1258
1259         if (!dfll_is_running(td))
1260                 return 0;
1261
1262         v = dfll_readl(td, DFLL_MONITOR_DATA);
1263         v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
1264         pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
1265
1266         s = dfll_readl(td, DFLL_FREQ_REQ);
1267         s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
1268         post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
1269
1270         return post_scaler_rate;
1271 }
1272
1273 static int attr_enable_get(void *data, u64 *val)
1274 {
1275         struct tegra_dfll *td = data;
1276
1277         *val = dfll_is_running(td);
1278
1279         return 0;
1280 }
1281 static int attr_enable_set(void *data, u64 val)
1282 {
1283         struct tegra_dfll *td = data;
1284
1285         return val ? dfll_enable(td) : dfll_disable(td);
1286 }
1287 DEFINE_DEBUGFS_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,
1288                          "%llu\n");
1289
1290 static int attr_lock_get(void *data, u64 *val)
1291 {
1292         struct tegra_dfll *td = data;
1293
1294         *val = (td->mode == DFLL_CLOSED_LOOP);
1295
1296         return 0;
1297 }
1298 static int attr_lock_set(void *data, u64 val)
1299 {
1300         struct tegra_dfll *td = data;
1301
1302         return val ? dfll_lock(td) :  dfll_unlock(td);
1303 }
1304 DEFINE_DEBUGFS_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, "%llu\n");
1305
1306 static int attr_rate_get(void *data, u64 *val)
1307 {
1308         struct tegra_dfll *td = data;
1309
1310         *val = dfll_read_monitor_rate(td);
1311
1312         return 0;
1313 }
1314
1315 static int attr_rate_set(void *data, u64 val)
1316 {
1317         struct tegra_dfll *td = data;
1318
1319         return dfll_request_rate(td, val);
1320 }
1321 DEFINE_DEBUGFS_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");
1322
1323 static int attr_registers_show(struct seq_file *s, void *data)
1324 {
1325         u32 val, offs;
1326         struct tegra_dfll *td = s->private;
1327
1328         seq_puts(s, "CONTROL REGISTERS:\n");
1329         for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) {
1330                 if (offs == DFLL_OUTPUT_CFG)
1331                         val = dfll_i2c_readl(td, offs);
1332                 else
1333                         val = dfll_readl(td, offs);
1334                 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val);
1335         }
1336
1337         seq_puts(s, "\nI2C and INTR REGISTERS:\n");
1338         for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4)
1339                 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1340                            dfll_i2c_readl(td, offs));
1341         for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4)
1342                 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1343                            dfll_i2c_readl(td, offs));
1344
1345         if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {
1346                 seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
1347                 offs = DFLL_I2C_CLK_DIVISOR;
1348                 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1349                            __raw_readl(td->i2c_controller_base + offs));
1350
1351                 seq_puts(s, "\nLUT:\n");
1352                 for (offs = 0; offs <  4 * MAX_DFLL_VOLTAGES; offs += 4)
1353                         seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1354                                    __raw_readl(td->lut_base + offs));
1355         }
1356
1357         return 0;
1358 }
1359
1360 DEFINE_SHOW_ATTRIBUTE(attr_registers);
1361
1362 static void dfll_debug_init(struct tegra_dfll *td)
1363 {
1364         struct dentry *root;
1365
1366         if (!td || (td->mode == DFLL_UNINITIALIZED))
1367                 return;
1368
1369         root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
1370         td->debugfs_dir = root;
1371
1372         debugfs_create_file_unsafe("enable", 0644, root, td,
1373                                    &enable_fops);
1374         debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);
1375         debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
1376         debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);
1377 }
1378
1379 #else
1380 static void inline dfll_debug_init(struct tegra_dfll *td) { }
1381 #endif /* CONFIG_DEBUG_FS */
1382
1383 /*
1384  * DFLL initialization
1385  */
1386
1387 /**
1388  * dfll_set_default_params - program non-output related DFLL parameters
1389  * @td: DFLL instance
1390  *
1391  * During DFLL driver initialization or resume from context loss,
1392  * program parameters for the closed loop integrator, DVCO tuning,
1393  * voltage droop control and monitor control.
1394  */
1395 static void dfll_set_default_params(struct tegra_dfll *td)
1396 {
1397         u32 val;
1398
1399         val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);
1400         BUG_ON(val > DFLL_CONFIG_DIV_MASK);
1401         dfll_writel(td, val, DFLL_CONFIG);
1402
1403         val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |
1404                 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |
1405                 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |
1406                 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |
1407                 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);
1408         dfll_writel(td, val, DFLL_PARAMS);
1409
1410         dfll_tune_low(td);
1411         dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);
1412         dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);
1413 }
1414
1415 /**
1416  * dfll_init_clks - clk_get() the DFLL source clocks
1417  * @td: DFLL instance
1418  *
1419  * Call clk_get() on the DFLL source clocks and save the pointers for later
1420  * use. Returns 0 upon success or error (see devm_clk_get) if one or more
1421  * of the clocks couldn't be looked up.
1422  */
1423 static int dfll_init_clks(struct tegra_dfll *td)
1424 {
1425         td->ref_clk = devm_clk_get(td->dev, "ref");
1426         if (IS_ERR(td->ref_clk)) {
1427                 dev_err(td->dev, "missing ref clock\n");
1428                 return PTR_ERR(td->ref_clk);
1429         }
1430
1431         td->soc_clk = devm_clk_get(td->dev, "soc");
1432         if (IS_ERR(td->soc_clk)) {
1433                 dev_err(td->dev, "missing soc clock\n");
1434                 return PTR_ERR(td->soc_clk);
1435         }
1436
1437         td->i2c_clk = devm_clk_get(td->dev, "i2c");
1438         if (IS_ERR(td->i2c_clk)) {
1439                 dev_err(td->dev, "missing i2c clock\n");
1440                 return PTR_ERR(td->i2c_clk);
1441         }
1442         td->i2c_clk_rate = clk_get_rate(td->i2c_clk);
1443
1444         return 0;
1445 }
1446
1447 /**
1448  * dfll_init - Prepare the DFLL IP block for use
1449  * @td: DFLL instance
1450  *
1451  * Do everything necessary to prepare the DFLL IP block for use. The
1452  * DFLL will be left in DISABLED state. Called by dfll_probe().
1453  * Returns 0 upon success, or passes along the error from whatever
1454  * function returned it.
1455  */
1456 static int dfll_init(struct tegra_dfll *td)
1457 {
1458         int ret;
1459
1460         td->ref_rate = clk_get_rate(td->ref_clk);
1461         if (td->ref_rate != REF_CLOCK_RATE) {
1462                 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
1463                         td->ref_rate, REF_CLOCK_RATE);
1464                 return -EINVAL;
1465         }
1466
1467         reset_control_deassert(td->dvco_rst);
1468
1469         ret = clk_prepare(td->ref_clk);
1470         if (ret) {
1471                 dev_err(td->dev, "failed to prepare ref_clk\n");
1472                 return ret;
1473         }
1474
1475         ret = clk_prepare(td->soc_clk);
1476         if (ret) {
1477                 dev_err(td->dev, "failed to prepare soc_clk\n");
1478                 goto di_err1;
1479         }
1480
1481         ret = clk_prepare(td->i2c_clk);
1482         if (ret) {
1483                 dev_err(td->dev, "failed to prepare i2c_clk\n");
1484                 goto di_err2;
1485         }
1486
1487         td->last_unrounded_rate = 0;
1488
1489         pm_runtime_enable(td->dev);
1490         pm_runtime_get_sync(td->dev);
1491
1492         dfll_set_mode(td, DFLL_DISABLED);
1493         dfll_set_default_params(td);
1494
1495         if (td->soc->init_clock_trimmers)
1496                 td->soc->init_clock_trimmers();
1497
1498         dfll_set_open_loop_config(td);
1499
1500         dfll_init_out_if(td);
1501
1502         pm_runtime_put_sync(td->dev);
1503
1504         return 0;
1505
1506 di_err2:
1507         clk_unprepare(td->soc_clk);
1508 di_err1:
1509         clk_unprepare(td->ref_clk);
1510
1511         reset_control_assert(td->dvco_rst);
1512
1513         return ret;
1514 }
1515
1516 /*
1517  * DT data fetch
1518  */
1519
1520 /*
1521  * Find a PMIC voltage register-to-voltage mapping for the given voltage.
1522  * An exact voltage match is required.
1523  */
1524 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
1525 {
1526         int i, n_voltages, reg_uV,reg_volt_id, align_step;
1527
1528         if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1529                 return -EINVAL;
1530
1531         align_step = uV / td->soc->alignment.step_uv;
1532         n_voltages = regulator_count_voltages(td->vdd_reg);
1533         for (i = 0; i < n_voltages; i++) {
1534                 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1535                 if (reg_uV < 0)
1536                         break;
1537
1538                 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1539
1540                 if (align_step == reg_volt_id)
1541                         return i;
1542         }
1543
1544         dev_err(td->dev, "no voltage map entry for %d uV\n", uV);
1545         return -EINVAL;
1546 }
1547
1548 /*
1549  * Find a PMIC voltage register-to-voltage mapping for the given voltage,
1550  * rounding up to the closest supported voltage.
1551  * */
1552 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
1553 {
1554         int i, n_voltages, reg_uV, reg_volt_id, align_step;
1555
1556         if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1557                 return -EINVAL;
1558
1559         align_step = uV / td->soc->alignment.step_uv;
1560         n_voltages = regulator_count_voltages(td->vdd_reg);
1561         for (i = 0; i < n_voltages; i++) {
1562                 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1563                 if (reg_uV < 0)
1564                         break;
1565
1566                 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1567
1568                 if (align_step <= reg_volt_id)
1569                         return i;
1570         }
1571
1572         dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);
1573         return -EINVAL;
1574 }
1575
1576 /*
1577  * dfll_build_pwm_lut - build the PWM regulator lookup table
1578  * @td: DFLL instance
1579  * @v_max: Vmax from OPP table
1580  *
1581  * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC.
1582  * In this case closed loop output is controlling duty cycle directly. The s/w
1583  * look-up that maps PWM duty cycle to voltage is still built by this function.
1584  */
1585 static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
1586 {
1587         int i;
1588         unsigned long rate, reg_volt;
1589         u8 lut_bottom = MAX_DFLL_VOLTAGES;
1590         int v_min = td->soc->cvb->min_millivolts * 1000;
1591
1592         for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
1593                 reg_volt = td->lut_uv[i];
1594
1595                 /* since opp voltage is exact mv */
1596                 reg_volt = (reg_volt / 1000) * 1000;
1597                 if (reg_volt > v_max)
1598                         break;
1599
1600                 td->lut[i] = i;
1601                 if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))
1602                         lut_bottom = i;
1603         }
1604
1605         /* determine voltage boundaries */
1606         td->lut_size = i;
1607         if ((lut_bottom == MAX_DFLL_VOLTAGES) ||
1608             (lut_bottom + 1 >= td->lut_size)) {
1609                 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
1610                         td->soc->cvb->min_millivolts);
1611                 return -EINVAL;
1612         }
1613         td->lut_bottom = lut_bottom;
1614
1615         /* determine rate boundaries */
1616         rate = get_dvco_rate_below(td, td->lut_bottom);
1617         if (!rate) {
1618                 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
1619                         td->soc->cvb->min_millivolts);
1620                 return -EINVAL;
1621         }
1622         td->dvco_rate_min = rate;
1623
1624         return 0;
1625 }
1626
1627 /**
1628  * dfll_build_i2c_lut - build the I2C voltage register lookup table
1629  * @td: DFLL instance
1630  * @v_max: Vmax from OPP table
1631  *
1632  * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
1633  * PMIC voltage register values that span the entire DFLL operating range.
1634  * This function builds the look-up table based on the OPP table provided by
1635  * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1636  * register-to-voltage mapping queried from the regulator framework.
1637  *
1638  * On success, fills in td->lut and returns 0, or -err on failure.
1639  */
1640 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
1641 {
1642         unsigned long rate, v, v_opp;
1643         int ret = -EINVAL;
1644         int j, selector, lut;
1645
1646         v = td->soc->cvb->min_millivolts * 1000;
1647         lut = find_vdd_map_entry_exact(td, v);
1648         if (lut < 0)
1649                 goto out;
1650         td->lut[0] = lut;
1651         td->lut_bottom = 0;
1652
1653         for (j = 1, rate = 0; ; rate++) {
1654                 struct dev_pm_opp *opp;
1655
1656                 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1657                 if (IS_ERR(opp))
1658                         break;
1659                 v_opp = dev_pm_opp_get_voltage(opp);
1660
1661                 if (v_opp <= td->soc->cvb->min_millivolts * 1000)
1662                         td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1663
1664                 dev_pm_opp_put(opp);
1665
1666                 for (;;) {
1667                         v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
1668                         if (v >= v_opp)
1669                                 break;
1670
1671                         selector = find_vdd_map_entry_min(td, v);
1672                         if (selector < 0)
1673                                 goto out;
1674                         if (selector != td->lut[j - 1])
1675                                 td->lut[j++] = selector;
1676                 }
1677
1678                 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
1679                 selector = find_vdd_map_entry_exact(td, v);
1680                 if (selector < 0)
1681                         goto out;
1682                 if (selector != td->lut[j - 1])
1683                         td->lut[j++] = selector;
1684
1685                 if (v >= v_max)
1686                         break;
1687         }
1688         td->lut_size = j;
1689
1690         if (!td->dvco_rate_min)
1691                 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1692                         td->soc->cvb->min_millivolts);
1693         else {
1694                 ret = 0;
1695                 for (j = 0; j < td->lut_size; j++)
1696                         td->lut_uv[j] =
1697                                 regulator_list_voltage(td->vdd_reg,
1698                                                        td->lut[j]);
1699         }
1700
1701 out:
1702         return ret;
1703 }
1704
1705 static int dfll_build_lut(struct tegra_dfll *td)
1706 {
1707         unsigned long rate, v_max;
1708         struct dev_pm_opp *opp;
1709
1710         rate = ULONG_MAX;
1711         opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1712         if (IS_ERR(opp)) {
1713                 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1714                 return -EINVAL;
1715         }
1716         v_max = dev_pm_opp_get_voltage(opp);
1717         dev_pm_opp_put(opp);
1718
1719         if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1720                 return dfll_build_pwm_lut(td, v_max);
1721         else
1722                 return dfll_build_i2c_lut(td, v_max);
1723 }
1724
1725 /**
1726  * read_dt_param - helper function for reading required parameters from the DT
1727  * @td: DFLL instance
1728  * @param: DT property name
1729  * @dest: output pointer for the value read
1730  *
1731  * Read a required numeric parameter from the DFLL device node, or complain
1732  * if the property doesn't exist. Returns a boolean indicating success for
1733  * easy chaining of multiple calls to this function.
1734  */
1735 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)
1736 {
1737         int err = of_property_read_u32(td->dev->of_node, param, dest);
1738
1739         if (err < 0) {
1740                 dev_err(td->dev, "failed to read DT parameter %s: %d\n",
1741                         param, err);
1742                 return false;
1743         }
1744
1745         return true;
1746 }
1747
1748 /**
1749  * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem
1750  * @td: DFLL instance
1751  *
1752  * Read all the parameters required for operation in I2C mode. The parameters
1753  * can originate from the device tree or the regulator subsystem.
1754  * Returns 0 on success or -err on failure.
1755  */
1756 static int dfll_fetch_i2c_params(struct tegra_dfll *td)
1757 {
1758         struct regmap *regmap;
1759         struct device *i2c_dev;
1760         struct i2c_client *i2c_client;
1761         int vsel_reg, vsel_mask;
1762         int ret;
1763
1764         if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
1765                 return -EINVAL;
1766
1767         regmap = regulator_get_regmap(td->vdd_reg);
1768         i2c_dev = regmap_get_device(regmap);
1769         i2c_client = to_i2c_client(i2c_dev);
1770
1771         td->i2c_slave_addr = i2c_client->addr;
1772
1773         ret = regulator_get_hardware_vsel_register(td->vdd_reg,
1774                                                    &vsel_reg,
1775                                                    &vsel_mask);
1776         if (ret < 0) {
1777                 dev_err(td->dev,
1778                         "regulator unsuitable for DFLL I2C operation\n");
1779                 return -EINVAL;
1780         }
1781         td->i2c_reg = vsel_reg;
1782
1783         return 0;
1784 }
1785
1786 static int dfll_fetch_pwm_params(struct tegra_dfll *td)
1787 {
1788         int ret, i;
1789         u32 pwm_period;
1790
1791         if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {
1792                 dev_err(td->dev,
1793                         "Missing step or alignment info for PWM regulator");
1794                 return -EINVAL;
1795         }
1796         for (i = 0; i < MAX_DFLL_VOLTAGES; i++)
1797                 td->lut_uv[i] = td->soc->alignment.offset_uv +
1798                                 i * td->soc->alignment.step_uv;
1799
1800         ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",
1801                             &td->reg_init_uV);
1802         if (!ret) {
1803                 dev_err(td->dev, "couldn't get initialized voltage\n");
1804                 return ret;
1805         }
1806
1807         ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
1808         if (!ret) {
1809                 dev_err(td->dev, "couldn't get PWM period\n");
1810                 return ret;
1811         }
1812         td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);
1813
1814         td->pwm_pin = devm_pinctrl_get(td->dev);
1815         if (IS_ERR(td->pwm_pin)) {
1816                 dev_err(td->dev, "DT: missing pinctrl device\n");
1817                 return PTR_ERR(td->pwm_pin);
1818         }
1819
1820         td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,
1821                                                     "dvfs_pwm_enable");
1822         if (IS_ERR(td->pwm_enable_state)) {
1823                 dev_err(td->dev, "DT: missing pwm enabled state\n");
1824                 return PTR_ERR(td->pwm_enable_state);
1825         }
1826
1827         td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,
1828                                                      "dvfs_pwm_disable");
1829         if (IS_ERR(td->pwm_disable_state)) {
1830                 dev_err(td->dev, "DT: missing pwm disabled state\n");
1831                 return PTR_ERR(td->pwm_disable_state);
1832         }
1833
1834         return 0;
1835 }
1836
1837 /**
1838  * dfll_fetch_common_params - read DFLL parameters from the device tree
1839  * @td: DFLL instance
1840  *
1841  * Read all the DT parameters that are common to both I2C and PWM operation.
1842  * Returns 0 on success or -EINVAL on any failure.
1843  */
1844 static int dfll_fetch_common_params(struct tegra_dfll *td)
1845 {
1846         bool ok = true;
1847
1848         ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);
1849         ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);
1850         ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);
1851         ok &= read_dt_param(td, "nvidia,cf", &td->cf);
1852         ok &= read_dt_param(td, "nvidia,ci", &td->ci);
1853         ok &= read_dt_param(td, "nvidia,cg", &td->cg);
1854         td->cg_scale = of_property_read_bool(td->dev->of_node,
1855                                              "nvidia,cg-scale");
1856
1857         if (of_property_read_string(td->dev->of_node, "clock-output-names",
1858                                     &td->output_clock_name)) {
1859                 dev_err(td->dev, "missing clock-output-names property\n");
1860                 ok = false;
1861         }
1862
1863         return ok ? 0 : -EINVAL;
1864 }
1865
1866 /*
1867  * API exported to per-SoC platform drivers
1868  */
1869
1870 /**
1871  * tegra_dfll_register - probe a Tegra DFLL device
1872  * @pdev: DFLL platform_device *
1873  * @soc: Per-SoC integration and characterization data for this DFLL instance
1874  *
1875  * Probe and initialize a DFLL device instance. Intended to be called
1876  * by a SoC-specific shim driver that passes in per-SoC integration
1877  * and configuration data via @soc. Returns 0 on success or -err on failure.
1878  */
1879 int tegra_dfll_register(struct platform_device *pdev,
1880                         struct tegra_dfll_soc_data *soc)
1881 {
1882         struct resource *mem;
1883         struct tegra_dfll *td;
1884         int ret;
1885
1886         if (!soc) {
1887                 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n");
1888                 return -EINVAL;
1889         }
1890
1891         td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);
1892         if (!td)
1893                 return -ENOMEM;
1894         td->dev = &pdev->dev;
1895         platform_set_drvdata(pdev, td);
1896
1897         td->soc = soc;
1898
1899         td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
1900         if (IS_ERR(td->dvco_rst)) {
1901                 dev_err(td->dev, "couldn't get dvco reset\n");
1902                 return PTR_ERR(td->dvco_rst);
1903         }
1904
1905         ret = dfll_fetch_common_params(td);
1906         if (ret) {
1907                 dev_err(td->dev, "couldn't parse device tree parameters\n");
1908                 return ret;
1909         }
1910
1911         if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {
1912                 td->pmu_if = TEGRA_DFLL_PMU_PWM;
1913                 ret = dfll_fetch_pwm_params(td);
1914         } else  {
1915                 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
1916                 if (IS_ERR(td->vdd_reg)) {
1917                         dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
1918                         return PTR_ERR(td->vdd_reg);
1919                 }
1920                 td->pmu_if = TEGRA_DFLL_PMU_I2C;
1921                 ret = dfll_fetch_i2c_params(td);
1922         }
1923         if (ret)
1924                 return ret;
1925
1926         ret = dfll_build_lut(td);
1927         if (ret) {
1928                 dev_err(td->dev, "couldn't build LUT\n");
1929                 return ret;
1930         }
1931
1932         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1933         if (!mem) {
1934                 dev_err(td->dev, "no control register resource\n");
1935                 return -ENODEV;
1936         }
1937
1938         td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1939         if (!td->base) {
1940                 dev_err(td->dev, "couldn't ioremap DFLL control registers\n");
1941                 return -ENODEV;
1942         }
1943
1944         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1945         if (!mem) {
1946                 dev_err(td->dev, "no i2c_base resource\n");
1947                 return -ENODEV;
1948         }
1949
1950         td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1951         if (!td->i2c_base) {
1952                 dev_err(td->dev, "couldn't ioremap i2c_base resource\n");
1953                 return -ENODEV;
1954         }
1955
1956         mem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1957         if (!mem) {
1958                 dev_err(td->dev, "no i2c_controller_base resource\n");
1959                 return -ENODEV;
1960         }
1961
1962         td->i2c_controller_base = devm_ioremap(td->dev, mem->start,
1963                                                resource_size(mem));
1964         if (!td->i2c_controller_base) {
1965                 dev_err(td->dev,
1966                         "couldn't ioremap i2c_controller_base resource\n");
1967                 return -ENODEV;
1968         }
1969
1970         mem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1971         if (!mem) {
1972                 dev_err(td->dev, "no lut_base resource\n");
1973                 return -ENODEV;
1974         }
1975
1976         td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1977         if (!td->lut_base) {
1978                 dev_err(td->dev,
1979                         "couldn't ioremap lut_base resource\n");
1980                 return -ENODEV;
1981         }
1982
1983         ret = dfll_init_clks(td);
1984         if (ret) {
1985                 dev_err(&pdev->dev, "DFLL clock init error\n");
1986                 return ret;
1987         }
1988
1989         /* Enable the clocks and set the device up */
1990         ret = dfll_init(td);
1991         if (ret)
1992                 return ret;
1993
1994         ret = dfll_register_clk(td);
1995         if (ret) {
1996                 dev_err(&pdev->dev, "DFLL clk registration failed\n");
1997                 return ret;
1998         }
1999
2000         dfll_debug_init(td);
2001
2002         return 0;
2003 }
2004 EXPORT_SYMBOL(tegra_dfll_register);
2005
2006 /**
2007  * tegra_dfll_unregister - release all of the DFLL driver resources for a device
2008  * @pdev: DFLL platform_device *
2009  *
2010  * Unbind this driver from the DFLL hardware device represented by
2011  * @pdev. The DFLL must be disabled for this to succeed. Returns a
2012  * soc pointer upon success or -EBUSY if the DFLL is still active.
2013  */
2014 struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
2015 {
2016         struct tegra_dfll *td = platform_get_drvdata(pdev);
2017
2018         /* Try to prevent removal while the DFLL is active */
2019         if (td->mode != DFLL_DISABLED) {
2020                 dev_err(&pdev->dev,
2021                         "must disable DFLL before removing driver\n");
2022                 return ERR_PTR(-EBUSY);
2023         }
2024
2025         debugfs_remove_recursive(td->debugfs_dir);
2026
2027         dfll_unregister_clk(td);
2028         pm_runtime_disable(&pdev->dev);
2029
2030         clk_unprepare(td->ref_clk);
2031         clk_unprepare(td->soc_clk);
2032         clk_unprepare(td->i2c_clk);
2033
2034         reset_control_assert(td->dvco_rst);
2035
2036         return td->soc;
2037 }
2038 EXPORT_SYMBOL(tegra_dfll_unregister);