1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/kernel.h>
9 #include <linux/slab.h>
10 #include <linux/clk-provider.h>
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
17 #define get_max_div(d) div_mask(d)
19 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
22 unsigned long parent_rate)
26 div = div_frac_get(rate, parent_rate, divider->width,
27 divider->frac_width, divider->flags);
35 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
36 unsigned long parent_rate)
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
41 u64 rate = parent_rate;
43 reg = readl_relaxed(divider->reg) >> divider->shift;
44 div = reg & div_mask(divider);
46 mul = get_mul(divider);
56 static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
59 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
61 unsigned long output_rate = *prate;
66 div = get_div(divider, rate, output_rate);
70 mul = get_mul(divider);
72 return DIV_ROUND_UP(output_rate * mul, div + mul);
75 static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
76 unsigned long parent_rate)
78 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
80 unsigned long flags = 0;
83 div = get_div(divider, rate, parent_rate);
88 spin_lock_irqsave(divider->lock, flags);
90 val = readl_relaxed(divider->reg);
91 val &= ~(div_mask(divider) << divider->shift);
92 val |= div << divider->shift;
94 if (divider->flags & TEGRA_DIVIDER_UART) {
96 val |= PERIPH_CLK_UART_DIV_ENB;
98 val &= ~PERIPH_CLK_UART_DIV_ENB;
101 if (divider->flags & TEGRA_DIVIDER_FIXED)
102 val |= pll_out_override(divider);
104 writel_relaxed(val, divider->reg);
107 spin_unlock_irqrestore(divider->lock, flags);
112 const struct clk_ops tegra_clk_frac_div_ops = {
113 .recalc_rate = clk_frac_div_recalc_rate,
114 .set_rate = clk_frac_div_set_rate,
115 .round_rate = clk_frac_div_round_rate,
118 struct clk *tegra_clk_register_divider(const char *name,
119 const char *parent_name, void __iomem *reg,
120 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
121 u8 frac_width, spinlock_t *lock)
123 struct tegra_clk_frac_div *divider;
125 struct clk_init_data init;
127 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
129 pr_err("%s: could not allocate fractional divider clk\n",
131 return ERR_PTR(-ENOMEM);
135 init.ops = &tegra_clk_frac_div_ops;
137 init.parent_names = parent_name ? &parent_name : NULL;
138 init.num_parents = parent_name ? 1 : 0;
141 divider->shift = shift;
142 divider->width = width;
143 divider->frac_width = frac_width;
144 divider->lock = lock;
145 divider->flags = clk_divider_flags;
147 /* Data in .init is copied by clk_register(), so stack variable OK */
148 divider->hw.init = &init;
150 clk = clk_register(NULL, ÷r->hw);
157 static const struct clk_div_table mc_div_table[] = {
158 { .val = 0, .div = 2 },
159 { .val = 1, .div = 1 },
160 { .val = 0, .div = 0 },
163 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
164 void __iomem *reg, spinlock_t *lock)
166 return clk_register_divider_table(NULL, name, parent_name,
168 reg, 16, 1, CLK_DIVIDER_READ_ONLY,