1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides IDs for clocks common between several Tegra SoCs
5 #ifndef _TEGRA_CLK_ID_H
6 #define _TEGRA_CLK_ID_H
50 tegra_clk_clk_out_1_mux,
52 tegra_clk_clk_out_2_mux,
54 tegra_clk_clk_out_3_mux,
100 tegra_clk_hda2codec_2x,
101 tegra_clk_hda2codec_2x_8,
104 tegra_clk_hdmi_audio,
153 tegra_clk_pll_a_out0,
159 tegra_clk_pll_c4_out0,
160 tegra_clk_pll_c4_out1,
161 tegra_clk_pll_c4_out2,
162 tegra_clk_pll_c4_out3,
163 tegra_clk_pll_c_out1,
166 tegra_clk_pll_d2_out0,
167 tegra_clk_pll_d_out0,
169 tegra_clk_pll_e_out0,
172 tegra_clk_pll_m_out1,
175 tegra_clk_pll_p_out1,
176 tegra_clk_pll_p_out2,
177 tegra_clk_pll_p_out2_int,
178 tegra_clk_pll_p_out3,
179 tegra_clk_pll_p_out4,
180 tegra_clk_pll_p_out4_cpu,
181 tegra_clk_pll_p_out5,
182 tegra_clk_pll_p_out_hsio,
183 tegra_clk_pll_p_out_xusb,
184 tegra_clk_pll_p_out_cpu,
185 tegra_clk_pll_p_out_adsp,
187 tegra_clk_pll_re_out,
188 tegra_clk_pll_re_vco,
191 tegra_clk_pll_u_out1,
192 tegra_clk_pll_u_out2,
194 tegra_clk_pll_u_480m,
198 tegra_clk_pll_x_out0,
206 tegra_clk_sata_oob_8,
224 tegra_clk_sdmmc_legacy,
237 tegra_clk_soc_therm_8,
245 tegra_clk_spdif_in_8,
246 tegra_clk_spdif_in_sync,
269 tegra_clk_usb2_hsic_trk,
285 tegra_clk_vimclk_sync,
287 tegra_clk_vi_sensor_8,
288 tegra_clk_vi_sensor_9,
289 tegra_clk_vi_sensor2,
290 tegra_clk_vi_sensor2_8,
292 tegra_clk_xusb_dev_src,
293 tegra_clk_xusb_dev_src_8,
294 tegra_clk_xusb_falcon_src,
295 tegra_clk_xusb_falcon_src_8,
296 tegra_clk_xusb_fs_src,
299 tegra_clk_xusb_host_src,
300 tegra_clk_xusb_host_src_8,
301 tegra_clk_xusb_hs_src,
302 tegra_clk_xusb_hs_src_4,
304 tegra_clk_xusb_ss_src,
305 tegra_clk_xusb_ss_src_8,
306 tegra_clk_xusb_ss_div2,
307 tegra_clk_xusb_ssp_src,
315 tegra_clk_dmic1_sync_clk,
316 tegra_clk_dmic2_sync_clk,
317 tegra_clk_dmic3_sync_clk,
318 tegra_clk_dmic1_sync_clk_mux,
319 tegra_clk_dmic2_sync_clk_mux,
320 tegra_clk_dmic3_sync_clk_mux,
323 tegra_clk_pll_a_out_adsp,
324 tegra_clk_pll_a_out0_out_adsp,
330 #endif /* _TEGRA_CLK_ID_H */