1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/slab.h>
8 #include <linux/delay.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
15 #define PLL_BASE_BYPASS BIT(31)
16 #define PLL_BASE_ENABLE BIT(30)
17 #define PLL_BASE_REF_ENABLE BIT(29)
18 #define PLL_BASE_OVERRIDE BIT(28)
20 #define PLL_BASE_DIVP_SHIFT 20
21 #define PLL_BASE_DIVP_WIDTH 3
22 #define PLL_BASE_DIVN_SHIFT 8
23 #define PLL_BASE_DIVN_WIDTH 10
24 #define PLL_BASE_DIVM_SHIFT 0
25 #define PLL_BASE_DIVM_WIDTH 5
26 #define PLLU_POST_DIVP_MASK 0x1
28 #define PLL_MISC_DCCON_SHIFT 20
29 #define PLL_MISC_CPCON_SHIFT 8
30 #define PLL_MISC_CPCON_WIDTH 4
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
32 #define PLL_MISC_LFCON_SHIFT 4
33 #define PLL_MISC_LFCON_WIDTH 4
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
36 #define PLL_MISC_VCOCON_WIDTH 4
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
39 #define OUT_OF_TABLE_CPCON 8
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
42 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
43 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
45 #define PLL_POST_LOCK_DELAY 50
47 #define PLLDU_LFCON_SET_DIVN 600
49 #define PLLE_BASE_DIVCML_SHIFT 24
50 #define PLLE_BASE_DIVCML_MASK 0xf
51 #define PLLE_BASE_DIVP_SHIFT 16
52 #define PLLE_BASE_DIVP_WIDTH 6
53 #define PLLE_BASE_DIVN_SHIFT 8
54 #define PLLE_BASE_DIVN_WIDTH 8
55 #define PLLE_BASE_DIVM_SHIFT 0
56 #define PLLE_BASE_DIVM_WIDTH 8
57 #define PLLE_BASE_ENABLE BIT(31)
59 #define PLLE_MISC_SETUP_BASE_SHIFT 16
60 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
61 #define PLLE_MISC_LOCK_ENABLE BIT(9)
62 #define PLLE_MISC_READY BIT(15)
63 #define PLLE_MISC_SETUP_EX_SHIFT 2
64 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
65 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
66 PLLE_MISC_SETUP_EX_MASK)
67 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
69 #define PLLE_SS_CTRL 0x68
70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
71 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
72 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
73 #define PLLE_SS_CNTL_CENTER BIT(14)
74 #define PLLE_SS_CNTL_INVERT BIT(15)
75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
77 #define PLLE_SS_MAX_MASK 0x1ff
78 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
79 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
80 #define PLLE_SS_INC_MASK (0xff << 16)
81 #define PLLE_SS_INC_VAL (0x1 << 16)
82 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
83 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
84 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
85 #define PLLE_SS_COEFFICIENTS_MASK \
86 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
87 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
88 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
89 PLLE_SS_INCINTRV_VAL_TEGRA114)
90 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
91 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
92 PLLE_SS_INCINTRV_VAL_TEGRA210)
94 #define PLLE_AUX_PLLP_SEL BIT(2)
95 #define PLLE_AUX_USE_LOCKDET BIT(3)
96 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
97 #define PLLE_AUX_SS_SWCTL BIT(6)
98 #define PLLE_AUX_SEQ_ENABLE BIT(24)
99 #define PLLE_AUX_SEQ_START_STATE BIT(25)
100 #define PLLE_AUX_PLLRE_SEL BIT(28)
101 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
103 #define XUSBIO_PLL_CFG0 0x51c
104 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
105 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
106 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
107 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
108 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
110 #define SATA_PLL_CFG0 0x490
111 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
112 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
113 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
114 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
116 #define PLLE_MISC_PLLE_PTS BIT(8)
117 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
118 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
119 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
120 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
121 #define PLLE_MISC_VREG_CTRL_SHIFT 2
122 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
124 #define PLLCX_MISC_STROBE BIT(31)
125 #define PLLCX_MISC_RESET BIT(30)
126 #define PLLCX_MISC_SDM_DIV_SHIFT 28
127 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
128 #define PLLCX_MISC_FILT_DIV_SHIFT 26
129 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
130 #define PLLCX_MISC_ALPHA_SHIFT 18
131 #define PLLCX_MISC_DIV_LOW_RANGE \
132 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
133 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
134 #define PLLCX_MISC_DIV_HIGH_RANGE \
135 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
136 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
137 #define PLLCX_MISC_COEF_LOW_RANGE \
138 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
139 #define PLLCX_MISC_KA_SHIFT 2
140 #define PLLCX_MISC_KB_SHIFT 9
141 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
142 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
143 PLLCX_MISC_DIV_LOW_RANGE | \
145 #define PLLCX_MISC1_DEFAULT 0x000d2308
146 #define PLLCX_MISC2_DEFAULT 0x30211200
147 #define PLLCX_MISC3_DEFAULT 0x200
149 #define PMC_SATA_PWRGT 0x1ac
150 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
151 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
153 #define PLLSS_MISC_KCP 0
154 #define PLLSS_MISC_KVCO 0
155 #define PLLSS_MISC_SETUP 0
156 #define PLLSS_EN_SDM 0
157 #define PLLSS_EN_SSC 0
158 #define PLLSS_EN_DITHER2 0
159 #define PLLSS_EN_DITHER 1
160 #define PLLSS_SDM_RESET 0
161 #define PLLSS_CLAMP 0
162 #define PLLSS_SDM_SSC_MAX 0
163 #define PLLSS_SDM_SSC_MIN 0
164 #define PLLSS_SDM_SSC_STEP 0
165 #define PLLSS_SDM_DIN 0
166 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
167 (PLLSS_MISC_KVCO << 24) | \
169 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
170 (PLLSS_EN_SSC << 30) | \
171 (PLLSS_EN_DITHER2 << 29) | \
172 (PLLSS_EN_DITHER << 28) | \
173 (PLLSS_SDM_RESET) << 27 | \
175 #define PLLSS_CTRL1_DEFAULT \
176 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
177 #define PLLSS_CTRL2_DEFAULT \
178 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
179 #define PLLSS_LOCK_OVERRIDE BIT(24)
180 #define PLLSS_REF_SRC_SEL_SHIFT 25
181 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
183 #define UTMIP_PLL_CFG1 0x484
184 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
185 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
186 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
187 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
188 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
189 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
190 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
192 #define UTMIP_PLL_CFG2 0x488
193 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
194 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
195 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
197 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
198 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
199 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
200 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
201 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
202 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
203 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
208 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
210 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
211 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
213 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
215 #define PLLU_HW_PWRDN_CFG0 0x530
216 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
217 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
218 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
219 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
220 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
221 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
223 #define XUSB_PLL_CFG0 0x534
224 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
225 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
227 #define PLLU_BASE_CLKENABLE_USB BIT(21)
228 #define PLLU_BASE_OVERRIDE BIT(24)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
244 #define mask(w) ((1 << (w)) - 1)
245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
248 mask(p->params->div_nmp->divp_width))
249 #define sdm_din_mask(p) p->params->sdm_din_mask
250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
256 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
260 #define divm_max(p) (divm_mask(p))
261 #define divn_max(p) (divn_mask(p))
262 #define divp_max(p) (1 << (divp_mask(p)))
264 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
265 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
267 static struct div_nmp default_nmp = {
268 .divn_shift = PLL_BASE_DIVN_SHIFT,
269 .divn_width = PLL_BASE_DIVN_WIDTH,
270 .divm_shift = PLL_BASE_DIVM_SHIFT,
271 .divm_width = PLL_BASE_DIVM_WIDTH,
272 .divp_shift = PLL_BASE_DIVP_SHIFT,
273 .divp_width = PLL_BASE_DIVP_WIDTH,
276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
286 val = pll_readl_misc(pll);
287 val |= BIT(pll->params->lock_enable_bit_idx);
288 pll_writel_misc(val, pll);
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
295 void __iomem *lock_addr;
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
298 udelay(pll->params->lock_delay);
302 lock_addr = pll->clk_base;
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
304 lock_addr += pll->params->misc_reg;
306 lock_addr += pll->params->base_reg;
308 lock_mask = pll->params->lock_mask;
310 for (i = 0; i < pll->params->lock_delay; i++) {
311 val = readl_relaxed(lock_addr);
312 if ((val & lock_mask) == lock_mask) {
313 udelay(PLL_POST_LOCK_DELAY);
316 udelay(2); /* timeout = 2 * lock time */
319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
320 clk_hw_get_name(&pll->hw));
325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
327 return clk_pll_wait_for_lock(pll);
330 static int clk_pll_is_enabled(struct clk_hw *hw)
332 struct tegra_clk_pll *pll = to_clk_pll(hw);
335 if (pll->params->flags & TEGRA_PLLM) {
336 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
337 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
338 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
341 val = pll_readl_base(pll);
343 return val & PLL_BASE_ENABLE ? 1 : 0;
346 static void _clk_pll_enable(struct clk_hw *hw)
348 struct tegra_clk_pll *pll = to_clk_pll(hw);
351 if (pll->params->iddq_reg) {
352 val = pll_readl(pll->params->iddq_reg, pll);
353 val &= ~BIT(pll->params->iddq_bit_idx);
354 pll_writel(val, pll->params->iddq_reg, pll);
358 if (pll->params->reset_reg) {
359 val = pll_readl(pll->params->reset_reg, pll);
360 val &= ~BIT(pll->params->reset_bit_idx);
361 pll_writel(val, pll->params->reset_reg, pll);
364 clk_pll_enable_lock(pll);
366 val = pll_readl_base(pll);
367 if (pll->params->flags & TEGRA_PLL_BYPASS)
368 val &= ~PLL_BASE_BYPASS;
369 val |= PLL_BASE_ENABLE;
370 pll_writel_base(val, pll);
372 if (pll->params->flags & TEGRA_PLLM) {
373 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
374 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
375 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
379 static void _clk_pll_disable(struct clk_hw *hw)
381 struct tegra_clk_pll *pll = to_clk_pll(hw);
384 val = pll_readl_base(pll);
385 if (pll->params->flags & TEGRA_PLL_BYPASS)
386 val &= ~PLL_BASE_BYPASS;
387 val &= ~PLL_BASE_ENABLE;
388 pll_writel_base(val, pll);
390 if (pll->params->flags & TEGRA_PLLM) {
391 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
392 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
393 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
396 if (pll->params->reset_reg) {
397 val = pll_readl(pll->params->reset_reg, pll);
398 val |= BIT(pll->params->reset_bit_idx);
399 pll_writel(val, pll->params->reset_reg, pll);
402 if (pll->params->iddq_reg) {
403 val = pll_readl(pll->params->iddq_reg, pll);
404 val |= BIT(pll->params->iddq_bit_idx);
405 pll_writel(val, pll->params->iddq_reg, pll);
410 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
412 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
413 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
415 val |= pll->params->ssc_ctrl_en_mask;
416 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
420 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
425 val &= ~pll->params->ssc_ctrl_en_mask;
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
430 static int clk_pll_enable(struct clk_hw *hw)
432 struct tegra_clk_pll *pll = to_clk_pll(hw);
433 unsigned long flags = 0;
436 if (clk_pll_is_enabled(hw))
440 spin_lock_irqsave(pll->lock, flags);
444 ret = clk_pll_wait_for_lock(pll);
446 pll_clk_start_ss(pll);
449 spin_unlock_irqrestore(pll->lock, flags);
454 static void clk_pll_disable(struct clk_hw *hw)
456 struct tegra_clk_pll *pll = to_clk_pll(hw);
457 unsigned long flags = 0;
460 spin_lock_irqsave(pll->lock, flags);
462 pll_clk_stop_ss(pll);
464 _clk_pll_disable(hw);
467 spin_unlock_irqrestore(pll->lock, flags);
470 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
472 struct tegra_clk_pll *pll = to_clk_pll(hw);
473 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
476 while (p_tohw->pdiv) {
477 if (p_div <= p_tohw->pdiv)
478 return p_tohw->hw_val;
486 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
488 return _p_div_to_hw(&pll->hw, p_div);
491 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
493 struct tegra_clk_pll *pll = to_clk_pll(hw);
494 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
497 while (p_tohw->pdiv) {
498 if (p_div_hw == p_tohw->hw_val)
505 return 1 << p_div_hw;
508 static int _get_table_rate(struct clk_hw *hw,
509 struct tegra_clk_pll_freq_table *cfg,
510 unsigned long rate, unsigned long parent_rate)
512 struct tegra_clk_pll *pll = to_clk_pll(hw);
513 struct tegra_clk_pll_freq_table *sel;
516 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
517 if (sel->input_rate == parent_rate &&
518 sel->output_rate == rate)
521 if (sel->input_rate == 0)
524 if (pll->params->pdiv_tohw) {
525 p = _p_div_to_hw(hw, sel->p);
532 cfg->input_rate = sel->input_rate;
533 cfg->output_rate = sel->output_rate;
537 cfg->cpcon = sel->cpcon;
538 cfg->sdm_data = sel->sdm_data;
543 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
544 unsigned long rate, unsigned long parent_rate)
546 struct tegra_clk_pll *pll = to_clk_pll(hw);
551 switch (parent_rate) {
554 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
557 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
561 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
566 * PLL_P_OUT1 rate is not listed in PLLA table
568 cfreq = parent_rate / (parent_rate / 1000000);
571 pr_err("%s Unexpected reference rate %lu\n",
572 __func__, parent_rate);
576 /* Raise VCO to guarantee 0.5% accuracy */
577 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
578 cfg->output_rate <<= 1)
581 cfg->m = parent_rate / cfreq;
582 cfg->n = cfg->output_rate / cfreq;
583 cfg->cpcon = OUT_OF_TABLE_CPCON;
585 if (cfg->m == 0 || cfg->m > divm_max(pll) ||
586 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
587 cfg->output_rate > pll->params->vco_max) {
591 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
592 cfg->output_rate >>= p_div;
594 if (pll->params->pdiv_tohw) {
595 ret = _p_div_to_hw(hw, 1 << p_div);
607 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
608 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
609 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
610 * to indicate that SDM is disabled.
612 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
614 static void clk_pll_set_sdm_data(struct clk_hw *hw,
615 struct tegra_clk_pll_freq_table *cfg)
617 struct tegra_clk_pll *pll = to_clk_pll(hw);
621 if (!pll->params->sdm_din_reg)
625 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
626 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
627 pll_writel_sdm_din(val, pll);
630 val = pll_readl_sdm_ctrl(pll);
631 enabled = (val & sdm_en_mask(pll));
633 if (cfg->sdm_data == 0 && enabled)
634 val &= ~pll->params->sdm_ctrl_en_mask;
636 if (cfg->sdm_data != 0 && !enabled)
637 val |= pll->params->sdm_ctrl_en_mask;
639 pll_writel_sdm_ctrl(val, pll);
642 static void _update_pll_mnp(struct tegra_clk_pll *pll,
643 struct tegra_clk_pll_freq_table *cfg)
646 struct tegra_clk_pll_params *params = pll->params;
647 struct div_nmp *div_nmp = params->div_nmp;
649 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
650 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
651 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
652 val = pll_override_readl(params->pmc_divp_reg, pll);
653 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
654 val |= cfg->p << div_nmp->override_divp_shift;
655 pll_override_writel(val, params->pmc_divp_reg, pll);
657 val = pll_override_readl(params->pmc_divnm_reg, pll);
658 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
659 (divn_mask(pll) << div_nmp->override_divn_shift));
660 val |= (cfg->m << div_nmp->override_divm_shift) |
661 (cfg->n << div_nmp->override_divn_shift);
662 pll_override_writel(val, params->pmc_divnm_reg, pll);
664 val = pll_readl_base(pll);
666 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
667 divp_mask_shifted(pll));
669 val |= (cfg->m << divm_shift(pll)) |
670 (cfg->n << divn_shift(pll)) |
671 (cfg->p << divp_shift(pll));
673 pll_writel_base(val, pll);
675 clk_pll_set_sdm_data(&pll->hw, cfg);
679 static void _get_pll_mnp(struct tegra_clk_pll *pll,
680 struct tegra_clk_pll_freq_table *cfg)
683 struct tegra_clk_pll_params *params = pll->params;
684 struct div_nmp *div_nmp = params->div_nmp;
686 *cfg = (struct tegra_clk_pll_freq_table) { };
688 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
689 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
690 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
691 val = pll_override_readl(params->pmc_divp_reg, pll);
692 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
694 val = pll_override_readl(params->pmc_divnm_reg, pll);
695 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
696 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
698 val = pll_readl_base(pll);
700 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
701 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
702 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
704 if (pll->params->sdm_din_reg) {
705 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
706 val = pll_readl_sdm_din(pll);
707 val &= sdm_din_mask(pll);
708 cfg->sdm_data = sdin_din_to_data(val);
714 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
715 struct tegra_clk_pll_freq_table *cfg,
720 val = pll_readl_misc(pll);
722 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
723 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
725 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
726 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
727 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
728 val |= 1 << PLL_MISC_LFCON_SHIFT;
729 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
730 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
731 if (rate >= (pll->params->vco_max >> 1))
732 val |= 1 << PLL_MISC_DCCON_SHIFT;
735 pll_writel_misc(val, pll);
738 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
741 struct tegra_clk_pll *pll = to_clk_pll(hw);
742 struct tegra_clk_pll_freq_table old_cfg;
745 state = clk_pll_is_enabled(hw);
747 _get_pll_mnp(pll, &old_cfg);
749 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
750 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
751 ret = pll->params->dyn_ramp(pll, cfg);
757 pll_clk_stop_ss(pll);
758 _clk_pll_disable(hw);
761 if (!pll->params->defaults_set && pll->params->set_defaults)
762 pll->params->set_defaults(pll);
764 _update_pll_mnp(pll, cfg);
766 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
767 _update_pll_cpcon(pll, cfg, rate);
771 ret = clk_pll_wait_for_lock(pll);
772 pll_clk_start_ss(pll);
778 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
779 unsigned long parent_rate)
781 struct tegra_clk_pll *pll = to_clk_pll(hw);
782 struct tegra_clk_pll_freq_table cfg, old_cfg;
783 unsigned long flags = 0;
786 if (pll->params->flags & TEGRA_PLL_FIXED) {
787 if (rate != pll->params->fixed_rate) {
788 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
789 __func__, clk_hw_get_name(hw),
790 pll->params->fixed_rate, rate);
796 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
797 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
798 pr_err("%s: Failed to set %s rate %lu\n", __func__,
799 clk_hw_get_name(hw), rate);
804 spin_lock_irqsave(pll->lock, flags);
806 _get_pll_mnp(pll, &old_cfg);
807 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
810 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
811 old_cfg.sdm_data != cfg.sdm_data)
812 ret = _program_pll(hw, &cfg, rate);
815 spin_unlock_irqrestore(pll->lock, flags);
820 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
821 unsigned long *prate)
823 struct tegra_clk_pll *pll = to_clk_pll(hw);
824 struct tegra_clk_pll_freq_table cfg;
826 if (pll->params->flags & TEGRA_PLL_FIXED) {
827 /* PLLM/MB are used for memory; we do not change rate */
828 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
829 return clk_hw_get_rate(hw);
830 return pll->params->fixed_rate;
833 if (_get_table_rate(hw, &cfg, rate, *prate) &&
834 pll->params->calc_rate(hw, &cfg, rate, *prate))
837 return cfg.output_rate;
840 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
841 unsigned long parent_rate)
843 struct tegra_clk_pll *pll = to_clk_pll(hw);
844 struct tegra_clk_pll_freq_table cfg;
846 u64 rate = parent_rate;
849 val = pll_readl_base(pll);
851 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
854 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
855 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
856 !(val & PLL_BASE_OVERRIDE)) {
857 struct tegra_clk_pll_freq_table sel;
858 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
860 pr_err("Clock %s has unknown fixed frequency\n",
861 clk_hw_get_name(hw));
864 return pll->params->fixed_rate;
867 _get_pll_mnp(pll, &cfg);
869 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
872 pdiv = _hw_to_p_div(hw, cfg.p);
874 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
875 clk_hw_get_name(hw), cfg.p);
880 if (pll->params->set_gain)
881 pll->params->set_gain(&cfg);
891 static int clk_plle_training(struct tegra_clk_pll *pll)
894 unsigned long timeout;
900 * PLLE is already disabled, and setup cleared;
901 * create falling edge on PLLE IDDQ input.
903 val = readl(pll->pmc + PMC_SATA_PWRGT);
904 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
905 writel(val, pll->pmc + PMC_SATA_PWRGT);
907 val = readl(pll->pmc + PMC_SATA_PWRGT);
908 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
909 writel(val, pll->pmc + PMC_SATA_PWRGT);
911 val = readl(pll->pmc + PMC_SATA_PWRGT);
912 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
913 writel(val, pll->pmc + PMC_SATA_PWRGT);
915 val = pll_readl_misc(pll);
917 timeout = jiffies + msecs_to_jiffies(100);
919 val = pll_readl_misc(pll);
920 if (val & PLLE_MISC_READY)
922 if (time_after(jiffies, timeout)) {
923 pr_err("%s: timeout waiting for PLLE\n", __func__);
932 static int clk_plle_enable(struct clk_hw *hw)
934 struct tegra_clk_pll *pll = to_clk_pll(hw);
935 struct tegra_clk_pll_freq_table sel;
936 unsigned long input_rate;
940 if (clk_pll_is_enabled(hw))
943 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
945 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
950 val = pll_readl_misc(pll);
951 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
952 pll_writel_misc(val, pll);
954 val = pll_readl_misc(pll);
955 if (!(val & PLLE_MISC_READY)) {
956 err = clk_plle_training(pll);
961 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
962 /* configure dividers */
963 val = pll_readl_base(pll);
964 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
965 divm_mask_shifted(pll));
966 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
967 val |= sel.m << divm_shift(pll);
968 val |= sel.n << divn_shift(pll);
969 val |= sel.p << divp_shift(pll);
970 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
971 pll_writel_base(val, pll);
974 val = pll_readl_misc(pll);
975 val |= PLLE_MISC_SETUP_VALUE;
976 val |= PLLE_MISC_LOCK_ENABLE;
977 pll_writel_misc(val, pll);
979 val = readl(pll->clk_base + PLLE_SS_CTRL);
980 val &= ~PLLE_SS_COEFFICIENTS_MASK;
981 val |= PLLE_SS_DISABLE;
982 writel(val, pll->clk_base + PLLE_SS_CTRL);
984 val = pll_readl_base(pll);
985 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
986 pll_writel_base(val, pll);
988 clk_pll_wait_for_lock(pll);
993 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
994 unsigned long parent_rate)
996 struct tegra_clk_pll *pll = to_clk_pll(hw);
997 u32 val = pll_readl_base(pll);
998 u32 divn = 0, divm = 0, divp = 0;
999 u64 rate = parent_rate;
1001 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1002 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1003 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1011 const struct clk_ops tegra_clk_pll_ops = {
1012 .is_enabled = clk_pll_is_enabled,
1013 .enable = clk_pll_enable,
1014 .disable = clk_pll_disable,
1015 .recalc_rate = clk_pll_recalc_rate,
1016 .round_rate = clk_pll_round_rate,
1017 .set_rate = clk_pll_set_rate,
1020 const struct clk_ops tegra_clk_plle_ops = {
1021 .recalc_rate = clk_plle_recalc_rate,
1022 .is_enabled = clk_pll_is_enabled,
1023 .disable = clk_pll_disable,
1024 .enable = clk_plle_enable,
1028 * Structure defining the fields for USB UTMI clocks Parameters.
1030 struct utmi_clk_param {
1031 /* Oscillator Frequency in Hz */
1033 /* UTMIP PLL Enable Delay Count */
1034 u8 enable_delay_count;
1035 /* UTMIP PLL Stable count */
1037 /* UTMIP PLL Active delay count */
1038 u8 active_delay_count;
1039 /* UTMIP PLL Xtal frequency count */
1043 static const struct utmi_clk_param utmi_parameters[] = {
1045 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1046 .stable_count = 0x33, .active_delay_count = 0x05,
1047 .xtal_freq_count = 0x7f
1049 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1050 .stable_count = 0x4b, .active_delay_count = 0x06,
1051 .xtal_freq_count = 0xbb
1053 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1054 .stable_count = 0x2f, .active_delay_count = 0x04,
1055 .xtal_freq_count = 0x76
1057 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1058 .stable_count = 0x66, .active_delay_count = 0x09,
1059 .xtal_freq_count = 0xfe
1061 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1062 .stable_count = 0x41, .active_delay_count = 0x0a,
1063 .xtal_freq_count = 0xa4
1065 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1066 .stable_count = 0x0, .active_delay_count = 0x6,
1067 .xtal_freq_count = 0x80
1071 static int clk_pllu_enable(struct clk_hw *hw)
1073 struct tegra_clk_pll *pll = to_clk_pll(hw);
1074 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1075 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1076 const struct utmi_clk_param *params = NULL;
1077 unsigned long flags = 0, input_rate;
1083 pr_err("%s: failed to get OSC clock\n", __func__);
1087 input_rate = clk_hw_get_rate(osc);
1090 spin_lock_irqsave(pll->lock, flags);
1092 _clk_pll_enable(hw);
1094 ret = clk_pll_wait_for_lock(pll);
1098 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1099 if (input_rate == utmi_parameters[i].osc_frequency) {
1100 params = &utmi_parameters[i];
1106 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1112 value = pll_readl_base(pll);
1113 value &= ~PLLU_BASE_OVERRIDE;
1114 pll_writel_base(value, pll);
1116 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1117 /* Program UTMIP PLL stable and active counts */
1118 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1119 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1120 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1121 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1122 /* Remove power downs from UTMIP PLL control bits */
1123 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1124 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1125 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1126 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1128 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1129 /* Program UTMIP PLL delay and oscillator frequency counts */
1130 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1131 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1132 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1133 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1134 /* Remove power downs from UTMIP PLL control bits */
1135 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1136 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1137 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1138 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1142 spin_unlock_irqrestore(pll->lock, flags);
1147 static const struct clk_ops tegra_clk_pllu_ops = {
1148 .is_enabled = clk_pll_is_enabled,
1149 .enable = clk_pllu_enable,
1150 .disable = clk_pll_disable,
1151 .recalc_rate = clk_pll_recalc_rate,
1152 .round_rate = clk_pll_round_rate,
1153 .set_rate = clk_pll_set_rate,
1156 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1157 unsigned long parent_rate)
1159 u16 mdiv = parent_rate / pll_params->cf_min;
1161 if (pll_params->flags & TEGRA_MDIV_NEW)
1162 return (!pll_params->mdiv_default ? mdiv :
1163 min(mdiv, pll_params->mdiv_default));
1165 if (pll_params->mdiv_default)
1166 return pll_params->mdiv_default;
1168 if (parent_rate > pll_params->cf_max)
1174 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1175 struct tegra_clk_pll_freq_table *cfg,
1176 unsigned long rate, unsigned long parent_rate)
1178 struct tegra_clk_pll *pll = to_clk_pll(hw);
1185 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1186 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1187 cfg->output_rate = rate * p;
1188 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1189 cfg->input_rate = parent_rate;
1191 p_div = _p_div_to_hw(hw, p);
1197 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1203 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1204 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1205 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1206 defined(CONFIG_ARCH_TEGRA_210_SOC)
1208 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1210 struct tegra_clk_pll *pll = to_clk_pll(hw);
1212 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1215 static unsigned long _clip_vco_min(unsigned long vco_min,
1216 unsigned long parent_rate)
1218 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1221 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1222 void __iomem *clk_base,
1223 unsigned long parent_rate)
1228 switch (parent_rate) {
1244 pr_err("%s: Unexpected reference rate %lu\n",
1245 __func__, parent_rate);
1250 val = step_a << pll_params->stepa_shift;
1251 val |= step_b << pll_params->stepb_shift;
1252 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1257 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1258 struct tegra_clk_pll_freq_table *cfg,
1259 unsigned long rate, unsigned long parent_rate)
1261 struct tegra_clk_pll *pll = to_clk_pll(hw);
1264 err = _get_table_rate(hw, cfg, rate, parent_rate);
1266 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1268 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1275 if (cfg->p > pll->params->max_p)
1282 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1283 unsigned long parent_rate)
1285 struct tegra_clk_pll *pll = to_clk_pll(hw);
1286 struct tegra_clk_pll_freq_table cfg, old_cfg;
1287 unsigned long flags = 0;
1290 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1295 spin_lock_irqsave(pll->lock, flags);
1297 _get_pll_mnp(pll, &old_cfg);
1298 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1301 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1302 ret = _program_pll(hw, &cfg, rate);
1305 spin_unlock_irqrestore(pll->lock, flags);
1310 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1311 unsigned long *prate)
1313 struct tegra_clk_pll *pll = to_clk_pll(hw);
1314 struct tegra_clk_pll_freq_table cfg;
1316 u64 output_rate = *prate;
1318 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1322 p_div = _hw_to_p_div(hw, cfg.p);
1326 if (pll->params->set_gain)
1327 pll->params->set_gain(&cfg);
1329 output_rate *= cfg.n;
1330 do_div(output_rate, cfg.m * p_div);
1335 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1339 val = pll_readl_misc(pll);
1340 val |= PLLCX_MISC_STROBE;
1341 pll_writel_misc(val, pll);
1344 val &= ~PLLCX_MISC_STROBE;
1345 pll_writel_misc(val, pll);
1348 static int clk_pllc_enable(struct clk_hw *hw)
1350 struct tegra_clk_pll *pll = to_clk_pll(hw);
1353 unsigned long flags = 0;
1355 if (clk_pll_is_enabled(hw))
1359 spin_lock_irqsave(pll->lock, flags);
1361 _clk_pll_enable(hw);
1364 val = pll_readl_misc(pll);
1365 val &= ~PLLCX_MISC_RESET;
1366 pll_writel_misc(val, pll);
1371 ret = clk_pll_wait_for_lock(pll);
1374 spin_unlock_irqrestore(pll->lock, flags);
1379 static void _clk_pllc_disable(struct clk_hw *hw)
1381 struct tegra_clk_pll *pll = to_clk_pll(hw);
1384 _clk_pll_disable(hw);
1386 val = pll_readl_misc(pll);
1387 val |= PLLCX_MISC_RESET;
1388 pll_writel_misc(val, pll);
1392 static void clk_pllc_disable(struct clk_hw *hw)
1394 struct tegra_clk_pll *pll = to_clk_pll(hw);
1395 unsigned long flags = 0;
1398 spin_lock_irqsave(pll->lock, flags);
1400 _clk_pllc_disable(hw);
1403 spin_unlock_irqrestore(pll->lock, flags);
1406 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1407 unsigned long input_rate, u32 n)
1409 u32 val, n_threshold;
1411 switch (input_rate) {
1426 pr_err("%s: Unexpected reference rate %lu\n",
1427 __func__, input_rate);
1431 val = pll_readl_misc(pll);
1432 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1433 val |= n <= n_threshold ?
1434 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1435 pll_writel_misc(val, pll);
1440 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1441 unsigned long parent_rate)
1443 struct tegra_clk_pll_freq_table cfg, old_cfg;
1444 struct tegra_clk_pll *pll = to_clk_pll(hw);
1445 unsigned long flags = 0;
1449 spin_lock_irqsave(pll->lock, flags);
1451 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1455 _get_pll_mnp(pll, &old_cfg);
1457 if (cfg.m != old_cfg.m) {
1462 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1465 state = clk_pll_is_enabled(hw);
1467 _clk_pllc_disable(hw);
1469 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1473 _update_pll_mnp(pll, &cfg);
1476 ret = clk_pllc_enable(hw);
1480 spin_unlock_irqrestore(pll->lock, flags);
1485 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1486 struct tegra_clk_pll_freq_table *cfg,
1487 unsigned long rate, unsigned long parent_rate)
1490 u64 output_rate = parent_rate;
1492 m = _pll_fixed_mdiv(pll->params, parent_rate);
1493 n = rate * m / parent_rate;
1496 do_div(output_rate, m);
1506 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1507 unsigned long parent_rate)
1509 struct tegra_clk_pll_freq_table cfg, old_cfg;
1510 struct tegra_clk_pll *pll = to_clk_pll(hw);
1511 unsigned long flags = 0;
1515 spin_lock_irqsave(pll->lock, flags);
1517 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1518 _get_pll_mnp(pll, &old_cfg);
1521 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1522 state = clk_pll_is_enabled(hw);
1524 _clk_pll_disable(hw);
1526 _update_pll_mnp(pll, &cfg);
1529 _clk_pll_enable(hw);
1530 ret = clk_pll_wait_for_lock(pll);
1535 spin_unlock_irqrestore(pll->lock, flags);
1540 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1541 unsigned long parent_rate)
1543 struct tegra_clk_pll_freq_table cfg;
1544 struct tegra_clk_pll *pll = to_clk_pll(hw);
1545 u64 rate = parent_rate;
1547 _get_pll_mnp(pll, &cfg);
1550 do_div(rate, cfg.m);
1555 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1556 unsigned long *prate)
1558 struct tegra_clk_pll *pll = to_clk_pll(hw);
1560 return _pllre_calc_rate(pll, NULL, rate, *prate);
1563 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1565 struct tegra_clk_pll *pll = to_clk_pll(hw);
1566 struct tegra_clk_pll_freq_table sel;
1569 unsigned long flags = 0;
1570 unsigned long input_rate;
1572 if (clk_pll_is_enabled(hw))
1575 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1577 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1581 spin_lock_irqsave(pll->lock, flags);
1583 val = pll_readl_base(pll);
1584 val &= ~BIT(29); /* Disable lock override */
1585 pll_writel_base(val, pll);
1587 val = pll_readl(pll->params->aux_reg, pll);
1588 val |= PLLE_AUX_ENABLE_SWCTL;
1589 val &= ~PLLE_AUX_SEQ_ENABLE;
1590 pll_writel(val, pll->params->aux_reg, pll);
1593 val = pll_readl_misc(pll);
1594 val |= PLLE_MISC_LOCK_ENABLE;
1595 val |= PLLE_MISC_IDDQ_SW_CTRL;
1596 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1597 val |= PLLE_MISC_PLLE_PTS;
1598 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1599 pll_writel_misc(val, pll);
1602 val = pll_readl(PLLE_SS_CTRL, pll);
1603 val |= PLLE_SS_DISABLE;
1604 pll_writel(val, PLLE_SS_CTRL, pll);
1606 val = pll_readl_base(pll);
1607 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1608 divm_mask_shifted(pll));
1609 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1610 val |= sel.m << divm_shift(pll);
1611 val |= sel.n << divn_shift(pll);
1612 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1613 pll_writel_base(val, pll);
1616 _clk_pll_enable(hw);
1617 ret = clk_pll_wait_for_lock(pll);
1622 val = pll_readl(PLLE_SS_CTRL, pll);
1623 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1624 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1625 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1626 pll_writel(val, PLLE_SS_CTRL, pll);
1627 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1628 pll_writel(val, PLLE_SS_CTRL, pll);
1630 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1631 pll_writel(val, PLLE_SS_CTRL, pll);
1634 /* Enable hw control of xusb brick pll */
1635 val = pll_readl_misc(pll);
1636 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1637 pll_writel_misc(val, pll);
1639 val = pll_readl(pll->params->aux_reg, pll);
1640 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1641 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1642 pll_writel(val, pll->params->aux_reg, pll);
1644 val |= PLLE_AUX_SEQ_ENABLE;
1645 pll_writel(val, pll->params->aux_reg, pll);
1647 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1648 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1649 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1650 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1651 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1652 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1654 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1655 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1657 /* Enable hw control of SATA pll */
1658 val = pll_readl(SATA_PLL_CFG0, pll);
1659 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1660 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1661 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1662 pll_writel(val, SATA_PLL_CFG0, pll);
1666 val = pll_readl(SATA_PLL_CFG0, pll);
1667 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1668 pll_writel(val, SATA_PLL_CFG0, pll);
1672 spin_unlock_irqrestore(pll->lock, flags);
1677 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1679 struct tegra_clk_pll *pll = to_clk_pll(hw);
1680 unsigned long flags = 0;
1684 spin_lock_irqsave(pll->lock, flags);
1686 _clk_pll_disable(hw);
1688 val = pll_readl_misc(pll);
1689 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1690 pll_writel_misc(val, pll);
1694 spin_unlock_irqrestore(pll->lock, flags);
1697 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1699 struct tegra_clk_pll *pll = to_clk_pll(hw);
1700 const struct utmi_clk_param *params = NULL;
1701 struct clk *osc = __clk_lookup("osc");
1702 unsigned long flags = 0, input_rate;
1708 pr_err("%s: failed to get OSC clock\n", __func__);
1712 if (clk_pll_is_enabled(hw))
1715 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1718 spin_lock_irqsave(pll->lock, flags);
1720 _clk_pll_enable(hw);
1722 ret = clk_pll_wait_for_lock(pll);
1726 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1727 if (input_rate == utmi_parameters[i].osc_frequency) {
1728 params = &utmi_parameters[i];
1734 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1740 value = pll_readl_base(pll);
1741 value &= ~PLLU_BASE_OVERRIDE;
1742 pll_writel_base(value, pll);
1744 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1745 /* Program UTMIP PLL stable and active counts */
1746 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1747 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1748 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1749 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1750 /* Remove power downs from UTMIP PLL control bits */
1751 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1752 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1753 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1754 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1756 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1757 /* Program UTMIP PLL delay and oscillator frequency counts */
1758 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1759 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1760 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1761 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1762 /* Remove power downs from UTMIP PLL control bits */
1763 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1764 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1765 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1766 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1767 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1769 /* Setup HW control of UTMIPLL */
1770 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1771 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1772 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1773 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1774 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1776 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1777 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1778 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1779 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1784 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1787 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1788 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1789 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1790 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1794 /* Enable HW control of UTMIPLL */
1795 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1796 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1797 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1801 spin_unlock_irqrestore(pll->lock, flags);
1807 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1808 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1811 struct tegra_clk_pll *pll;
1813 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1815 return ERR_PTR(-ENOMEM);
1817 pll->clk_base = clk_base;
1820 pll->params = pll_params;
1823 if (!pll_params->div_nmp)
1824 pll_params->div_nmp = &default_nmp;
1829 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1830 const char *name, const char *parent_name, unsigned long flags,
1831 const struct clk_ops *ops)
1833 struct clk_init_data init;
1838 init.parent_names = (parent_name ? &parent_name : NULL);
1839 init.num_parents = (parent_name ? 1 : 0);
1841 /* Default to _calc_rate if unspecified */
1842 if (!pll->params->calc_rate) {
1843 if (pll->params->flags & TEGRA_PLLM)
1844 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1846 pll->params->calc_rate = _calc_rate;
1849 if (pll->params->set_defaults)
1850 pll->params->set_defaults(pll);
1852 /* Data in .init is copied by clk_register(), so stack variable OK */
1853 pll->hw.init = &init;
1855 return clk_register(NULL, &pll->hw);
1858 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1859 void __iomem *clk_base, void __iomem *pmc,
1860 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1863 struct tegra_clk_pll *pll;
1866 pll_params->flags |= TEGRA_PLL_BYPASS;
1868 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1870 return ERR_CAST(pll);
1872 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1873 &tegra_clk_pll_ops);
1880 static struct div_nmp pll_e_nmp = {
1881 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1882 .divn_width = PLLE_BASE_DIVN_WIDTH,
1883 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1884 .divm_width = PLLE_BASE_DIVM_WIDTH,
1885 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1886 .divp_width = PLLE_BASE_DIVP_WIDTH,
1889 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1890 void __iomem *clk_base, void __iomem *pmc,
1891 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1894 struct tegra_clk_pll *pll;
1897 pll_params->flags |= TEGRA_PLL_BYPASS;
1899 if (!pll_params->div_nmp)
1900 pll_params->div_nmp = &pll_e_nmp;
1902 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1904 return ERR_CAST(pll);
1906 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1907 &tegra_clk_plle_ops);
1914 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1915 void __iomem *clk_base, unsigned long flags,
1916 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1918 struct tegra_clk_pll *pll;
1921 pll_params->flags |= TEGRA_PLLU;
1923 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1925 return ERR_CAST(pll);
1927 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1928 &tegra_clk_pllu_ops);
1935 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1936 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1937 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1938 defined(CONFIG_ARCH_TEGRA_210_SOC)
1939 static const struct clk_ops tegra_clk_pllxc_ops = {
1940 .is_enabled = clk_pll_is_enabled,
1941 .enable = clk_pll_enable,
1942 .disable = clk_pll_disable,
1943 .recalc_rate = clk_pll_recalc_rate,
1944 .round_rate = clk_pll_ramp_round_rate,
1945 .set_rate = clk_pllxc_set_rate,
1948 static const struct clk_ops tegra_clk_pllc_ops = {
1949 .is_enabled = clk_pll_is_enabled,
1950 .enable = clk_pllc_enable,
1951 .disable = clk_pllc_disable,
1952 .recalc_rate = clk_pll_recalc_rate,
1953 .round_rate = clk_pll_ramp_round_rate,
1954 .set_rate = clk_pllc_set_rate,
1957 static const struct clk_ops tegra_clk_pllre_ops = {
1958 .is_enabled = clk_pll_is_enabled,
1959 .enable = clk_pll_enable,
1960 .disable = clk_pll_disable,
1961 .recalc_rate = clk_pllre_recalc_rate,
1962 .round_rate = clk_pllre_round_rate,
1963 .set_rate = clk_pllre_set_rate,
1966 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1967 .is_enabled = clk_pll_is_enabled,
1968 .enable = clk_plle_tegra114_enable,
1969 .disable = clk_plle_tegra114_disable,
1970 .recalc_rate = clk_pll_recalc_rate,
1973 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1974 .is_enabled = clk_pll_is_enabled,
1975 .enable = clk_pllu_tegra114_enable,
1976 .disable = clk_pll_disable,
1977 .recalc_rate = clk_pll_recalc_rate,
1980 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1981 void __iomem *clk_base, void __iomem *pmc,
1982 unsigned long flags,
1983 struct tegra_clk_pll_params *pll_params,
1986 struct tegra_clk_pll *pll;
1987 struct clk *clk, *parent;
1988 unsigned long parent_rate;
1991 parent = __clk_lookup(parent_name);
1993 WARN(1, "parent clk %s of %s must be registered first\n",
1995 return ERR_PTR(-EINVAL);
1998 if (!pll_params->pdiv_tohw)
1999 return ERR_PTR(-EINVAL);
2001 parent_rate = clk_get_rate(parent);
2003 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2005 if (pll_params->adjust_vco)
2006 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2010 * If the pll has a set_defaults callback, it will take care of
2011 * configuring dynamic ramping and setting IDDQ in that path.
2013 if (!pll_params->set_defaults) {
2016 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2018 return ERR_PTR(err);
2020 val = readl_relaxed(clk_base + pll_params->base_reg);
2021 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2023 if (val & PLL_BASE_ENABLE)
2024 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2026 val_iddq |= BIT(pll_params->iddq_bit_idx);
2027 writel_relaxed(val_iddq,
2028 clk_base + pll_params->iddq_reg);
2032 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2034 return ERR_CAST(pll);
2036 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2037 &tegra_clk_pllxc_ops);
2044 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2045 void __iomem *clk_base, void __iomem *pmc,
2046 unsigned long flags,
2047 struct tegra_clk_pll_params *pll_params,
2048 spinlock_t *lock, unsigned long parent_rate)
2051 struct tegra_clk_pll *pll;
2054 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2056 if (pll_params->adjust_vco)
2057 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2060 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2062 return ERR_CAST(pll);
2064 /* program minimum rate by default */
2066 val = pll_readl_base(pll);
2067 if (val & PLL_BASE_ENABLE)
2068 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2069 BIT(pll_params->iddq_bit_idx));
2073 m = _pll_fixed_mdiv(pll_params, parent_rate);
2074 val = m << divm_shift(pll);
2075 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2076 pll_writel_base(val, pll);
2079 /* disable lock override */
2081 val = pll_readl_misc(pll);
2083 pll_writel_misc(val, pll);
2085 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2086 &tegra_clk_pllre_ops);
2093 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2094 void __iomem *clk_base, void __iomem *pmc,
2095 unsigned long flags,
2096 struct tegra_clk_pll_params *pll_params,
2099 struct tegra_clk_pll *pll;
2100 struct clk *clk, *parent;
2101 unsigned long parent_rate;
2103 if (!pll_params->pdiv_tohw)
2104 return ERR_PTR(-EINVAL);
2106 parent = __clk_lookup(parent_name);
2108 WARN(1, "parent clk %s of %s must be registered first\n",
2110 return ERR_PTR(-EINVAL);
2113 parent_rate = clk_get_rate(parent);
2115 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2117 if (pll_params->adjust_vco)
2118 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2121 pll_params->flags |= TEGRA_PLL_BYPASS;
2122 pll_params->flags |= TEGRA_PLLM;
2123 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2125 return ERR_CAST(pll);
2127 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2128 &tegra_clk_pll_ops);
2135 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2136 void __iomem *clk_base, void __iomem *pmc,
2137 unsigned long flags,
2138 struct tegra_clk_pll_params *pll_params,
2141 struct clk *parent, *clk;
2142 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2143 struct tegra_clk_pll *pll;
2144 struct tegra_clk_pll_freq_table cfg;
2145 unsigned long parent_rate;
2148 return ERR_PTR(-EINVAL);
2150 parent = __clk_lookup(parent_name);
2152 WARN(1, "parent clk %s of %s must be registered first\n",
2154 return ERR_PTR(-EINVAL);
2157 parent_rate = clk_get_rate(parent);
2159 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2161 pll_params->flags |= TEGRA_PLL_BYPASS;
2162 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2164 return ERR_CAST(pll);
2167 * Most of PLLC register fields are shadowed, and can not be read
2168 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2169 * Initialize PLL to default state: disabled, reset; shadow registers
2170 * loaded with default parameters; dividers are preset for half of
2171 * minimum VCO rate (the latter assured that shadowed divider settings
2172 * are within supported range).
2175 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2176 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2178 while (p_tohw->pdiv) {
2179 if (p_tohw->pdiv == 2) {
2180 cfg.p = p_tohw->hw_val;
2186 if (!p_tohw->pdiv) {
2188 return ERR_PTR(-EINVAL);
2191 pll_writel_base(0, pll);
2192 _update_pll_mnp(pll, &cfg);
2194 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2195 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2196 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2197 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2199 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2201 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2202 &tegra_clk_pllc_ops);
2209 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2210 const char *parent_name,
2211 void __iomem *clk_base, unsigned long flags,
2212 struct tegra_clk_pll_params *pll_params,
2215 struct tegra_clk_pll *pll;
2219 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2221 return ERR_CAST(pll);
2223 /* ensure parent is set to pll_re_vco */
2225 val = pll_readl_base(pll);
2226 val_aux = pll_readl(pll_params->aux_reg, pll);
2228 if (val & PLL_BASE_ENABLE) {
2229 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2230 (val_aux & PLLE_AUX_PLLP_SEL))
2231 WARN(1, "pll_e enabled with unsupported parent %s\n",
2232 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2235 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2236 pll_writel(val_aux, pll_params->aux_reg, pll);
2239 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2240 &tegra_clk_plle_tegra114_ops);
2248 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2249 void __iomem *clk_base, unsigned long flags,
2250 struct tegra_clk_pll_params *pll_params,
2253 struct tegra_clk_pll *pll;
2256 pll_params->flags |= TEGRA_PLLU;
2258 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2260 return ERR_CAST(pll);
2262 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2263 &tegra_clk_pllu_tegra114_ops);
2271 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2272 static const struct clk_ops tegra_clk_pllss_ops = {
2273 .is_enabled = clk_pll_is_enabled,
2274 .enable = clk_pll_enable,
2275 .disable = clk_pll_disable,
2276 .recalc_rate = clk_pll_recalc_rate,
2277 .round_rate = clk_pll_ramp_round_rate,
2278 .set_rate = clk_pllxc_set_rate,
2281 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2282 void __iomem *clk_base, unsigned long flags,
2283 struct tegra_clk_pll_params *pll_params,
2286 struct tegra_clk_pll *pll;
2287 struct clk *clk, *parent;
2288 struct tegra_clk_pll_freq_table cfg;
2289 unsigned long parent_rate;
2293 if (!pll_params->div_nmp)
2294 return ERR_PTR(-EINVAL);
2296 parent = __clk_lookup(parent_name);
2298 WARN(1, "parent clk %s of %s must be registered first\n",
2300 return ERR_PTR(-EINVAL);
2303 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2305 return ERR_CAST(pll);
2307 val = pll_readl_base(pll);
2308 val &= ~PLLSS_REF_SRC_SEL_MASK;
2309 pll_writel_base(val, pll);
2311 parent_rate = clk_get_rate(parent);
2313 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2315 /* initialize PLL to minimum rate */
2317 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2318 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2320 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2324 return ERR_PTR(-EINVAL);
2327 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2329 _update_pll_mnp(pll, &cfg);
2331 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2332 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2333 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2334 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2336 val = pll_readl_base(pll);
2337 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2338 if (val & PLL_BASE_ENABLE) {
2339 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2340 WARN(1, "%s is on but IDDQ set\n", name);
2342 return ERR_PTR(-EINVAL);
2345 val_iddq |= BIT(pll_params->iddq_bit_idx);
2346 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2349 val &= ~PLLSS_LOCK_OVERRIDE;
2350 pll_writel_base(val, pll);
2352 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2353 &tegra_clk_pllss_ops);
2362 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2363 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2364 const char *parent_name, void __iomem *clk_base,
2365 void __iomem *pmc, unsigned long flags,
2366 struct tegra_clk_pll_params *pll_params,
2367 spinlock_t *lock, unsigned long parent_rate)
2369 struct tegra_clk_pll *pll;
2372 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2374 if (pll_params->adjust_vco)
2375 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2378 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2380 return ERR_CAST(pll);
2382 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2383 &tegra_clk_pll_ops);
2390 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2392 struct tegra_clk_pll *pll = to_clk_pll(hw);
2395 val = pll_readl_base(pll);
2397 return val & PLLE_BASE_ENABLE ? 1 : 0;
2400 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2402 struct tegra_clk_pll *pll = to_clk_pll(hw);
2403 struct tegra_clk_pll_freq_table sel;
2406 unsigned long flags = 0;
2407 unsigned long input_rate;
2409 if (clk_plle_tegra210_is_enabled(hw))
2412 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2414 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2418 spin_lock_irqsave(pll->lock, flags);
2420 val = pll_readl(pll->params->aux_reg, pll);
2421 if (val & PLLE_AUX_SEQ_ENABLE)
2424 val = pll_readl_base(pll);
2425 val &= ~BIT(30); /* Disable lock override */
2426 pll_writel_base(val, pll);
2428 val = pll_readl_misc(pll);
2429 val |= PLLE_MISC_LOCK_ENABLE;
2430 val |= PLLE_MISC_IDDQ_SW_CTRL;
2431 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2432 val |= PLLE_MISC_PLLE_PTS;
2433 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2434 pll_writel_misc(val, pll);
2437 val = pll_readl(PLLE_SS_CTRL, pll);
2438 val |= PLLE_SS_DISABLE;
2439 pll_writel(val, PLLE_SS_CTRL, pll);
2441 val = pll_readl_base(pll);
2442 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2443 divm_mask_shifted(pll));
2444 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2445 val |= sel.m << divm_shift(pll);
2446 val |= sel.n << divn_shift(pll);
2447 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2448 pll_writel_base(val, pll);
2451 val = pll_readl_base(pll);
2452 val |= PLLE_BASE_ENABLE;
2453 pll_writel_base(val, pll);
2455 ret = clk_pll_wait_for_lock(pll);
2460 val = pll_readl(PLLE_SS_CTRL, pll);
2461 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2462 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2463 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2464 pll_writel(val, PLLE_SS_CTRL, pll);
2465 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2466 pll_writel(val, PLLE_SS_CTRL, pll);
2468 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2469 pll_writel(val, PLLE_SS_CTRL, pll);
2472 val = pll_readl_misc(pll);
2473 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2474 pll_writel_misc(val, pll);
2476 val = pll_readl(pll->params->aux_reg, pll);
2477 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2478 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2479 pll_writel(val, pll->params->aux_reg, pll);
2481 val |= PLLE_AUX_SEQ_ENABLE;
2482 pll_writel(val, pll->params->aux_reg, pll);
2486 spin_unlock_irqrestore(pll->lock, flags);
2491 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2493 struct tegra_clk_pll *pll = to_clk_pll(hw);
2494 unsigned long flags = 0;
2498 spin_lock_irqsave(pll->lock, flags);
2500 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2501 val = pll_readl(pll->params->aux_reg, pll);
2502 if (val & PLLE_AUX_SEQ_ENABLE)
2505 val = pll_readl_base(pll);
2506 val &= ~PLLE_BASE_ENABLE;
2507 pll_writel_base(val, pll);
2509 val = pll_readl(pll->params->aux_reg, pll);
2510 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2511 pll_writel(val, pll->params->aux_reg, pll);
2513 val = pll_readl_misc(pll);
2514 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2515 pll_writel_misc(val, pll);
2520 spin_unlock_irqrestore(pll->lock, flags);
2523 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2524 .is_enabled = clk_plle_tegra210_is_enabled,
2525 .enable = clk_plle_tegra210_enable,
2526 .disable = clk_plle_tegra210_disable,
2527 .recalc_rate = clk_pll_recalc_rate,
2530 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2531 const char *parent_name,
2532 void __iomem *clk_base, unsigned long flags,
2533 struct tegra_clk_pll_params *pll_params,
2536 struct tegra_clk_pll *pll;
2540 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2542 return ERR_CAST(pll);
2544 /* ensure parent is set to pll_re_vco */
2546 val = pll_readl_base(pll);
2547 val_aux = pll_readl(pll_params->aux_reg, pll);
2549 if (val & PLLE_BASE_ENABLE) {
2550 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2551 (val_aux & PLLE_AUX_PLLP_SEL))
2552 WARN(1, "pll_e enabled with unsupported parent %s\n",
2553 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2556 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2557 pll_writel(val_aux, pll_params->aux_reg, pll);
2560 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2561 &tegra_clk_plle_tegra210_ops);
2568 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2569 const char *parent_name, void __iomem *clk_base,
2570 void __iomem *pmc, unsigned long flags,
2571 struct tegra_clk_pll_params *pll_params,
2574 struct clk *parent, *clk;
2575 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2576 struct tegra_clk_pll *pll;
2577 unsigned long parent_rate;
2580 return ERR_PTR(-EINVAL);
2582 parent = __clk_lookup(parent_name);
2584 WARN(1, "parent clk %s of %s must be registered first\n",
2586 return ERR_PTR(-EINVAL);
2589 parent_rate = clk_get_rate(parent);
2591 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2593 if (pll_params->adjust_vco)
2594 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2597 pll_params->flags |= TEGRA_PLL_BYPASS;
2598 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2600 return ERR_CAST(pll);
2602 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2603 &tegra_clk_pll_ops);
2610 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2611 const char *parent_name, void __iomem *clk_base,
2612 unsigned long flags,
2613 struct tegra_clk_pll_params *pll_params,
2616 struct tegra_clk_pll *pll;
2617 struct clk *clk, *parent;
2618 unsigned long parent_rate;
2621 if (!pll_params->div_nmp)
2622 return ERR_PTR(-EINVAL);
2624 parent = __clk_lookup(parent_name);
2626 WARN(1, "parent clk %s of %s must be registered first\n",
2628 return ERR_PTR(-EINVAL);
2631 val = readl_relaxed(clk_base + pll_params->base_reg);
2632 if (val & PLLSS_REF_SRC_SEL_MASK) {
2633 WARN(1, "not supported reference clock for %s\n", name);
2634 return ERR_PTR(-EINVAL);
2637 parent_rate = clk_get_rate(parent);
2639 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2641 if (pll_params->adjust_vco)
2642 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2645 pll_params->flags |= TEGRA_PLL_BYPASS;
2646 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2648 return ERR_CAST(pll);
2650 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2651 &tegra_clk_pll_ops);
2659 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2660 void __iomem *clk_base, void __iomem *pmc,
2661 unsigned long flags,
2662 struct tegra_clk_pll_params *pll_params,
2665 struct tegra_clk_pll *pll;
2666 struct clk *clk, *parent;
2667 unsigned long parent_rate;
2669 if (!pll_params->pdiv_tohw)
2670 return ERR_PTR(-EINVAL);
2672 parent = __clk_lookup(parent_name);
2674 WARN(1, "parent clk %s of %s must be registered first\n",
2676 return ERR_PTR(-EINVAL);
2679 parent_rate = clk_get_rate(parent);
2681 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2683 if (pll_params->adjust_vco)
2684 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2687 pll_params->flags |= TEGRA_PLL_BYPASS;
2688 pll_params->flags |= TEGRA_PLLMB;
2689 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2691 return ERR_CAST(pll);
2693 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2694 &tegra_clk_pll_ops);