drivers/clk/tegra/clk-pll.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/slab.h>
   7 #include <linux/io.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12
  13 #include "clk.h"
  14
  15 #define PLL_BASE_BYPASS BIT(31)
  16 #define PLL_BASE_ENABLE BIT(30)
  17 #define PLL_BASE_REF_ENABLE BIT(29)
  18 #define PLL_BASE_OVERRIDE BIT(28)
  19
  20 #define PLL_BASE_DIVP_SHIFT 20
  21 #define PLL_BASE_DIVP_WIDTH 3
  22 #define PLL_BASE_DIVN_SHIFT 8
  23 #define PLL_BASE_DIVN_WIDTH 10
  24 #define PLL_BASE_DIVM_SHIFT 0
  25 #define PLL_BASE_DIVM_WIDTH 5
  26 #define PLLU_POST_DIVP_MASK 0x1
  27
  28 #define PLL_MISC_DCCON_SHIFT 20
  29 #define PLL_MISC_CPCON_SHIFT 8
  30 #define PLL_MISC_CPCON_WIDTH 4
  31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  32 #define PLL_MISC_LFCON_SHIFT 4
  33 #define PLL_MISC_LFCON_WIDTH 4
  34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  35 #define PLL_MISC_VCOCON_SHIFT 0
  36 #define PLL_MISC_VCOCON_WIDTH 4
  37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  38
  39 #define OUT_OF_TABLE_CPCON 8
  40
  41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  42 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  43 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  44
  45 #define PLL_POST_LOCK_DELAY 50
  46
  47 #define PLLDU_LFCON_SET_DIVN 600
  48
  49 #define PLLE_BASE_DIVCML_SHIFT 24
  50 #define PLLE_BASE_DIVCML_MASK 0xf
  51 #define PLLE_BASE_DIVP_SHIFT 16
  52 #define PLLE_BASE_DIVP_WIDTH 6
  53 #define PLLE_BASE_DIVN_SHIFT 8
  54 #define PLLE_BASE_DIVN_WIDTH 8
  55 #define PLLE_BASE_DIVM_SHIFT 0
  56 #define PLLE_BASE_DIVM_WIDTH 8
  57 #define PLLE_BASE_ENABLE BIT(31)
  58
  59 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  60 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  61 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  62 #define PLLE_MISC_READY BIT(15)
  63 #define PLLE_MISC_SETUP_EX_SHIFT 2
  64 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  65 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  66                               PLLE_MISC_SETUP_EX_MASK)
  67 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  68
  69 #define PLLE_SS_CTRL 0x68
  70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  71 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  72 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  73 #define PLLE_SS_CNTL_CENTER BIT(14)
  74 #define PLLE_SS_CNTL_INVERT BIT(15)
  75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  76                                 PLLE_SS_CNTL_SSC_BYP)
  77 #define PLLE_SS_MAX_MASK 0x1ff
  78 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  79 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  80 #define PLLE_SS_INC_MASK (0xff << 16)
  81 #define PLLE_SS_INC_VAL (0x1 << 16)
  82 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  83 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  84 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  85 #define PLLE_SS_COEFFICIENTS_MASK \
  86         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  87 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  88         (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
  89          PLLE_SS_INCINTRV_VAL_TEGRA114)
  90 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
  91         (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
  92          PLLE_SS_INCINTRV_VAL_TEGRA210)
  93
  94 #define PLLE_AUX_PLLP_SEL       BIT(2)
  95 #define PLLE_AUX_USE_LOCKDET    BIT(3)
  96 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
  97 #define PLLE_AUX_SS_SWCTL       BIT(6)
  98 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
  99 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 100 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 101 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 102
 103 #define XUSBIO_PLL_CFG0         0x51c
 104 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 105 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 106 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 107 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 108 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 109
 110 #define SATA_PLL_CFG0           0x490
 111 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 112 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 113 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 114 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 115
 116 #define PLLE_MISC_PLLE_PTS      BIT(8)
 117 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 118 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 119 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 120 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 121 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 122 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 123
 124 #define PLLCX_MISC_STROBE       BIT(31)
 125 #define PLLCX_MISC_RESET        BIT(30)
 126 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 127 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 128 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 129 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 130 #define PLLCX_MISC_ALPHA_SHIFT 18
 131 #define PLLCX_MISC_DIV_LOW_RANGE \
 132                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 133                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 134 #define PLLCX_MISC_DIV_HIGH_RANGE \
 135                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 136                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 137 #define PLLCX_MISC_COEF_LOW_RANGE \
 138                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 139 #define PLLCX_MISC_KA_SHIFT 2
 140 #define PLLCX_MISC_KB_SHIFT 9
 141 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 142                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 143                             PLLCX_MISC_DIV_LOW_RANGE | \
 144                             PLLCX_MISC_RESET)
 145 #define PLLCX_MISC1_DEFAULT 0x000d2308
 146 #define PLLCX_MISC2_DEFAULT 0x30211200
 147 #define PLLCX_MISC3_DEFAULT 0x200
 148
 149 #define PMC_SATA_PWRGT 0x1ac
 150 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 151 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 152
 153 #define PLLSS_MISC_KCP          0
 154 #define PLLSS_MISC_KVCO         0
 155 #define PLLSS_MISC_SETUP        0
 156 #define PLLSS_EN_SDM            0
 157 #define PLLSS_EN_SSC            0
 158 #define PLLSS_EN_DITHER2        0
 159 #define PLLSS_EN_DITHER         1
 160 #define PLLSS_SDM_RESET         0
 161 #define PLLSS_CLAMP             0
 162 #define PLLSS_SDM_SSC_MAX       0
 163 #define PLLSS_SDM_SSC_MIN       0
 164 #define PLLSS_SDM_SSC_STEP      0
 165 #define PLLSS_SDM_DIN           0
 166 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 167                             (PLLSS_MISC_KVCO << 24) | \
 168                             PLLSS_MISC_SETUP)
 169 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 170                            (PLLSS_EN_SSC << 30) | \
 171                            (PLLSS_EN_DITHER2 << 29) | \
 172                            (PLLSS_EN_DITHER << 28) | \
 173                            (PLLSS_SDM_RESET) << 27 | \
 174                            (PLLSS_CLAMP << 22))
 175 #define PLLSS_CTRL1_DEFAULT \
 176                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 177 #define PLLSS_CTRL2_DEFAULT \
 178                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 179 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 180 #define PLLSS_REF_SRC_SEL_SHIFT 25
 181 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 182
 183 #define UTMIP_PLL_CFG1 0x484
 184 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 185 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 186 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 187 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 188 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 189 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 190 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 191
 192 #define UTMIP_PLL_CFG2 0x488
 193 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 194 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 195 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 197 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 198 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 199 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 200 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 201 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 202 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 203 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 204
 205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
 206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 208 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 210 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 211 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 213 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 214
 215 #define PLLU_HW_PWRDN_CFG0 0x530
 216 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 217 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 218 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 219 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 220 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 221 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 222
 223 #define XUSB_PLL_CFG0 0x534
 224 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 225 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 226
 227 #define PLLU_BASE_CLKENABLE_USB BIT(21)
 228 #define PLLU_BASE_OVERRIDE BIT(24)
 229
 230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 236
 237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 243
 244 #define mask(w) ((1 << (w)) - 1)
 245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 248                       mask(p->params->div_nmp->divp_width))
 249 #define sdm_din_mask(p) p->params->sdm_din_mask
 250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 251
 252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 255
 256 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 259
 260 #define divm_max(p) (divm_mask(p))
 261 #define divn_max(p) (divn_mask(p))
 262 #define divp_max(p) (1 << (divp_mask(p)))
 263
 264 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 265 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 266
 267 static struct div_nmp default_nmp = {
 268         .divn_shift = PLL_BASE_DIVN_SHIFT,
 269         .divn_width = PLL_BASE_DIVN_WIDTH,
 270         .divm_shift = PLL_BASE_DIVM_SHIFT,
 271         .divm_width = PLL_BASE_DIVM_WIDTH,
 272         .divp_shift = PLL_BASE_DIVP_SHIFT,
 273         .divp_width = PLL_BASE_DIVP_WIDTH,
 274 };
 275
 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 277 {
 278         u32 val;
 279
 280         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 281                 return;
 282
 283         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 284                 return;
 285
 286         val = pll_readl_misc(pll);
 287         val |= BIT(pll->params->lock_enable_bit_idx);
 288         pll_writel_misc(val, pll);
 289 }
 290
 291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 292 {
 293         int i;
 294         u32 val, lock_mask;
 295         void __iomem *lock_addr;
 296
 297         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 298                 udelay(pll->params->lock_delay);
 299                 return 0;
 300         }
 301
 302         lock_addr = pll->clk_base;
 303         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 304                 lock_addr += pll->params->misc_reg;
 305         else
 306                 lock_addr += pll->params->base_reg;
 307
 308         lock_mask = pll->params->lock_mask;
 309
 310         for (i = 0; i < pll->params->lock_delay; i++) {
 311                 val = readl_relaxed(lock_addr);
 312                 if ((val & lock_mask) == lock_mask) {
 313                         udelay(PLL_POST_LOCK_DELAY);
 314                         return 0;
 315                 }
 316                 udelay(2); /* timeout = 2 * lock time */
 317         }
 318
 319         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 320                clk_hw_get_name(&pll->hw));
 321
 322         return -1;
 323 }
 324
 325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 326 {
 327         return clk_pll_wait_for_lock(pll);
 328 }
 329
 330 static int clk_pll_is_enabled(struct clk_hw *hw)
 331 {
 332         struct tegra_clk_pll *pll = to_clk_pll(hw);
 333         u32 val;
 334
 335         if (pll->params->flags & TEGRA_PLLM) {
 336                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 337                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 338                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 339         }
 340
 341         val = pll_readl_base(pll);
 342
 343         return val & PLL_BASE_ENABLE ? 1 : 0;
 344 }
 345
 346 static void _clk_pll_enable(struct clk_hw *hw)
 347 {
 348         struct tegra_clk_pll *pll = to_clk_pll(hw);
 349         u32 val;
 350
 351         if (pll->params->iddq_reg) {
 352                 val = pll_readl(pll->params->iddq_reg, pll);
 353                 val &= ~BIT(pll->params->iddq_bit_idx);
 354                 pll_writel(val, pll->params->iddq_reg, pll);
 355                 udelay(5);
 356         }
 357
 358         if (pll->params->reset_reg) {
 359                 val = pll_readl(pll->params->reset_reg, pll);
 360                 val &= ~BIT(pll->params->reset_bit_idx);
 361                 pll_writel(val, pll->params->reset_reg, pll);
 362         }
 363
 364         clk_pll_enable_lock(pll);
 365
 366         val = pll_readl_base(pll);
 367         if (pll->params->flags & TEGRA_PLL_BYPASS)
 368                 val &= ~PLL_BASE_BYPASS;
 369         val |= PLL_BASE_ENABLE;
 370         pll_writel_base(val, pll);
 371
 372         if (pll->params->flags & TEGRA_PLLM) {
 373                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 374                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 375                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 376         }
 377 }
 378
 379 static void _clk_pll_disable(struct clk_hw *hw)
 380 {
 381         struct tegra_clk_pll *pll = to_clk_pll(hw);
 382         u32 val;
 383
 384         val = pll_readl_base(pll);
 385         if (pll->params->flags & TEGRA_PLL_BYPASS)
 386                 val &= ~PLL_BASE_BYPASS;
 387         val &= ~PLL_BASE_ENABLE;
 388         pll_writel_base(val, pll);
 389
 390         if (pll->params->flags & TEGRA_PLLM) {
 391                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 392                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 393                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 394         }
 395
 396         if (pll->params->reset_reg) {
 397                 val = pll_readl(pll->params->reset_reg, pll);
 398                 val |= BIT(pll->params->reset_bit_idx);
 399                 pll_writel(val, pll->params->reset_reg, pll);
 400         }
 401
 402         if (pll->params->iddq_reg) {
 403                 val = pll_readl(pll->params->iddq_reg, pll);
 404                 val |= BIT(pll->params->iddq_bit_idx);
 405                 pll_writel(val, pll->params->iddq_reg, pll);
 406                 udelay(2);
 407         }
 408 }
 409
 410 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 411 {
 412         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 413                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 414
 415                 val |= pll->params->ssc_ctrl_en_mask;
 416                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 417         }
 418 }
 419
 420 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 421 {
 422         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 423                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 424
 425                 val &= ~pll->params->ssc_ctrl_en_mask;
 426                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 427         }
 428 }
 429
 430 static int clk_pll_enable(struct clk_hw *hw)
 431 {
 432         struct tegra_clk_pll *pll = to_clk_pll(hw);
 433         unsigned long flags = 0;
 434         int ret;
 435
 436         if (clk_pll_is_enabled(hw))
 437                 return 0;
 438
 439         if (pll->lock)
 440                 spin_lock_irqsave(pll->lock, flags);
 441
 442         _clk_pll_enable(hw);
 443
 444         ret = clk_pll_wait_for_lock(pll);
 445
 446         pll_clk_start_ss(pll);
 447
 448         if (pll->lock)
 449                 spin_unlock_irqrestore(pll->lock, flags);
 450
 451         return ret;
 452 }
 453
 454 static void clk_pll_disable(struct clk_hw *hw)
 455 {
 456         struct tegra_clk_pll *pll = to_clk_pll(hw);
 457         unsigned long flags = 0;
 458
 459         if (pll->lock)
 460                 spin_lock_irqsave(pll->lock, flags);
 461
 462         pll_clk_stop_ss(pll);
 463
 464         _clk_pll_disable(hw);
 465
 466         if (pll->lock)
 467                 spin_unlock_irqrestore(pll->lock, flags);
 468 }
 469
 470 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 471 {
 472         struct tegra_clk_pll *pll = to_clk_pll(hw);
 473         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 474
 475         if (p_tohw) {
 476                 while (p_tohw->pdiv) {
 477                         if (p_div <= p_tohw->pdiv)
 478                                 return p_tohw->hw_val;
 479                         p_tohw++;
 480                 }
 481                 return -EINVAL;
 482         }
 483         return -EINVAL;
 484 }
 485
 486 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 487 {
 488         return _p_div_to_hw(&pll->hw, p_div);
 489 }
 490
 491 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 492 {
 493         struct tegra_clk_pll *pll = to_clk_pll(hw);
 494         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 495
 496         if (p_tohw) {
 497                 while (p_tohw->pdiv) {
 498                         if (p_div_hw == p_tohw->hw_val)
 499                                 return p_tohw->pdiv;
 500                         p_tohw++;
 501                 }
 502                 return -EINVAL;
 503         }
 504
 505         return 1 << p_div_hw;
 506 }
 507
 508 static int _get_table_rate(struct clk_hw *hw,
 509                            struct tegra_clk_pll_freq_table *cfg,
 510                            unsigned long rate, unsigned long parent_rate)
 511 {
 512         struct tegra_clk_pll *pll = to_clk_pll(hw);
 513         struct tegra_clk_pll_freq_table *sel;
 514         int p;
 515
 516         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 517                 if (sel->input_rate == parent_rate &&
 518                     sel->output_rate == rate)
 519                         break;
 520
 521         if (sel->input_rate == 0)
 522                 return -EINVAL;
 523
 524         if (pll->params->pdiv_tohw) {
 525                 p = _p_div_to_hw(hw, sel->p);
 526                 if (p < 0)
 527                         return p;
 528         } else {
 529                 p = ilog2(sel->p);
 530         }
 531
 532         cfg->input_rate = sel->input_rate;
 533         cfg->output_rate = sel->output_rate;
 534         cfg->m = sel->m;
 535         cfg->n = sel->n;
 536         cfg->p = p;
 537         cfg->cpcon = sel->cpcon;
 538         cfg->sdm_data = sel->sdm_data;
 539
 540         return 0;
 541 }
 542
 543 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 544                       unsigned long rate, unsigned long parent_rate)
 545 {
 546         struct tegra_clk_pll *pll = to_clk_pll(hw);
 547         unsigned long cfreq;
 548         u32 p_div = 0;
 549         int ret;
 550
 551         switch (parent_rate) {
 552         case 12000000:
 553         case 26000000:
 554                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 555                 break;
 556         case 13000000:
 557                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 558                 break;
 559         case 16800000:
 560         case 19200000:
 561                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 562                 break;
 563         case 9600000:
 564         case 28800000:
 565                 /*
 566                  * PLL_P_OUT1 rate is not listed in PLLA table
 567                  */
 568                 cfreq = parent_rate / (parent_rate / 1000000);
 569                 break;
 570         default:
 571                 pr_err("%s Unexpected reference rate %lu\n",
 572                        __func__, parent_rate);
 573                 BUG();
 574         }
 575
 576         /* Raise VCO to guarantee 0.5% accuracy */
 577         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 578              cfg->output_rate <<= 1)
 579                 p_div++;
 580
 581         cfg->m = parent_rate / cfreq;
 582         cfg->n = cfg->output_rate / cfreq;
 583         cfg->cpcon = OUT_OF_TABLE_CPCON;
 584
 585         if (cfg->m == 0 || cfg->m > divm_max(pll) ||
 586             cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
 587             cfg->output_rate > pll->params->vco_max) {
 588                 return -EINVAL;
 589         }
 590
 591         cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
 592         cfg->output_rate >>= p_div;
 593
 594         if (pll->params->pdiv_tohw) {
 595                 ret = _p_div_to_hw(hw, 1 << p_div);
 596                 if (ret < 0)
 597                         return ret;
 598                 else
 599                         cfg->p = ret;
 600         } else
 601                 cfg->p = p_div;
 602
 603         return 0;
 604 }
 605
 606 /*
 607  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 608  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 609  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 610  * to indicate that SDM is disabled.
 611  *
 612  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 613  */
 614 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 615                                  struct tegra_clk_pll_freq_table *cfg)
 616 {
 617         struct tegra_clk_pll *pll = to_clk_pll(hw);
 618         u32 val;
 619         bool enabled;
 620
 621         if (!pll->params->sdm_din_reg)
 622                 return;
 623
 624         if (cfg->sdm_data) {
 625                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 626                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 627                 pll_writel_sdm_din(val, pll);
 628         }
 629
 630         val = pll_readl_sdm_ctrl(pll);
 631         enabled = (val & sdm_en_mask(pll));
 632
 633         if (cfg->sdm_data == 0 && enabled)
 634                 val &= ~pll->params->sdm_ctrl_en_mask;
 635
 636         if (cfg->sdm_data != 0 && !enabled)
 637                 val |= pll->params->sdm_ctrl_en_mask;
 638
 639         pll_writel_sdm_ctrl(val, pll);
 640 }
 641
 642 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 643                             struct tegra_clk_pll_freq_table *cfg)
 644 {
 645         u32 val;
 646         struct tegra_clk_pll_params *params = pll->params;
 647         struct div_nmp *div_nmp = params->div_nmp;
 648
 649         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 650                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 651                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 652                 val = pll_override_readl(params->pmc_divp_reg, pll);
 653                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 654                 val |= cfg->p << div_nmp->override_divp_shift;
 655                 pll_override_writel(val, params->pmc_divp_reg, pll);
 656
 657                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 658                 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
 659                         (divn_mask(pll) << div_nmp->override_divn_shift));
 660                 val |= (cfg->m << div_nmp->override_divm_shift) |
 661                         (cfg->n << div_nmp->override_divn_shift);
 662                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 663         } else {
 664                 val = pll_readl_base(pll);
 665
 666                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 667                          divp_mask_shifted(pll));
 668
 669                 val |= (cfg->m << divm_shift(pll)) |
 670                        (cfg->n << divn_shift(pll)) |
 671                        (cfg->p << divp_shift(pll));
 672
 673                 pll_writel_base(val, pll);
 674
 675                 clk_pll_set_sdm_data(&pll->hw, cfg);
 676         }
 677 }
 678
 679 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 680                          struct tegra_clk_pll_freq_table *cfg)
 681 {
 682         u32 val;
 683         struct tegra_clk_pll_params *params = pll->params;
 684         struct div_nmp *div_nmp = params->div_nmp;
 685
 686         *cfg = (struct tegra_clk_pll_freq_table) { };
 687
 688         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 689                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 690                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 691                 val = pll_override_readl(params->pmc_divp_reg, pll);
 692                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 693
 694                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 695                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 696                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 697         }  else {
 698                 val = pll_readl_base(pll);
 699
 700                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 701                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 702                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 703
 704                 if (pll->params->sdm_din_reg) {
 705                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 706                                 val = pll_readl_sdm_din(pll);
 707                                 val &= sdm_din_mask(pll);
 708                                 cfg->sdm_data = sdin_din_to_data(val);
 709                         }
 710                 }
 711         }
 712 }
 713
 714 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 715                               struct tegra_clk_pll_freq_table *cfg,
 716                               unsigned long rate)
 717 {
 718         u32 val;
 719
 720         val = pll_readl_misc(pll);
 721
 722         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 723         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 724
 725         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 726                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 727                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 728                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 729         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 730                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 731                 if (rate >= (pll->params->vco_max >> 1))
 732                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 733         }
 734
 735         pll_writel_misc(val, pll);
 736 }
 737
 738 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 739                         unsigned long rate)
 740 {
 741         struct tegra_clk_pll *pll = to_clk_pll(hw);
 742         struct tegra_clk_pll_freq_table old_cfg;
 743         int state, ret = 0;
 744
 745         state = clk_pll_is_enabled(hw);
 746
 747         _get_pll_mnp(pll, &old_cfg);
 748
 749         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 750                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 751                 ret = pll->params->dyn_ramp(pll, cfg);
 752                 if (!ret)
 753                         return 0;
 754         }
 755
 756         if (state) {
 757                 pll_clk_stop_ss(pll);
 758                 _clk_pll_disable(hw);
 759         }
 760
 761         if (!pll->params->defaults_set && pll->params->set_defaults)
 762                 pll->params->set_defaults(pll);
 763
 764         _update_pll_mnp(pll, cfg);
 765
 766         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 767                 _update_pll_cpcon(pll, cfg, rate);
 768
 769         if (state) {
 770                 _clk_pll_enable(hw);
 771                 ret = clk_pll_wait_for_lock(pll);
 772                 pll_clk_start_ss(pll);
 773         }
 774
 775         return ret;
 776 }
 777
 778 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 779                         unsigned long parent_rate)
 780 {
 781         struct tegra_clk_pll *pll = to_clk_pll(hw);
 782         struct tegra_clk_pll_freq_table cfg, old_cfg;
 783         unsigned long flags = 0;
 784         int ret = 0;
 785
 786         if (pll->params->flags & TEGRA_PLL_FIXED) {
 787                 if (rate != pll->params->fixed_rate) {
 788                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 789                                 __func__, clk_hw_get_name(hw),
 790                                 pll->params->fixed_rate, rate);
 791                         return -EINVAL;
 792                 }
 793                 return 0;
 794         }
 795
 796         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 797             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 798                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 799                        clk_hw_get_name(hw), rate);
 800                 WARN_ON(1);
 801                 return -EINVAL;
 802         }
 803         if (pll->lock)
 804                 spin_lock_irqsave(pll->lock, flags);
 805
 806         _get_pll_mnp(pll, &old_cfg);
 807         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 808                 cfg.p = old_cfg.p;
 809
 810         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 811                 old_cfg.sdm_data != cfg.sdm_data)
 812                 ret = _program_pll(hw, &cfg, rate);
 813
 814         if (pll->lock)
 815                 spin_unlock_irqrestore(pll->lock, flags);
 816
 817         return ret;
 818 }
 819
 820 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 821                         unsigned long *prate)
 822 {
 823         struct tegra_clk_pll *pll = to_clk_pll(hw);
 824         struct tegra_clk_pll_freq_table cfg;
 825
 826         if (pll->params->flags & TEGRA_PLL_FIXED) {
 827                 /* PLLM/MB are used for memory; we do not change rate */
 828                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 829                         return clk_hw_get_rate(hw);
 830                 return pll->params->fixed_rate;
 831         }
 832
 833         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 834             pll->params->calc_rate(hw, &cfg, rate, *prate))
 835                 return -EINVAL;
 836
 837         return cfg.output_rate;
 838 }
 839
 840 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 841                                          unsigned long parent_rate)
 842 {
 843         struct tegra_clk_pll *pll = to_clk_pll(hw);
 844         struct tegra_clk_pll_freq_table cfg;
 845         u32 val;
 846         u64 rate = parent_rate;
 847         int pdiv;
 848
 849         val = pll_readl_base(pll);
 850
 851         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 852                 return parent_rate;
 853
 854         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 855             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 856                         !(val & PLL_BASE_OVERRIDE)) {
 857                 struct tegra_clk_pll_freq_table sel;
 858                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 859                                         parent_rate)) {
 860                         pr_err("Clock %s has unknown fixed frequency\n",
 861                                clk_hw_get_name(hw));
 862                         BUG();
 863                 }
 864                 return pll->params->fixed_rate;
 865         }
 866
 867         _get_pll_mnp(pll, &cfg);
 868
 869         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 870                 pdiv = 1;
 871         } else {
 872                 pdiv = _hw_to_p_div(hw, cfg.p);
 873                 if (pdiv < 0) {
 874                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 875                              clk_hw_get_name(hw), cfg.p);
 876                         pdiv = 1;
 877                 }
 878         }
 879
 880         if (pll->params->set_gain)
 881                 pll->params->set_gain(&cfg);
 882
 883         cfg.m *= pdiv;
 884
 885         rate *= cfg.n;
 886         do_div(rate, cfg.m);
 887
 888         return rate;
 889 }
 890
 891 static int clk_plle_training(struct tegra_clk_pll *pll)
 892 {
 893         u32 val;
 894         unsigned long timeout;
 895
 896         if (!pll->pmc)
 897                 return -ENOSYS;
 898
 899         /*
 900          * PLLE is already disabled, and setup cleared;
 901          * create falling edge on PLLE IDDQ input.
 902          */
 903         val = readl(pll->pmc + PMC_SATA_PWRGT);
 904         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 905         writel(val, pll->pmc + PMC_SATA_PWRGT);
 906
 907         val = readl(pll->pmc + PMC_SATA_PWRGT);
 908         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 909         writel(val, pll->pmc + PMC_SATA_PWRGT);
 910
 911         val = readl(pll->pmc + PMC_SATA_PWRGT);
 912         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 913         writel(val, pll->pmc + PMC_SATA_PWRGT);
 914
 915         val = pll_readl_misc(pll);
 916
 917         timeout = jiffies + msecs_to_jiffies(100);
 918         while (1) {
 919                 val = pll_readl_misc(pll);
 920                 if (val & PLLE_MISC_READY)
 921                         break;
 922                 if (time_after(jiffies, timeout)) {
 923                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 924                         return -EBUSY;
 925                 }
 926                 udelay(300);
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int clk_plle_enable(struct clk_hw *hw)
 933 {
 934         struct tegra_clk_pll *pll = to_clk_pll(hw);
 935         struct tegra_clk_pll_freq_table sel;
 936         unsigned long input_rate;
 937         u32 val;
 938         int err;
 939
 940         if (clk_pll_is_enabled(hw))
 941                 return 0;
 942
 943         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 944
 945         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 946                 return -EINVAL;
 947
 948         clk_pll_disable(hw);
 949
 950         val = pll_readl_misc(pll);
 951         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 952         pll_writel_misc(val, pll);
 953
 954         val = pll_readl_misc(pll);
 955         if (!(val & PLLE_MISC_READY)) {
 956                 err = clk_plle_training(pll);
 957                 if (err)
 958                         return err;
 959         }
 960
 961         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 962                 /* configure dividers */
 963                 val = pll_readl_base(pll);
 964                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 965                          divm_mask_shifted(pll));
 966                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 967                 val |= sel.m << divm_shift(pll);
 968                 val |= sel.n << divn_shift(pll);
 969                 val |= sel.p << divp_shift(pll);
 970                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 971                 pll_writel_base(val, pll);
 972         }
 973
 974         val = pll_readl_misc(pll);
 975         val |= PLLE_MISC_SETUP_VALUE;
 976         val |= PLLE_MISC_LOCK_ENABLE;
 977         pll_writel_misc(val, pll);
 978
 979         val = readl(pll->clk_base + PLLE_SS_CTRL);
 980         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 981         val |= PLLE_SS_DISABLE;
 982         writel(val, pll->clk_base + PLLE_SS_CTRL);
 983
 984         val = pll_readl_base(pll);
 985         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 986         pll_writel_base(val, pll);
 987
 988         clk_pll_wait_for_lock(pll);
 989
 990         return 0;
 991 }
 992
 993 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 994                                          unsigned long parent_rate)
 995 {
 996         struct tegra_clk_pll *pll = to_clk_pll(hw);
 997         u32 val = pll_readl_base(pll);
 998         u32 divn = 0, divm = 0, divp = 0;
 999         u64 rate = parent_rate;
1000
1001         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1002         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1003         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1004         divm *= divp;
1005
1006         rate *= divn;
1007         do_div(rate, divm);
1008         return rate;
1009 }
1010
1011 static void tegra_clk_pll_restore_context(struct clk_hw *hw)
1012 {
1013         struct tegra_clk_pll *pll = to_clk_pll(hw);
1014         struct clk_hw *parent = clk_hw_get_parent(hw);
1015         unsigned long parent_rate = clk_hw_get_rate(parent);
1016         unsigned long rate = clk_hw_get_rate(hw);
1017
1018         if (clk_pll_is_enabled(hw))
1019                 return;
1020
1021         if (pll->params->set_defaults)
1022                 pll->params->set_defaults(pll);
1023
1024         clk_pll_set_rate(hw, rate, parent_rate);
1025
1026         if (!__clk_get_enable_count(hw->clk))
1027                 clk_pll_disable(hw);
1028         else
1029                 clk_pll_enable(hw);
1030 }
1031
1032 const struct clk_ops tegra_clk_pll_ops = {
1033         .is_enabled = clk_pll_is_enabled,
1034         .enable = clk_pll_enable,
1035         .disable = clk_pll_disable,
1036         .recalc_rate = clk_pll_recalc_rate,
1037         .round_rate = clk_pll_round_rate,
1038         .set_rate = clk_pll_set_rate,
1039         .restore_context = tegra_clk_pll_restore_context,
1040 };
1041
1042 const struct clk_ops tegra_clk_plle_ops = {
1043         .recalc_rate = clk_plle_recalc_rate,
1044         .is_enabled = clk_pll_is_enabled,
1045         .disable = clk_pll_disable,
1046         .enable = clk_plle_enable,
1047 };
1048
1049 /*
1050  * Structure defining the fields for USB UTMI clocks Parameters.
1051  */
1052 struct utmi_clk_param {
1053         /* Oscillator Frequency in Hz */
1054         u32 osc_frequency;
1055         /* UTMIP PLL Enable Delay Count  */
1056         u8 enable_delay_count;
1057         /* UTMIP PLL Stable count */
1058         u8 stable_count;
1059         /*  UTMIP PLL Active delay count */
1060         u8 active_delay_count;
1061         /* UTMIP PLL Xtal frequency count */
1062         u8 xtal_freq_count;
1063 };
1064
1065 static const struct utmi_clk_param utmi_parameters[] = {
1066         {
1067                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1068                 .stable_count = 0x33, .active_delay_count = 0x05,
1069                 .xtal_freq_count = 0x7f
1070         }, {
1071                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1072                 .stable_count = 0x4b, .active_delay_count = 0x06,
1073                 .xtal_freq_count = 0xbb
1074         }, {
1075                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1076                 .stable_count = 0x2f, .active_delay_count = 0x04,
1077                 .xtal_freq_count = 0x76
1078         }, {
1079                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1080                 .stable_count = 0x66, .active_delay_count = 0x09,
1081                 .xtal_freq_count = 0xfe
1082         }, {
1083                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1084                 .stable_count = 0x41, .active_delay_count = 0x0a,
1085                 .xtal_freq_count = 0xa4
1086         }, {
1087                 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1088                 .stable_count = 0x0, .active_delay_count = 0x6,
1089                 .xtal_freq_count = 0x80
1090         },
1091 };
1092
1093 static int clk_pllu_enable(struct clk_hw *hw)
1094 {
1095         struct tegra_clk_pll *pll = to_clk_pll(hw);
1096         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1097         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1098         const struct utmi_clk_param *params = NULL;
1099         unsigned long flags = 0, input_rate;
1100         unsigned int i;
1101         int ret = 0;
1102         u32 value;
1103
1104         if (!osc) {
1105                 pr_err("%s: failed to get OSC clock\n", __func__);
1106                 return -EINVAL;
1107         }
1108
1109         input_rate = clk_hw_get_rate(osc);
1110
1111         if (pll->lock)
1112                 spin_lock_irqsave(pll->lock, flags);
1113
1114         _clk_pll_enable(hw);
1115
1116         ret = clk_pll_wait_for_lock(pll);
1117         if (ret < 0)
1118                 goto out;
1119
1120         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1121                 if (input_rate == utmi_parameters[i].osc_frequency) {
1122                         params = &utmi_parameters[i];
1123                         break;
1124                 }
1125         }
1126
1127         if (!params) {
1128                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1129                        input_rate);
1130                 ret = -EINVAL;
1131                 goto out;
1132         }
1133
1134         value = pll_readl_base(pll);
1135         value &= ~PLLU_BASE_OVERRIDE;
1136         pll_writel_base(value, pll);
1137
1138         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1139         /* Program UTMIP PLL stable and active counts */
1140         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1141         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1142         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1143         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1144         /* Remove power downs from UTMIP PLL control bits */
1145         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1146         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1147         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1148         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1149
1150         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1151         /* Program UTMIP PLL delay and oscillator frequency counts */
1152         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1153         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1154         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1155         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1156         /* Remove power downs from UTMIP PLL control bits */
1157         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1158         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1159         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1160         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1161
1162 out:
1163         if (pll->lock)
1164                 spin_unlock_irqrestore(pll->lock, flags);
1165
1166         return ret;
1167 }
1168
1169 static const struct clk_ops tegra_clk_pllu_ops = {
1170         .is_enabled = clk_pll_is_enabled,
1171         .enable = clk_pllu_enable,
1172         .disable = clk_pll_disable,
1173         .recalc_rate = clk_pll_recalc_rate,
1174         .round_rate = clk_pll_round_rate,
1175         .set_rate = clk_pll_set_rate,
1176 };
1177
1178 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1179                            unsigned long parent_rate)
1180 {
1181         u16 mdiv = parent_rate / pll_params->cf_min;
1182
1183         if (pll_params->flags & TEGRA_MDIV_NEW)
1184                 return (!pll_params->mdiv_default ? mdiv :
1185                         min(mdiv, pll_params->mdiv_default));
1186
1187         if (pll_params->mdiv_default)
1188                 return pll_params->mdiv_default;
1189
1190         if (parent_rate > pll_params->cf_max)
1191                 return 2;
1192         else
1193                 return 1;
1194 }
1195
1196 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1197                                 struct tegra_clk_pll_freq_table *cfg,
1198                                 unsigned long rate, unsigned long parent_rate)
1199 {
1200         struct tegra_clk_pll *pll = to_clk_pll(hw);
1201         unsigned int p;
1202         int p_div;
1203
1204         if (!rate)
1205                 return -EINVAL;
1206
1207         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1208         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1209         cfg->output_rate = rate * p;
1210         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1211         cfg->input_rate = parent_rate;
1212
1213         p_div = _p_div_to_hw(hw, p);
1214         if (p_div < 0)
1215                 return p_div;
1216
1217         cfg->p = p_div;
1218
1219         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1220                 return -EINVAL;
1221
1222         return 0;
1223 }
1224
1225 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1226         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1227         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1228         defined(CONFIG_ARCH_TEGRA_210_SOC)
1229
1230 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1231 {
1232         struct tegra_clk_pll *pll = to_clk_pll(hw);
1233
1234         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1235 }
1236
1237 static unsigned long _clip_vco_min(unsigned long vco_min,
1238                                    unsigned long parent_rate)
1239 {
1240         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1241 }
1242
1243 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1244                                void __iomem *clk_base,
1245                                unsigned long parent_rate)
1246 {
1247         u32 val;
1248         u32 step_a, step_b;
1249
1250         switch (parent_rate) {
1251         case 12000000:
1252         case 13000000:
1253         case 26000000:
1254                 step_a = 0x2B;
1255                 step_b = 0x0B;
1256                 break;
1257         case 16800000:
1258                 step_a = 0x1A;
1259                 step_b = 0x09;
1260                 break;
1261         case 19200000:
1262                 step_a = 0x12;
1263                 step_b = 0x08;
1264                 break;
1265         default:
1266                 pr_err("%s: Unexpected reference rate %lu\n",
1267                         __func__, parent_rate);
1268                 WARN_ON(1);
1269                 return -EINVAL;
1270         }
1271
1272         val = step_a << pll_params->stepa_shift;
1273         val |= step_b << pll_params->stepb_shift;
1274         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1275
1276         return 0;
1277 }
1278
1279 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1280                               struct tegra_clk_pll_freq_table *cfg,
1281                               unsigned long rate, unsigned long parent_rate)
1282 {
1283         struct tegra_clk_pll *pll = to_clk_pll(hw);
1284         int err = 0;
1285
1286         err = _get_table_rate(hw, cfg, rate, parent_rate);
1287         if (err < 0)
1288                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1289         else {
1290                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1291                         WARN_ON(1);
1292                         err = -EINVAL;
1293                         goto out;
1294                 }
1295         }
1296
1297         if (cfg->p >  pll->params->max_p)
1298                 err = -EINVAL;
1299
1300 out:
1301         return err;
1302 }
1303
1304 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1305                                 unsigned long parent_rate)
1306 {
1307         struct tegra_clk_pll *pll = to_clk_pll(hw);
1308         struct tegra_clk_pll_freq_table cfg, old_cfg;
1309         unsigned long flags = 0;
1310         int ret;
1311
1312         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1313         if (ret < 0)
1314                 return ret;
1315
1316         if (pll->lock)
1317                 spin_lock_irqsave(pll->lock, flags);
1318
1319         _get_pll_mnp(pll, &old_cfg);
1320         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1321                 cfg.p = old_cfg.p;
1322
1323         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1324                 ret = _program_pll(hw, &cfg, rate);
1325
1326         if (pll->lock)
1327                 spin_unlock_irqrestore(pll->lock, flags);
1328
1329         return ret;
1330 }
1331
1332 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1333                                 unsigned long *prate)
1334 {
1335         struct tegra_clk_pll *pll = to_clk_pll(hw);
1336         struct tegra_clk_pll_freq_table cfg;
1337         int ret, p_div;
1338         u64 output_rate = *prate;
1339
1340         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1341         if (ret < 0)
1342                 return ret;
1343
1344         p_div = _hw_to_p_div(hw, cfg.p);
1345         if (p_div < 0)
1346                 return p_div;
1347
1348         if (pll->params->set_gain)
1349                 pll->params->set_gain(&cfg);
1350
1351         output_rate *= cfg.n;
1352         do_div(output_rate, cfg.m * p_div);
1353
1354         return output_rate;
1355 }
1356
1357 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1358 {
1359         u32 val;
1360
1361         val = pll_readl_misc(pll);
1362         val |= PLLCX_MISC_STROBE;
1363         pll_writel_misc(val, pll);
1364         udelay(2);
1365
1366         val &= ~PLLCX_MISC_STROBE;
1367         pll_writel_misc(val, pll);
1368 }
1369
1370 static int clk_pllc_enable(struct clk_hw *hw)
1371 {
1372         struct tegra_clk_pll *pll = to_clk_pll(hw);
1373         u32 val;
1374         int ret;
1375         unsigned long flags = 0;
1376
1377         if (clk_pll_is_enabled(hw))
1378                 return 0;
1379
1380         if (pll->lock)
1381                 spin_lock_irqsave(pll->lock, flags);
1382
1383         _clk_pll_enable(hw);
1384         udelay(2);
1385
1386         val = pll_readl_misc(pll);
1387         val &= ~PLLCX_MISC_RESET;
1388         pll_writel_misc(val, pll);
1389         udelay(2);
1390
1391         _pllcx_strobe(pll);
1392
1393         ret = clk_pll_wait_for_lock(pll);
1394
1395         if (pll->lock)
1396                 spin_unlock_irqrestore(pll->lock, flags);
1397
1398         return ret;
1399 }
1400
1401 static void _clk_pllc_disable(struct clk_hw *hw)
1402 {
1403         struct tegra_clk_pll *pll = to_clk_pll(hw);
1404         u32 val;
1405
1406         _clk_pll_disable(hw);
1407
1408         val = pll_readl_misc(pll);
1409         val |= PLLCX_MISC_RESET;
1410         pll_writel_misc(val, pll);
1411         udelay(2);
1412 }
1413
1414 static void clk_pllc_disable(struct clk_hw *hw)
1415 {
1416         struct tegra_clk_pll *pll = to_clk_pll(hw);
1417         unsigned long flags = 0;
1418
1419         if (pll->lock)
1420                 spin_lock_irqsave(pll->lock, flags);
1421
1422         _clk_pllc_disable(hw);
1423
1424         if (pll->lock)
1425                 spin_unlock_irqrestore(pll->lock, flags);
1426 }
1427
1428 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1429                                         unsigned long input_rate, u32 n)
1430 {
1431         u32 val, n_threshold;
1432
1433         switch (input_rate) {
1434         case 12000000:
1435                 n_threshold = 70;
1436                 break;
1437         case 13000000:
1438         case 26000000:
1439                 n_threshold = 71;
1440                 break;
1441         case 16800000:
1442                 n_threshold = 55;
1443                 break;
1444         case 19200000:
1445                 n_threshold = 48;
1446                 break;
1447         default:
1448                 pr_err("%s: Unexpected reference rate %lu\n",
1449                         __func__, input_rate);
1450                 return -EINVAL;
1451         }
1452
1453         val = pll_readl_misc(pll);
1454         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1455         val |= n <= n_threshold ?
1456                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1457         pll_writel_misc(val, pll);
1458
1459         return 0;
1460 }
1461
1462 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1463                                 unsigned long parent_rate)
1464 {
1465         struct tegra_clk_pll_freq_table cfg, old_cfg;
1466         struct tegra_clk_pll *pll = to_clk_pll(hw);
1467         unsigned long flags = 0;
1468         int state, ret = 0;
1469
1470         if (pll->lock)
1471                 spin_lock_irqsave(pll->lock, flags);
1472
1473         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1474         if (ret < 0)
1475                 goto out;
1476
1477         _get_pll_mnp(pll, &old_cfg);
1478
1479         if (cfg.m != old_cfg.m) {
1480                 WARN_ON(1);
1481                 goto out;
1482         }
1483
1484         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1485                 goto out;
1486
1487         state = clk_pll_is_enabled(hw);
1488         if (state)
1489                 _clk_pllc_disable(hw);
1490
1491         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1492         if (ret < 0)
1493                 goto out;
1494
1495         _update_pll_mnp(pll, &cfg);
1496
1497         if (state)
1498                 ret = clk_pllc_enable(hw);
1499
1500 out:
1501         if (pll->lock)
1502                 spin_unlock_irqrestore(pll->lock, flags);
1503
1504         return ret;
1505 }
1506
1507 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1508                              struct tegra_clk_pll_freq_table *cfg,
1509                              unsigned long rate, unsigned long parent_rate)
1510 {
1511         u16 m, n;
1512         u64 output_rate = parent_rate;
1513
1514         m = _pll_fixed_mdiv(pll->params, parent_rate);
1515         n = rate * m / parent_rate;
1516
1517         output_rate *= n;
1518         do_div(output_rate, m);
1519
1520         if (cfg) {
1521                 cfg->m = m;
1522                 cfg->n = n;
1523         }
1524
1525         return output_rate;
1526 }
1527
1528 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1529                                 unsigned long parent_rate)
1530 {
1531         struct tegra_clk_pll_freq_table cfg, old_cfg;
1532         struct tegra_clk_pll *pll = to_clk_pll(hw);
1533         unsigned long flags = 0;
1534         int state, ret = 0;
1535
1536         if (pll->lock)
1537                 spin_lock_irqsave(pll->lock, flags);
1538
1539         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1540         _get_pll_mnp(pll, &old_cfg);
1541         cfg.p = old_cfg.p;
1542
1543         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1544                 state = clk_pll_is_enabled(hw);
1545                 if (state)
1546                         _clk_pll_disable(hw);
1547
1548                 _update_pll_mnp(pll, &cfg);
1549
1550                 if (state) {
1551                         _clk_pll_enable(hw);
1552                         ret = clk_pll_wait_for_lock(pll);
1553                 }
1554         }
1555
1556         if (pll->lock)
1557                 spin_unlock_irqrestore(pll->lock, flags);
1558
1559         return ret;
1560 }
1561
1562 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1563                                          unsigned long parent_rate)
1564 {
1565         struct tegra_clk_pll_freq_table cfg;
1566         struct tegra_clk_pll *pll = to_clk_pll(hw);
1567         u64 rate = parent_rate;
1568
1569         _get_pll_mnp(pll, &cfg);
1570
1571         rate *= cfg.n;
1572         do_div(rate, cfg.m);
1573
1574         return rate;
1575 }
1576
1577 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1578                                  unsigned long *prate)
1579 {
1580         struct tegra_clk_pll *pll = to_clk_pll(hw);
1581
1582         return _pllre_calc_rate(pll, NULL, rate, *prate);
1583 }
1584
1585 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1586 {
1587         struct tegra_clk_pll *pll = to_clk_pll(hw);
1588         struct tegra_clk_pll_freq_table sel;
1589         u32 val;
1590         int ret;
1591         unsigned long flags = 0;
1592         unsigned long input_rate;
1593
1594         if (clk_pll_is_enabled(hw))
1595                 return 0;
1596
1597         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1598
1599         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1600                 return -EINVAL;
1601
1602         if (pll->lock)
1603                 spin_lock_irqsave(pll->lock, flags);
1604
1605         val = pll_readl_base(pll);
1606         val &= ~BIT(29); /* Disable lock override */
1607         pll_writel_base(val, pll);
1608
1609         val = pll_readl(pll->params->aux_reg, pll);
1610         val |= PLLE_AUX_ENABLE_SWCTL;
1611         val &= ~PLLE_AUX_SEQ_ENABLE;
1612         pll_writel(val, pll->params->aux_reg, pll);
1613         udelay(1);
1614
1615         val = pll_readl_misc(pll);
1616         val |= PLLE_MISC_LOCK_ENABLE;
1617         val |= PLLE_MISC_IDDQ_SW_CTRL;
1618         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1619         val |= PLLE_MISC_PLLE_PTS;
1620         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1621         pll_writel_misc(val, pll);
1622         udelay(5);
1623
1624         val = pll_readl(PLLE_SS_CTRL, pll);
1625         val |= PLLE_SS_DISABLE;
1626         pll_writel(val, PLLE_SS_CTRL, pll);
1627
1628         val = pll_readl_base(pll);
1629         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1630                  divm_mask_shifted(pll));
1631         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1632         val |= sel.m << divm_shift(pll);
1633         val |= sel.n << divn_shift(pll);
1634         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1635         pll_writel_base(val, pll);
1636         udelay(1);
1637
1638         _clk_pll_enable(hw);
1639         ret = clk_pll_wait_for_lock(pll);
1640
1641         if (ret < 0)
1642                 goto out;
1643
1644         val = pll_readl(PLLE_SS_CTRL, pll);
1645         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1646         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1647         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1648         pll_writel(val, PLLE_SS_CTRL, pll);
1649         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1650         pll_writel(val, PLLE_SS_CTRL, pll);
1651         udelay(1);
1652         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1653         pll_writel(val, PLLE_SS_CTRL, pll);
1654         udelay(1);
1655
1656         /* Enable hw control of xusb brick pll */
1657         val = pll_readl_misc(pll);
1658         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1659         pll_writel_misc(val, pll);
1660
1661         val = pll_readl(pll->params->aux_reg, pll);
1662         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1663         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1664         pll_writel(val, pll->params->aux_reg, pll);
1665         udelay(1);
1666         val |= PLLE_AUX_SEQ_ENABLE;
1667         pll_writel(val, pll->params->aux_reg, pll);
1668
1669         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1670         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1671                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1672         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1673                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1674         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1675         udelay(1);
1676         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1677         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1678
1679         /* Enable hw control of SATA pll */
1680         val = pll_readl(SATA_PLL_CFG0, pll);
1681         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1682         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1683         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1684         pll_writel(val, SATA_PLL_CFG0, pll);
1685
1686         udelay(1);
1687
1688         val = pll_readl(SATA_PLL_CFG0, pll);
1689         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1690         pll_writel(val, SATA_PLL_CFG0, pll);
1691
1692 out:
1693         if (pll->lock)
1694                 spin_unlock_irqrestore(pll->lock, flags);
1695
1696         return ret;
1697 }
1698
1699 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1700 {
1701         struct tegra_clk_pll *pll = to_clk_pll(hw);
1702         unsigned long flags = 0;
1703         u32 val;
1704
1705         if (pll->lock)
1706                 spin_lock_irqsave(pll->lock, flags);
1707
1708         _clk_pll_disable(hw);
1709
1710         val = pll_readl_misc(pll);
1711         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1712         pll_writel_misc(val, pll);
1713         udelay(1);
1714
1715         if (pll->lock)
1716                 spin_unlock_irqrestore(pll->lock, flags);
1717 }
1718
1719 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1720 {
1721         struct tegra_clk_pll *pll = to_clk_pll(hw);
1722         const struct utmi_clk_param *params = NULL;
1723         struct clk *osc = __clk_lookup("osc");
1724         unsigned long flags = 0, input_rate;
1725         unsigned int i;
1726         int ret = 0;
1727         u32 value;
1728
1729         if (!osc) {
1730                 pr_err("%s: failed to get OSC clock\n", __func__);
1731                 return -EINVAL;
1732         }
1733
1734         if (clk_pll_is_enabled(hw))
1735                 return 0;
1736
1737         input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1738
1739         if (pll->lock)
1740                 spin_lock_irqsave(pll->lock, flags);
1741
1742         _clk_pll_enable(hw);
1743
1744         ret = clk_pll_wait_for_lock(pll);
1745         if (ret < 0)
1746                 goto out;
1747
1748         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1749                 if (input_rate == utmi_parameters[i].osc_frequency) {
1750                         params = &utmi_parameters[i];
1751                         break;
1752                 }
1753         }
1754
1755         if (!params) {
1756                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1757                        input_rate);
1758                 ret = -EINVAL;
1759                 goto out;
1760         }
1761
1762         value = pll_readl_base(pll);
1763         value &= ~PLLU_BASE_OVERRIDE;
1764         pll_writel_base(value, pll);
1765
1766         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1767         /* Program UTMIP PLL stable and active counts */
1768         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1769         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1770         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1771         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1772         /* Remove power downs from UTMIP PLL control bits */
1773         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1774         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1775         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1776         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1777
1778         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1779         /* Program UTMIP PLL delay and oscillator frequency counts */
1780         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1781         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1782         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1783         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1784         /* Remove power downs from UTMIP PLL control bits */
1785         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1786         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1787         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1788         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1789         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1790
1791         /* Setup HW control of UTMIPLL */
1792         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1793         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1794         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1795         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1796         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1797
1798         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1799         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1800         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1801         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1802
1803         udelay(1);
1804
1805         /*
1806          * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1807          * to USB2
1808          */
1809         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1810         value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1811         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1812         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1813
1814         udelay(1);
1815
1816         /* Enable HW control of UTMIPLL */
1817         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1818         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1819         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1820
1821 out:
1822         if (pll->lock)
1823                 spin_unlock_irqrestore(pll->lock, flags);
1824
1825         return ret;
1826 }
1827
1828 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
1829 {
1830         u32 val, val_aux;
1831
1832         /* ensure parent is set to pll_ref */
1833         val = pll_readl_base(pll);
1834         val_aux = pll_readl(pll->params->aux_reg, pll);
1835
1836         if (val & PLL_BASE_ENABLE) {
1837                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1838                     (val_aux & PLLE_AUX_PLLP_SEL))
1839                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1840                              (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1841                              "pll_re_vco");
1842         } else {
1843                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1844                 pll_writel(val_aux, pll->params->aux_reg, pll);
1845                 fence_udelay(1, pll->clk_base);
1846         }
1847 }
1848 #endif
1849
1850 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1851                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1852                 spinlock_t *lock)
1853 {
1854         struct tegra_clk_pll *pll;
1855
1856         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1857         if (!pll)
1858                 return ERR_PTR(-ENOMEM);
1859
1860         pll->clk_base = clk_base;
1861         pll->pmc = pmc;
1862
1863         pll->params = pll_params;
1864         pll->lock = lock;
1865
1866         if (!pll_params->div_nmp)
1867                 pll_params->div_nmp = &default_nmp;
1868
1869         return pll;
1870 }
1871
1872 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1873                 const char *name, const char *parent_name, unsigned long flags,
1874                 const struct clk_ops *ops)
1875 {
1876         struct clk_init_data init;
1877
1878         init.name = name;
1879         init.ops = ops;
1880         init.flags = flags;
1881         init.parent_names = (parent_name ? &parent_name : NULL);
1882         init.num_parents = (parent_name ? 1 : 0);
1883
1884         /* Default to _calc_rate if unspecified */
1885         if (!pll->params->calc_rate) {
1886                 if (pll->params->flags & TEGRA_PLLM)
1887                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1888                 else
1889                         pll->params->calc_rate = _calc_rate;
1890         }
1891
1892         if (pll->params->set_defaults)
1893                 pll->params->set_defaults(pll);
1894
1895         /* Data in .init is copied by clk_register(), so stack variable OK */
1896         pll->hw.init = &init;
1897
1898         return clk_register(NULL, &pll->hw);
1899 }
1900
1901 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1902                 void __iomem *clk_base, void __iomem *pmc,
1903                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1904                 spinlock_t *lock)
1905 {
1906         struct tegra_clk_pll *pll;
1907         struct clk *clk;
1908
1909         pll_params->flags |= TEGRA_PLL_BYPASS;
1910
1911         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1912         if (IS_ERR(pll))
1913                 return ERR_CAST(pll);
1914
1915         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1916                                       &tegra_clk_pll_ops);
1917         if (IS_ERR(clk))
1918                 kfree(pll);
1919
1920         return clk;
1921 }
1922
1923 static struct div_nmp pll_e_nmp = {
1924         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1925         .divn_width = PLLE_BASE_DIVN_WIDTH,
1926         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1927         .divm_width = PLLE_BASE_DIVM_WIDTH,
1928         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1929         .divp_width = PLLE_BASE_DIVP_WIDTH,
1930 };
1931
1932 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1933                 void __iomem *clk_base, void __iomem *pmc,
1934                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1935                 spinlock_t *lock)
1936 {
1937         struct tegra_clk_pll *pll;
1938         struct clk *clk;
1939
1940         pll_params->flags |= TEGRA_PLL_BYPASS;
1941
1942         if (!pll_params->div_nmp)
1943                 pll_params->div_nmp = &pll_e_nmp;
1944
1945         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1946         if (IS_ERR(pll))
1947                 return ERR_CAST(pll);
1948
1949         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1950                                       &tegra_clk_plle_ops);
1951         if (IS_ERR(clk))
1952                 kfree(pll);
1953
1954         return clk;
1955 }
1956
1957 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1958                 void __iomem *clk_base, unsigned long flags,
1959                 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1960 {
1961         struct tegra_clk_pll *pll;
1962         struct clk *clk;
1963
1964         pll_params->flags |= TEGRA_PLLU;
1965
1966         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1967         if (IS_ERR(pll))
1968                 return ERR_CAST(pll);
1969
1970         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1971                                       &tegra_clk_pllu_ops);
1972         if (IS_ERR(clk))
1973                 kfree(pll);
1974
1975         return clk;
1976 }
1977
1978 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1979         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1980         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1981         defined(CONFIG_ARCH_TEGRA_210_SOC)
1982 static const struct clk_ops tegra_clk_pllxc_ops = {
1983         .is_enabled = clk_pll_is_enabled,
1984         .enable = clk_pll_enable,
1985         .disable = clk_pll_disable,
1986         .recalc_rate = clk_pll_recalc_rate,
1987         .round_rate = clk_pll_ramp_round_rate,
1988         .set_rate = clk_pllxc_set_rate,
1989 };
1990
1991 static const struct clk_ops tegra_clk_pllc_ops = {
1992         .is_enabled = clk_pll_is_enabled,
1993         .enable = clk_pllc_enable,
1994         .disable = clk_pllc_disable,
1995         .recalc_rate = clk_pll_recalc_rate,
1996         .round_rate = clk_pll_ramp_round_rate,
1997         .set_rate = clk_pllc_set_rate,
1998 };
1999
2000 static const struct clk_ops tegra_clk_pllre_ops = {
2001         .is_enabled = clk_pll_is_enabled,
2002         .enable = clk_pll_enable,
2003         .disable = clk_pll_disable,
2004         .recalc_rate = clk_pllre_recalc_rate,
2005         .round_rate = clk_pllre_round_rate,
2006         .set_rate = clk_pllre_set_rate,
2007 };
2008
2009 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
2010         .is_enabled =  clk_pll_is_enabled,
2011         .enable = clk_plle_tegra114_enable,
2012         .disable = clk_plle_tegra114_disable,
2013         .recalc_rate = clk_pll_recalc_rate,
2014 };
2015
2016 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
2017         .is_enabled =  clk_pll_is_enabled,
2018         .enable = clk_pllu_tegra114_enable,
2019         .disable = clk_pll_disable,
2020         .recalc_rate = clk_pll_recalc_rate,
2021 };
2022
2023 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
2024                           void __iomem *clk_base, void __iomem *pmc,
2025                           unsigned long flags,
2026                           struct tegra_clk_pll_params *pll_params,
2027                           spinlock_t *lock)
2028 {
2029         struct tegra_clk_pll *pll;
2030         struct clk *clk, *parent;
2031         unsigned long parent_rate;
2032         u32 val, val_iddq;
2033
2034         parent = __clk_lookup(parent_name);
2035         if (!parent) {
2036                 WARN(1, "parent clk %s of %s must be registered first\n",
2037                         parent_name, name);
2038                 return ERR_PTR(-EINVAL);
2039         }
2040
2041         if (!pll_params->pdiv_tohw)
2042                 return ERR_PTR(-EINVAL);
2043
2044         parent_rate = clk_get_rate(parent);
2045
2046         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2047
2048         if (pll_params->adjust_vco)
2049                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2050                                                              parent_rate);
2051
2052         /*
2053          * If the pll has a set_defaults callback, it will take care of
2054          * configuring dynamic ramping and setting IDDQ in that path.
2055          */
2056         if (!pll_params->set_defaults) {
2057                 int err;
2058
2059                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2060                 if (err)
2061                         return ERR_PTR(err);
2062
2063                 val = readl_relaxed(clk_base + pll_params->base_reg);
2064                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2065
2066                 if (val & PLL_BASE_ENABLE)
2067                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2068                 else {
2069                         val_iddq |= BIT(pll_params->iddq_bit_idx);
2070                         writel_relaxed(val_iddq,
2071                                        clk_base + pll_params->iddq_reg);
2072                 }
2073         }
2074
2075         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2076         if (IS_ERR(pll))
2077                 return ERR_CAST(pll);
2078
2079         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2080                                       &tegra_clk_pllxc_ops);
2081         if (IS_ERR(clk))
2082                 kfree(pll);
2083
2084         return clk;
2085 }
2086
2087 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2088                           void __iomem *clk_base, void __iomem *pmc,
2089                           unsigned long flags,
2090                           struct tegra_clk_pll_params *pll_params,
2091                           spinlock_t *lock, unsigned long parent_rate)
2092 {
2093         u32 val;
2094         struct tegra_clk_pll *pll;
2095         struct clk *clk;
2096
2097         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2098
2099         if (pll_params->adjust_vco)
2100                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2101                                                              parent_rate);
2102
2103         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2104         if (IS_ERR(pll))
2105                 return ERR_CAST(pll);
2106
2107         /* program minimum rate by default */
2108
2109         val = pll_readl_base(pll);
2110         if (val & PLL_BASE_ENABLE)
2111                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2112                                 BIT(pll_params->iddq_bit_idx));
2113         else {
2114                 int m;
2115
2116                 m = _pll_fixed_mdiv(pll_params, parent_rate);
2117                 val = m << divm_shift(pll);
2118                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2119                 pll_writel_base(val, pll);
2120         }
2121
2122         /* disable lock override */
2123
2124         val = pll_readl_misc(pll);
2125         val &= ~BIT(29);
2126         pll_writel_misc(val, pll);
2127
2128         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2129                                       &tegra_clk_pllre_ops);
2130         if (IS_ERR(clk))
2131                 kfree(pll);
2132
2133         return clk;
2134 }
2135
2136 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2137                           void __iomem *clk_base, void __iomem *pmc,
2138                           unsigned long flags,
2139                           struct tegra_clk_pll_params *pll_params,
2140                           spinlock_t *lock)
2141 {
2142         struct tegra_clk_pll *pll;
2143         struct clk *clk, *parent;
2144         unsigned long parent_rate;
2145
2146         if (!pll_params->pdiv_tohw)
2147                 return ERR_PTR(-EINVAL);
2148
2149         parent = __clk_lookup(parent_name);
2150         if (!parent) {
2151                 WARN(1, "parent clk %s of %s must be registered first\n",
2152                         parent_name, name);
2153                 return ERR_PTR(-EINVAL);
2154         }
2155
2156         parent_rate = clk_get_rate(parent);
2157
2158         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2159
2160         if (pll_params->adjust_vco)
2161                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2162                                                              parent_rate);
2163
2164         pll_params->flags |= TEGRA_PLL_BYPASS;
2165         pll_params->flags |= TEGRA_PLLM;
2166         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2167         if (IS_ERR(pll))
2168                 return ERR_CAST(pll);
2169
2170         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2171                                       &tegra_clk_pll_ops);
2172         if (IS_ERR(clk))
2173                 kfree(pll);
2174
2175         return clk;
2176 }
2177
2178 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2179                           void __iomem *clk_base, void __iomem *pmc,
2180                           unsigned long flags,
2181                           struct tegra_clk_pll_params *pll_params,
2182                           spinlock_t *lock)
2183 {
2184         struct clk *parent, *clk;
2185         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2186         struct tegra_clk_pll *pll;
2187         struct tegra_clk_pll_freq_table cfg;
2188         unsigned long parent_rate;
2189
2190         if (!p_tohw)
2191                 return ERR_PTR(-EINVAL);
2192
2193         parent = __clk_lookup(parent_name);
2194         if (!parent) {
2195                 WARN(1, "parent clk %s of %s must be registered first\n",
2196                         parent_name, name);
2197                 return ERR_PTR(-EINVAL);
2198         }
2199
2200         parent_rate = clk_get_rate(parent);
2201
2202         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2203
2204         pll_params->flags |= TEGRA_PLL_BYPASS;
2205         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2206         if (IS_ERR(pll))
2207                 return ERR_CAST(pll);
2208
2209         /*
2210          * Most of PLLC register fields are shadowed, and can not be read
2211          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2212          * Initialize PLL to default state: disabled, reset; shadow registers
2213          * loaded with default parameters; dividers are preset for half of
2214          * minimum VCO rate (the latter assured that shadowed divider settings
2215          * are within supported range).
2216          */
2217
2218         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2219         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2220
2221         while (p_tohw->pdiv) {
2222                 if (p_tohw->pdiv == 2) {
2223                         cfg.p = p_tohw->hw_val;
2224                         break;
2225                 }
2226                 p_tohw++;
2227         }
2228
2229         if (!p_tohw->pdiv) {
2230                 WARN_ON(1);
2231                 return ERR_PTR(-EINVAL);
2232         }
2233
2234         pll_writel_base(0, pll);
2235         _update_pll_mnp(pll, &cfg);
2236
2237         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2238         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2239         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2240         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2241
2242         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2243
2244         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2245                                       &tegra_clk_pllc_ops);
2246         if (IS_ERR(clk))
2247                 kfree(pll);
2248
2249         return clk;
2250 }
2251
2252 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2253                                 const char *parent_name,
2254                                 void __iomem *clk_base, unsigned long flags,
2255                                 struct tegra_clk_pll_params *pll_params,
2256                                 spinlock_t *lock)
2257 {
2258         struct tegra_clk_pll *pll;
2259         struct clk *clk;
2260
2261         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2262         if (IS_ERR(pll))
2263                 return ERR_CAST(pll);
2264
2265         _clk_plle_tegra_init_parent(pll);
2266
2267         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2268                                       &tegra_clk_plle_tegra114_ops);
2269         if (IS_ERR(clk))
2270                 kfree(pll);
2271
2272         return clk;
2273 }
2274
2275 struct clk *
2276 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2277                                  void __iomem *clk_base, unsigned long flags,
2278                                  struct tegra_clk_pll_params *pll_params,
2279                                  spinlock_t *lock)
2280 {
2281         struct tegra_clk_pll *pll;
2282         struct clk *clk;
2283
2284         pll_params->flags |= TEGRA_PLLU;
2285
2286         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2287         if (IS_ERR(pll))
2288                 return ERR_CAST(pll);
2289
2290         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2291                                       &tegra_clk_pllu_tegra114_ops);
2292         if (IS_ERR(clk))
2293                 kfree(pll);
2294
2295         return clk;
2296 }
2297 #endif
2298
2299 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2300 static const struct clk_ops tegra_clk_pllss_ops = {
2301         .is_enabled = clk_pll_is_enabled,
2302         .enable = clk_pll_enable,
2303         .disable = clk_pll_disable,
2304         .recalc_rate = clk_pll_recalc_rate,
2305         .round_rate = clk_pll_ramp_round_rate,
2306         .set_rate = clk_pllxc_set_rate,
2307         .restore_context = tegra_clk_pll_restore_context,
2308 };
2309
2310 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2311                                 void __iomem *clk_base, unsigned long flags,
2312                                 struct tegra_clk_pll_params *pll_params,
2313                                 spinlock_t *lock)
2314 {
2315         struct tegra_clk_pll *pll;
2316         struct clk *clk, *parent;
2317         struct tegra_clk_pll_freq_table cfg;
2318         unsigned long parent_rate;
2319         u32 val, val_iddq;
2320         int i;
2321
2322         if (!pll_params->div_nmp)
2323                 return ERR_PTR(-EINVAL);
2324
2325         parent = __clk_lookup(parent_name);
2326         if (!parent) {
2327                 WARN(1, "parent clk %s of %s must be registered first\n",
2328                         parent_name, name);
2329                 return ERR_PTR(-EINVAL);
2330         }
2331
2332         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2333         if (IS_ERR(pll))
2334                 return ERR_CAST(pll);
2335
2336         val = pll_readl_base(pll);
2337         val &= ~PLLSS_REF_SRC_SEL_MASK;
2338         pll_writel_base(val, pll);
2339
2340         parent_rate = clk_get_rate(parent);
2341
2342         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2343
2344         /* initialize PLL to minimum rate */
2345
2346         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2347         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2348
2349         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2350                 ;
2351         if (!i) {
2352                 kfree(pll);
2353                 return ERR_PTR(-EINVAL);
2354         }
2355
2356         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2357
2358         _update_pll_mnp(pll, &cfg);
2359
2360         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2361         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2362         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2363         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2364
2365         val = pll_readl_base(pll);
2366         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2367         if (val & PLL_BASE_ENABLE) {
2368                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2369                         WARN(1, "%s is on but IDDQ set\n", name);
2370                         kfree(pll);
2371                         return ERR_PTR(-EINVAL);
2372                 }
2373         } else {
2374                 val_iddq |= BIT(pll_params->iddq_bit_idx);
2375                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2376         }
2377
2378         val &= ~PLLSS_LOCK_OVERRIDE;
2379         pll_writel_base(val, pll);
2380
2381         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2382                                         &tegra_clk_pllss_ops);
2383
2384         if (IS_ERR(clk))
2385                 kfree(pll);
2386
2387         return clk;
2388 }
2389 #endif
2390
2391 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2392 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2393                           const char *parent_name, void __iomem *clk_base,
2394                           void __iomem *pmc, unsigned long flags,
2395                           struct tegra_clk_pll_params *pll_params,
2396                           spinlock_t *lock, unsigned long parent_rate)
2397 {
2398         struct tegra_clk_pll *pll;
2399         struct clk *clk;
2400
2401         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2402
2403         if (pll_params->adjust_vco)
2404                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2405                                                              parent_rate);
2406
2407         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2408         if (IS_ERR(pll))
2409                 return ERR_CAST(pll);
2410
2411         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2412                                       &tegra_clk_pll_ops);
2413         if (IS_ERR(clk))
2414                 kfree(pll);
2415
2416         return clk;
2417 }
2418
2419 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2420 {
2421         struct tegra_clk_pll *pll = to_clk_pll(hw);
2422         u32 val;
2423
2424         val = pll_readl_base(pll);
2425
2426         return val & PLLE_BASE_ENABLE ? 1 : 0;
2427 }
2428
2429 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2430 {
2431         struct tegra_clk_pll *pll = to_clk_pll(hw);
2432         struct tegra_clk_pll_freq_table sel;
2433         u32 val;
2434         int ret = 0;
2435         unsigned long flags = 0;
2436         unsigned long input_rate;
2437
2438         if (clk_plle_tegra210_is_enabled(hw))
2439                 return 0;
2440
2441         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2442
2443         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2444                 return -EINVAL;
2445
2446         if (pll->lock)
2447                 spin_lock_irqsave(pll->lock, flags);
2448
2449         val = pll_readl(pll->params->aux_reg, pll);
2450         if (val & PLLE_AUX_SEQ_ENABLE)
2451                 goto out;
2452
2453         val = pll_readl_base(pll);
2454         val &= ~BIT(30); /* Disable lock override */
2455         pll_writel_base(val, pll);
2456
2457         val = pll_readl_misc(pll);
2458         val |= PLLE_MISC_LOCK_ENABLE;
2459         val |= PLLE_MISC_IDDQ_SW_CTRL;
2460         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2461         val |= PLLE_MISC_PLLE_PTS;
2462         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2463         pll_writel_misc(val, pll);
2464         udelay(5);
2465
2466         val = pll_readl(PLLE_SS_CTRL, pll);
2467         val |= PLLE_SS_DISABLE;
2468         pll_writel(val, PLLE_SS_CTRL, pll);
2469
2470         val = pll_readl_base(pll);
2471         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2472                  divm_mask_shifted(pll));
2473         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2474         val |= sel.m << divm_shift(pll);
2475         val |= sel.n << divn_shift(pll);
2476         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2477         pll_writel_base(val, pll);
2478         udelay(1);
2479
2480         val = pll_readl_base(pll);
2481         val |= PLLE_BASE_ENABLE;
2482         pll_writel_base(val, pll);
2483
2484         ret = clk_pll_wait_for_lock(pll);
2485
2486         if (ret < 0)
2487                 goto out;
2488
2489         val = pll_readl(PLLE_SS_CTRL, pll);
2490         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2491         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2492         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2493         pll_writel(val, PLLE_SS_CTRL, pll);
2494         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2495         pll_writel(val, PLLE_SS_CTRL, pll);
2496         udelay(1);
2497         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2498         pll_writel(val, PLLE_SS_CTRL, pll);
2499         udelay(1);
2500
2501         val = pll_readl_misc(pll);
2502         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2503         pll_writel_misc(val, pll);
2504
2505         val = pll_readl(pll->params->aux_reg, pll);
2506         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2507         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2508         pll_writel(val, pll->params->aux_reg, pll);
2509         udelay(1);
2510         val |= PLLE_AUX_SEQ_ENABLE;
2511         pll_writel(val, pll->params->aux_reg, pll);
2512
2513 out:
2514         if (pll->lock)
2515                 spin_unlock_irqrestore(pll->lock, flags);
2516
2517         return ret;
2518 }
2519
2520 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2521 {
2522         struct tegra_clk_pll *pll = to_clk_pll(hw);
2523         unsigned long flags = 0;
2524         u32 val;
2525
2526         if (pll->lock)
2527                 spin_lock_irqsave(pll->lock, flags);
2528
2529         /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2530         val = pll_readl(pll->params->aux_reg, pll);
2531         if (val & PLLE_AUX_SEQ_ENABLE)
2532                 goto out;
2533
2534         val = pll_readl_base(pll);
2535         val &= ~PLLE_BASE_ENABLE;
2536         pll_writel_base(val, pll);
2537
2538         val = pll_readl(pll->params->aux_reg, pll);
2539         val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2540         pll_writel(val, pll->params->aux_reg, pll);
2541
2542         val = pll_readl_misc(pll);
2543         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2544         pll_writel_misc(val, pll);
2545         udelay(1);
2546
2547 out:
2548         if (pll->lock)
2549                 spin_unlock_irqrestore(pll->lock, flags);
2550 }
2551
2552 static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
2553 {
2554         struct tegra_clk_pll *pll = to_clk_pll(hw);
2555
2556         _clk_plle_tegra_init_parent(pll);
2557 }
2558
2559 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2560         .is_enabled =  clk_plle_tegra210_is_enabled,
2561         .enable = clk_plle_tegra210_enable,
2562         .disable = clk_plle_tegra210_disable,
2563         .recalc_rate = clk_pll_recalc_rate,
2564         .restore_context = tegra_clk_plle_t210_restore_context,
2565 };
2566
2567 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2568                                 const char *parent_name,
2569                                 void __iomem *clk_base, unsigned long flags,
2570                                 struct tegra_clk_pll_params *pll_params,
2571                                 spinlock_t *lock)
2572 {
2573         struct tegra_clk_pll *pll;
2574         struct clk *clk;
2575
2576         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2577         if (IS_ERR(pll))
2578                 return ERR_CAST(pll);
2579
2580         _clk_plle_tegra_init_parent(pll);
2581
2582         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2583                                       &tegra_clk_plle_tegra210_ops);
2584         if (IS_ERR(clk))
2585                 kfree(pll);
2586
2587         return clk;
2588 }
2589
2590 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2591                         const char *parent_name, void __iomem *clk_base,
2592                         void __iomem *pmc, unsigned long flags,
2593                         struct tegra_clk_pll_params *pll_params,
2594                         spinlock_t *lock)
2595 {
2596         struct clk *parent, *clk;
2597         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2598         struct tegra_clk_pll *pll;
2599         unsigned long parent_rate;
2600
2601         if (!p_tohw)
2602                 return ERR_PTR(-EINVAL);
2603
2604         parent = __clk_lookup(parent_name);
2605         if (!parent) {
2606                 WARN(1, "parent clk %s of %s must be registered first\n",
2607                         name, parent_name);
2608                 return ERR_PTR(-EINVAL);
2609         }
2610
2611         parent_rate = clk_get_rate(parent);
2612
2613         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2614
2615         if (pll_params->adjust_vco)
2616                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2617                                                              parent_rate);
2618
2619         pll_params->flags |= TEGRA_PLL_BYPASS;
2620         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2621         if (IS_ERR(pll))
2622                 return ERR_CAST(pll);
2623
2624         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2625                                       &tegra_clk_pll_ops);
2626         if (IS_ERR(clk))
2627                 kfree(pll);
2628
2629         return clk;
2630 }
2631
2632 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2633                                 const char *parent_name, void __iomem *clk_base,
2634                                 unsigned long flags,
2635                                 struct tegra_clk_pll_params *pll_params,
2636                                 spinlock_t *lock)
2637 {
2638         struct tegra_clk_pll *pll;
2639         struct clk *clk, *parent;
2640         unsigned long parent_rate;
2641         u32 val;
2642
2643         if (!pll_params->div_nmp)
2644                 return ERR_PTR(-EINVAL);
2645
2646         parent = __clk_lookup(parent_name);
2647         if (!parent) {
2648                 WARN(1, "parent clk %s of %s must be registered first\n",
2649                         name, parent_name);
2650                 return ERR_PTR(-EINVAL);
2651         }
2652
2653         val = readl_relaxed(clk_base + pll_params->base_reg);
2654         if (val & PLLSS_REF_SRC_SEL_MASK) {
2655                 WARN(1, "not supported reference clock for %s\n", name);
2656                 return ERR_PTR(-EINVAL);
2657         }
2658
2659         parent_rate = clk_get_rate(parent);
2660
2661         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2662
2663         if (pll_params->adjust_vco)
2664                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2665                                                              parent_rate);
2666
2667         pll_params->flags |= TEGRA_PLL_BYPASS;
2668         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2669         if (IS_ERR(pll))
2670                 return ERR_CAST(pll);
2671
2672         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2673                                         &tegra_clk_pll_ops);
2674
2675         if (IS_ERR(clk))
2676                 kfree(pll);
2677
2678         return clk;
2679 }
2680
2681 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2682                           void __iomem *clk_base, void __iomem *pmc,
2683                           unsigned long flags,
2684                           struct tegra_clk_pll_params *pll_params,
2685                           spinlock_t *lock)
2686 {
2687         struct tegra_clk_pll *pll;
2688         struct clk *clk, *parent;
2689         unsigned long parent_rate;
2690
2691         if (!pll_params->pdiv_tohw)
2692                 return ERR_PTR(-EINVAL);
2693
2694         parent = __clk_lookup(parent_name);
2695         if (!parent) {
2696                 WARN(1, "parent clk %s of %s must be registered first\n",
2697                         parent_name, name);
2698                 return ERR_PTR(-EINVAL);
2699         }
2700
2701         parent_rate = clk_get_rate(parent);
2702
2703         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2704
2705         if (pll_params->adjust_vco)
2706                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2707                                                              parent_rate);
2708
2709         pll_params->flags |= TEGRA_PLL_BYPASS;
2710         pll_params->flags |= TEGRA_PLLMB;
2711         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2712         if (IS_ERR(pll))
2713                 return ERR_CAST(pll);
2714
2715         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2716                                       &tegra_clk_pll_ops);
2717         if (IS_ERR(clk))
2718                 kfree(pll);
2719
2720         return clk;
2721 }
2722
2723 #endif