1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk-provider.h>
8 #include <linux/clkdev.h>
10 #include <linux/of_address.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13 #include <linux/clk/tegra.h>
18 #define PMC_CLK_OUT_CNTRL 0x1a8
19 #define PMC_DPD_PADS_ORIDE 0x1c
20 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
22 #define PMC_CTRL_BLINK_ENB 7
23 #define PMC_BLINK_TIMER 0x40
25 struct pmc_clk_init_data {
37 #define PMC_CLK(_num, _mux_shift, _gate_shift)\
39 .mux_name = "clk_out_" #_num "_mux",\
40 .gate_name = "clk_out_" #_num,\
41 .parents = clk_out ##_num ##_parents,\
42 .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
43 .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
44 .gate_id = tegra_clk_clk_out_ ##_num,\
45 .dev_name = "extern" #_num,\
46 .mux_shift = _mux_shift,\
47 .gate_shift = _gate_shift,\
50 static DEFINE_SPINLOCK(clk_out_lock);
52 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
53 "clk_m_div4", "extern1",
56 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
57 "clk_m_div4", "extern2",
60 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
61 "clk_m_div4", "extern3",
64 static struct pmc_clk_init_data pmc_clks[] = {
70 void __init tegra_pmc_clk_init(void __iomem *pmc_base,
71 struct tegra_clk *tegra_clks)
77 for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
78 struct pmc_clk_init_data *data;
82 dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
86 clk = clk_register_mux(NULL, data->mux_name, data->parents,
88 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
89 pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
94 dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
98 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
100 pmc_base + PMC_CLK_OUT_CNTRL,
101 data->gate_shift, 0, &clk_out_lock);
103 clk_register_clkdev(clk, data->dev_name, data->gate_name);
107 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
108 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
109 pmc_base + PMC_DPD_PADS_ORIDE,
110 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
112 dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
116 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
118 PMC_CTRL_BLINK_ENB, 0, NULL);
119 clk_register_clkdev(clk, "blink", NULL);