1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
11 #include <linux/of_address.h>
12 #include <linux/delay.h>
13 #include <linux/export.h>
14 #include <linux/mutex.h>
15 #include <linux/clk/tegra.h>
16 #include <dt-bindings/clock/tegra210-car.h>
17 #include <dt-bindings/reset/tegra210-car.h>
18 #include <linux/iopoll.h>
19 #include <linux/sizes.h>
20 #include <soc/tegra/pmc.h>
26 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
27 * banks present in the Tegra210 CAR IP block. The banks are
28 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
29 * periph_regs[] in drivers/clk/tegra/clk.c
31 #define TEGRA210_CAR_BANK_COUNT 7
33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_LA 0x1f8
37 #define CLK_SOURCE_SDMMC2 0x154
38 #define CLK_SOURCE_SDMMC4 0x164
40 #define PLLC_BASE 0x80
42 #define PLLC_MISC0 0x88
43 #define PLLC_MISC1 0x8c
44 #define PLLC_MISC2 0x5d0
45 #define PLLC_MISC3 0x5d4
47 #define PLLC2_BASE 0x4e8
48 #define PLLC2_MISC0 0x4ec
49 #define PLLC2_MISC1 0x4f0
50 #define PLLC2_MISC2 0x4f4
51 #define PLLC2_MISC3 0x4f8
53 #define PLLC3_BASE 0x4fc
54 #define PLLC3_MISC0 0x500
55 #define PLLC3_MISC1 0x504
56 #define PLLC3_MISC2 0x508
57 #define PLLC3_MISC3 0x50c
59 #define PLLM_BASE 0x90
60 #define PLLM_MISC1 0x98
61 #define PLLM_MISC2 0x9c
62 #define PLLP_BASE 0xa0
63 #define PLLP_MISC0 0xac
64 #define PLLP_MISC1 0x680
65 #define PLLA_BASE 0xb0
66 #define PLLA_MISC0 0xbc
67 #define PLLA_MISC1 0xb8
68 #define PLLA_MISC2 0x5d8
69 #define PLLD_BASE 0xd0
70 #define PLLD_MISC0 0xdc
71 #define PLLD_MISC1 0xd8
72 #define PLLU_BASE 0xc0
73 #define PLLU_OUTA 0xc4
74 #define PLLU_MISC0 0xcc
75 #define PLLU_MISC1 0xc8
76 #define PLLX_BASE 0xe0
77 #define PLLX_MISC0 0xe4
78 #define PLLX_MISC1 0x510
79 #define PLLX_MISC2 0x514
80 #define PLLX_MISC3 0x518
81 #define PLLX_MISC4 0x5f0
82 #define PLLX_MISC5 0x5f4
83 #define PLLE_BASE 0xe8
84 #define PLLE_MISC0 0xec
85 #define PLLD2_BASE 0x4b8
86 #define PLLD2_MISC0 0x4bc
87 #define PLLD2_MISC1 0x570
88 #define PLLD2_MISC2 0x574
89 #define PLLD2_MISC3 0x578
90 #define PLLE_AUX 0x48c
91 #define PLLRE_BASE 0x4c4
92 #define PLLRE_MISC0 0x4c8
93 #define PLLRE_OUT1 0x4cc
94 #define PLLDP_BASE 0x590
95 #define PLLDP_MISC 0x594
97 #define PLLC4_BASE 0x5a4
98 #define PLLC4_MISC0 0x5a8
99 #define PLLC4_OUT 0x5e4
100 #define PLLMB_BASE 0x5e8
101 #define PLLMB_MISC1 0x5ec
102 #define PLLA1_BASE 0x6a4
103 #define PLLA1_MISC0 0x6a8
104 #define PLLA1_MISC1 0x6ac
105 #define PLLA1_MISC2 0x6b0
106 #define PLLA1_MISC3 0x6b4
108 #define PLLU_IDDQ_BIT 31
109 #define PLLCX_IDDQ_BIT 27
110 #define PLLRE_IDDQ_BIT 24
111 #define PLLA_IDDQ_BIT 25
112 #define PLLD_IDDQ_BIT 20
113 #define PLLSS_IDDQ_BIT 18
114 #define PLLM_IDDQ_BIT 5
115 #define PLLMB_IDDQ_BIT 17
116 #define PLLXP_IDDQ_BIT 3
118 #define PLLCX_RESET_BIT 30
120 #define PLL_BASE_LOCK BIT(27)
121 #define PLLCX_BASE_LOCK BIT(26)
122 #define PLLE_MISC_LOCK BIT(11)
123 #define PLLRE_MISC_LOCK BIT(27)
125 #define PLL_MISC_LOCK_ENABLE 18
126 #define PLLC_MISC_LOCK_ENABLE 24
127 #define PLLDU_MISC_LOCK_ENABLE 22
128 #define PLLU_MISC_LOCK_ENABLE 29
129 #define PLLE_MISC_LOCK_ENABLE 9
130 #define PLLRE_MISC_LOCK_ENABLE 30
131 #define PLLSS_MISC_LOCK_ENABLE 30
132 #define PLLP_MISC_LOCK_ENABLE 18
133 #define PLLM_MISC_LOCK_ENABLE 4
134 #define PLLMB_MISC_LOCK_ENABLE 16
135 #define PLLA_MISC_LOCK_ENABLE 28
136 #define PLLU_MISC_LOCK_ENABLE 29
137 #define PLLD_MISC_LOCK_ENABLE 18
139 #define PLLA_SDM_DIN_MASK 0xffff
140 #define PLLA_SDM_EN_MASK BIT(26)
142 #define PLLD_SDM_EN_MASK BIT(16)
144 #define PLLD2_SDM_EN_MASK BIT(31)
145 #define PLLD2_SSC_EN_MASK 0
147 #define PLLDP_SS_CFG 0x598
148 #define PLLDP_SDM_EN_MASK BIT(31)
149 #define PLLDP_SSC_EN_MASK BIT(30)
150 #define PLLDP_SS_CTRL1 0x59c
151 #define PLLDP_SS_CTRL2 0x5a0
153 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
154 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
156 #define UTMIP_PLL_CFG2 0x488
157 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
158 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
159 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
160 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
168 #define UTMIP_PLL_CFG1 0x484
169 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
170 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
171 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
172 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
173 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
174 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
175 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
177 #define SATA_PLL_CFG0 0x490
178 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
179 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
180 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
181 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
182 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
183 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
185 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
186 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
188 #define XUSBIO_PLL_CFG0 0x51c
189 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
190 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
191 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
192 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
193 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
195 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
196 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
197 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
198 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
199 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
200 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
201 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
202 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
203 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
204 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
205 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
207 #define PLLU_HW_PWRDN_CFG0 0x530
208 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
209 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
210 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
211 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
212 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
213 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
215 #define XUSB_PLL_CFG0 0x534
216 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
217 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
219 #define SPARE_REG0 0x55c
220 #define CLK_M_DIVISOR_SHIFT 2
221 #define CLK_M_DIVISOR_MASK 0x3
223 #define RST_DFLL_DVCO 0x2f4
224 #define DVFS_DFLL_RESET_SHIFT 0
226 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
227 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
229 #define LVL2_CLK_GATE_OVRA 0xf8
230 #define LVL2_CLK_GATE_OVRC 0x3a0
231 #define LVL2_CLK_GATE_OVRD 0x3a4
232 #define LVL2_CLK_GATE_OVRE 0x554
234 /* I2S registers to handle during APE MBIST WAR */
235 #define TEGRA210_I2S_BASE 0x1000
236 #define TEGRA210_I2S_SIZE 0x100
237 #define TEGRA210_I2S_CTRLS 5
238 #define TEGRA210_I2S_CG 0x88
239 #define TEGRA210_I2S_CTRL 0xa0
241 /* DISPA registers to handle during MBIST WAR */
242 #define DC_CMD_DISPLAY_COMMAND 0xc8
243 #define DC_COM_DSC_TOP_CTL 0xcf8
245 /* VIC register to handle during MBIST WAR */
246 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
248 /* APE, DISPA and VIC base addesses needed for MBIST WAR */
249 #define TEGRA210_AHUB_BASE 0x702d0000
250 #define TEGRA210_DISPA_BASE 0x54200000
251 #define TEGRA210_VIC_BASE 0x54340000
254 * SDM fractional divisor is 16-bit 2's complement signed number within
255 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
256 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
257 * indicate that SDM is disabled.
259 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
261 #define PLL_SDM_COEFF BIT(13)
262 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
263 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
264 /* This macro returns ndiv effective scaled to SDM range */
265 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
266 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
268 /* Tegra CPU clock and reset control regs */
269 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
271 #ifdef CONFIG_PM_SLEEP
272 static struct cpu_clk_suspend_context {
274 } tegra210_cpu_clk_sctx;
277 struct tegra210_domain_mbist_war {
278 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
279 const u32 lvl2_offset;
281 const unsigned int num_clks;
282 const unsigned int *clk_init_data;
283 struct clk_bulk_data *clks;
286 static struct clk **clks;
288 static void __iomem *clk_base;
289 static void __iomem *pmc_base;
290 static void __iomem *ahub_base;
291 static void __iomem *dispa_base;
292 static void __iomem *vic_base;
294 static unsigned long osc_freq;
295 static unsigned long pll_ref_freq;
297 static DEFINE_SPINLOCK(pll_d_lock);
298 static DEFINE_SPINLOCK(pll_e_lock);
299 static DEFINE_SPINLOCK(pll_re_lock);
300 static DEFINE_SPINLOCK(pll_u_lock);
301 static DEFINE_SPINLOCK(sor1_lock);
302 static DEFINE_SPINLOCK(emc_lock);
303 static DEFINE_MUTEX(lvl2_ovr_lock);
305 /* possible OSC frequencies in Hz */
306 static unsigned long tegra210_input_freq[] = {
311 static const char *mux_pllmcp_clkm[] = {
312 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
315 #define mux_pllmcp_clkm_idx NULL
317 #define PLL_ENABLE (1 << 30)
319 #define PLLCX_MISC1_IDDQ (1 << 27)
320 #define PLLCX_MISC0_RESET (1 << 30)
322 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
323 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
324 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
325 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
326 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
327 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
328 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
329 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
332 #define PLLA_BASE_IDDQ (1 << 25)
333 #define PLLA_BASE_LOCK (1 << 27)
335 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
336 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
338 #define PLLA_MISC2_EN_SDM (1 << 26)
339 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
341 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
342 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
343 #define PLLA_MISC2_DEFAULT_VALUE 0x0
344 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
347 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
349 #define PLLD_MISC0_EN_SDM (1 << 16)
350 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
351 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
352 #define PLLD_MISC0_IDDQ (1 << 20)
353 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
355 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
356 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
357 #define PLLD_MISC1_DEFAULT_VALUE 0x20
358 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
360 /* PLLD2 and PLLDP and PLLC4 */
361 #define PLLDSS_BASE_LOCK (1 << 27)
362 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
363 #define PLLDSS_BASE_IDDQ (1 << 18)
364 #define PLLDSS_BASE_REF_SEL_SHIFT 25
365 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
367 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
369 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
370 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
372 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
373 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
374 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
375 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
377 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
378 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
379 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
380 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
382 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
383 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
384 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
385 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
387 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
390 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
391 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
392 #define PLLRE_MISC0_LOCK (1 << 27)
393 #define PLLRE_MISC0_IDDQ (1 << 24)
395 #define PLLRE_BASE_DEFAULT_VALUE 0x0
396 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
398 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
399 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
402 #define PLLX_USE_DYN_RAMP 1
403 #define PLLX_BASE_LOCK (1 << 27)
405 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
406 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
408 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
409 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
410 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
411 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
412 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
413 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
414 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
415 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
416 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
418 #define PLLX_MISC3_IDDQ (0x1 << 3)
420 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
421 #define PLLX_MISC0_WRITE_MASK 0x10c40000
422 #define PLLX_MISC1_DEFAULT_VALUE 0x20
423 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
424 #define PLLX_MISC2_DEFAULT_VALUE 0x0
425 #define PLLX_MISC2_WRITE_MASK 0xffffff11
426 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
427 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
428 #define PLLX_MISC4_DEFAULT_VALUE 0x0
429 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
430 #define PLLX_MISC5_DEFAULT_VALUE 0x0
431 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
433 #define PLLX_HW_CTRL_CFG 0x548
434 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
437 #define PLLMB_BASE_LOCK (1 << 27)
439 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
440 #define PLLMB_MISC1_IDDQ (1 << 17)
441 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
443 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
444 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
447 #define PLLP_BASE_OVERRIDE (1 << 28)
448 #define PLLP_BASE_LOCK (1 << 27)
450 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
451 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
452 #define PLLP_MISC0_IDDQ (1 << 3)
454 #define PLLP_MISC1_HSIO_EN_SHIFT 29
455 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
456 #define PLLP_MISC1_XUSB_EN_SHIFT 28
457 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
459 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
460 #define PLLP_MISC1_DEFAULT_VALUE 0x0
462 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
463 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
466 #define PLLU_BASE_LOCK (1 << 27)
467 #define PLLU_BASE_OVERRIDE (1 << 24)
468 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
469 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
470 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
471 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
472 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
473 PLLU_BASE_CLKENABLE_HSIC |\
474 PLLU_BASE_CLKENABLE_ICUSB |\
475 PLLU_BASE_CLKENABLE_48M)
477 #define PLLU_MISC0_IDDQ (1 << 31)
478 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
479 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
481 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
482 #define PLLU_MISC1_DEFAULT_VALUE 0x0
484 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
485 #define PLLU_MISC1_WRITE_MASK 0x00000007
487 void tegra210_xusb_pll_hw_control_enable(void)
491 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
492 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
493 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
494 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
495 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
496 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
498 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
500 void tegra210_xusb_pll_hw_sequence_start(void)
504 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
505 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
508 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
510 void tegra210_sata_pll_hw_control_enable(void)
514 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
515 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
516 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
517 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
518 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
520 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
522 void tegra210_sata_pll_hw_sequence_start(void)
526 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
527 val |= SATA_PLL_CFG0_SEQ_ENABLE;
528 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
530 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
532 void tegra210_set_sata_pll_seq_sw(bool state)
536 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
538 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
539 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
540 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
541 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
543 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
544 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
545 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
546 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
548 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
550 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
552 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
556 val = readl_relaxed(clk_base + mbist->lvl2_offset);
557 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
558 fence_udelay(1, clk_base);
559 writel_relaxed(val, clk_base + mbist->lvl2_offset);
560 fence_udelay(1, clk_base);
563 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
565 u32 csi_src, ovra, ovre;
566 unsigned long flags = 0;
568 spin_lock_irqsave(&pll_d_lock, flags);
570 csi_src = readl_relaxed(clk_base + PLLD_BASE);
571 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
572 fence_udelay(1, clk_base);
574 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
575 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
576 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
577 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
578 fence_udelay(1, clk_base);
580 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
581 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
582 writel_relaxed(csi_src, clk_base + PLLD_BASE);
583 fence_udelay(1, clk_base);
585 spin_unlock_irqrestore(&pll_d_lock, flags);
588 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
590 u32 ovra, dsc_top_ctrl;
592 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
593 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
594 fence_udelay(1, clk_base);
596 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
597 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
598 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
599 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
600 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
602 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
603 fence_udelay(1, clk_base);
606 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
610 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
611 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
612 fence_udelay(1, clk_base);
614 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
615 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
616 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
617 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
619 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
620 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
622 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
623 fence_udelay(1, clk_base);
626 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
628 void __iomem *i2s_base;
632 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
633 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
634 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
635 writel_relaxed(ovre | BIT(10) | BIT(11),
636 clk_base + LVL2_CLK_GATE_OVRE);
637 fence_udelay(1, clk_base);
639 i2s_base = ahub_base + TEGRA210_I2S_BASE;
641 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
644 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
645 writel_relaxed(i2s_ctrl | BIT(10),
646 i2s_base + TEGRA210_I2S_CTRL);
647 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
648 readl(i2s_base + TEGRA210_I2S_CG);
649 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
650 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
651 readl(i2s_base + TEGRA210_I2S_CTRL);
653 i2s_base += TEGRA210_I2S_SIZE;
656 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
657 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
658 fence_udelay(1, clk_base);
661 static inline void _pll_misc_chk_default(void __iomem *base,
662 struct tegra_clk_pll_params *params,
663 u8 misc_num, u32 default_val, u32 mask)
665 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
669 if (boot_val != default_val) {
670 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
671 misc_num, boot_val, default_val);
672 pr_warn(" (comparison mask = 0x%x)\n", mask);
673 params->defaults_set = false;
678 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
679 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
680 * that changes NDIV only, while PLL is already locked.
682 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
686 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
687 _pll_misc_chk_default(clk_base, params, 0, default_val,
688 PLLCX_MISC0_WRITE_MASK);
690 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
691 _pll_misc_chk_default(clk_base, params, 1, default_val,
692 PLLCX_MISC1_WRITE_MASK);
694 default_val = PLLCX_MISC2_DEFAULT_VALUE;
695 _pll_misc_chk_default(clk_base, params, 2, default_val,
696 PLLCX_MISC2_WRITE_MASK);
698 default_val = PLLCX_MISC3_DEFAULT_VALUE;
699 _pll_misc_chk_default(clk_base, params, 3, default_val,
700 PLLCX_MISC3_WRITE_MASK);
703 static void tegra210_pllcx_set_defaults(const char *name,
704 struct tegra_clk_pll *pllcx)
706 pllcx->params->defaults_set = true;
708 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
709 /* PLL is ON: only check if defaults already set */
710 pllcx_check_defaults(pllcx->params);
711 if (!pllcx->params->defaults_set)
712 pr_warn("%s already enabled. Postponing set full defaults\n",
717 /* Defaults assert PLL reset, and set IDDQ */
718 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
719 clk_base + pllcx->params->ext_misc_reg[0]);
720 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
721 clk_base + pllcx->params->ext_misc_reg[1]);
722 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
723 clk_base + pllcx->params->ext_misc_reg[2]);
724 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
725 clk_base + pllcx->params->ext_misc_reg[3]);
729 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
731 tegra210_pllcx_set_defaults("PLL_C", pllcx);
734 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
736 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
739 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
741 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
744 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
746 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
751 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
752 * Fractional SDM is allowed to provide exact audio rates.
754 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
757 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
759 plla->params->defaults_set = true;
761 if (val & PLL_ENABLE) {
763 * PLL is ON: check if defaults already set, then set those
764 * that can be updated in flight.
766 if (val & PLLA_BASE_IDDQ) {
767 pr_warn("PLL_A boot enabled with IDDQ set\n");
768 plla->params->defaults_set = false;
771 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
773 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
774 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
775 _pll_misc_chk_default(clk_base, plla->params, 0, val,
776 ~mask & PLLA_MISC0_WRITE_MASK);
778 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
779 _pll_misc_chk_default(clk_base, plla->params, 2, val,
780 PLLA_MISC2_EN_DYNRAMP);
782 /* Enable lock detect */
783 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
785 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
786 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
792 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
793 val |= PLLA_BASE_IDDQ;
794 writel_relaxed(val, clk_base + plla->params->base_reg);
795 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
796 clk_base + plla->params->ext_misc_reg[0]);
797 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
798 clk_base + plla->params->ext_misc_reg[2]);
804 * PLL with fractional SDM.
806 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
811 plld->params->defaults_set = true;
813 if (readl_relaxed(clk_base + plld->params->base_reg) &
817 * PLL is ON: check if defaults already set, then set those
818 * that can be updated in flight.
820 val = PLLD_MISC1_DEFAULT_VALUE;
821 _pll_misc_chk_default(clk_base, plld->params, 1,
822 val, PLLD_MISC1_WRITE_MASK);
824 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
825 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
826 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
827 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
828 _pll_misc_chk_default(clk_base, plld->params, 0, val,
829 ~mask & PLLD_MISC0_WRITE_MASK);
831 if (!plld->params->defaults_set)
832 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
834 /* Enable lock detect */
835 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
836 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
838 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
839 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
845 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
846 val &= PLLD_MISC0_DSI_CLKENABLE;
847 val |= PLLD_MISC0_DEFAULT_VALUE;
848 /* set IDDQ, enable lock detect, disable SDM */
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
850 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
851 plld->params->ext_misc_reg[1]);
857 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
859 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
860 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
863 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
865 plldss->params->defaults_set = true;
867 if (val & PLL_ENABLE) {
870 * PLL is ON: check if defaults already set, then set those
871 * that can be updated in flight.
873 if (val & PLLDSS_BASE_IDDQ) {
874 pr_warn("plldss boot enabled with IDDQ set\n");
875 plldss->params->defaults_set = false;
878 /* ignore lock enable */
879 default_val = misc0_val;
880 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
881 PLLDSS_MISC0_WRITE_MASK &
882 (~PLLDSS_MISC0_LOCK_ENABLE));
885 * If SSC is used, check all settings, otherwise just confirm
886 * that SSC is not used on boot as well. Do nothing when using
887 * this function for PLLC4 that has only MISC0.
889 if (plldss->params->ssc_ctrl_en_mask) {
890 default_val = misc1_val;
891 _pll_misc_chk_default(clk_base, plldss->params, 1,
892 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
893 default_val = misc2_val;
894 _pll_misc_chk_default(clk_base, plldss->params, 2,
895 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
896 default_val = misc3_val;
897 _pll_misc_chk_default(clk_base, plldss->params, 3,
898 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
899 } else if (plldss->params->ext_misc_reg[1]) {
900 default_val = misc1_val;
901 _pll_misc_chk_default(clk_base, plldss->params, 1,
902 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
903 (~PLLDSS_MISC1_CFG_EN_SDM));
906 if (!plldss->params->defaults_set)
907 pr_warn("%s already enabled. Postponing set full defaults\n",
910 /* Enable lock detect */
911 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
912 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
913 writel_relaxed(val, clk_base +
914 plldss->params->base_reg);
917 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
918 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
919 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
920 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
926 /* set IDDQ, enable lock detect, configure SDM/SSC */
927 val |= PLLDSS_BASE_IDDQ;
928 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
929 writel_relaxed(val, clk_base + plldss->params->base_reg);
931 /* When using this function for PLLC4 exit here */
932 if (!plldss->params->ext_misc_reg[1]) {
933 writel_relaxed(misc0_val, clk_base +
934 plldss->params->ext_misc_reg[0]);
939 writel_relaxed(misc0_val, clk_base +
940 plldss->params->ext_misc_reg[0]);
941 /* if SSC used set by 1st enable */
942 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
943 clk_base + plldss->params->ext_misc_reg[1]);
944 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
945 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
949 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
951 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
952 PLLD2_MISC1_CFG_DEFAULT_VALUE,
953 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
954 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
957 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
959 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
960 PLLDP_MISC1_CFG_DEFAULT_VALUE,
961 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
962 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
967 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
968 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
970 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
972 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
977 * VCO is exposed to the clock tree directly along with post-divider output
979 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
982 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
984 pllre->params->defaults_set = true;
986 if (val & PLL_ENABLE) {
987 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
990 * PLL is ON: check if defaults already set, then set those
991 * that can be updated in flight.
993 val &= PLLRE_BASE_DEFAULT_MASK;
994 if (val != PLLRE_BASE_DEFAULT_VALUE) {
995 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
996 val, PLLRE_BASE_DEFAULT_VALUE);
997 pr_warn("(comparison mask = 0x%x)\n",
998 PLLRE_BASE_DEFAULT_MASK);
999 pllre->params->defaults_set = false;
1002 /* Ignore lock enable */
1003 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
1004 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
1005 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1006 ~mask & PLLRE_MISC0_WRITE_MASK);
1008 /* Enable lock detect */
1009 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1011 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
1012 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1018 /* set IDDQ, enable lock detect */
1019 val &= ~PLLRE_BASE_DEFAULT_MASK;
1020 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
1021 writel_relaxed(val, clk_base + pllre->params->base_reg);
1022 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
1023 clk_base + pllre->params->ext_misc_reg[0]);
1027 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
1029 unsigned long input_rate;
1032 if (!IS_ERR_OR_NULL(hw->clk))
1033 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1035 input_rate = 38400000;
1037 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
1039 switch (input_rate) {
1055 pr_err("%s: Unexpected reference rate %lu\n",
1056 __func__, input_rate);
1061 static void pllx_check_defaults(struct tegra_clk_pll *pll)
1065 default_val = PLLX_MISC0_DEFAULT_VALUE;
1066 /* ignore lock enable */
1067 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1068 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
1070 default_val = PLLX_MISC1_DEFAULT_VALUE;
1071 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1072 PLLX_MISC1_WRITE_MASK);
1074 /* ignore all but control bit */
1075 default_val = PLLX_MISC2_DEFAULT_VALUE;
1076 _pll_misc_chk_default(clk_base, pll->params, 2,
1077 default_val, PLLX_MISC2_EN_DYNRAMP);
1079 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
1080 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1081 PLLX_MISC3_WRITE_MASK);
1083 default_val = PLLX_MISC4_DEFAULT_VALUE;
1084 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1085 PLLX_MISC4_WRITE_MASK);
1087 default_val = PLLX_MISC5_DEFAULT_VALUE;
1088 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1089 PLLX_MISC5_WRITE_MASK);
1092 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
1097 pllx->params->defaults_set = true;
1099 /* Get ready dyn ramp state machine settings */
1100 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
1101 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
1102 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
1103 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
1104 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
1106 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1109 * PLL is ON: check if defaults already set, then set those
1110 * that can be updated in flight.
1112 pllx_check_defaults(pllx);
1114 if (!pllx->params->defaults_set)
1115 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1116 /* Configure dyn ramp, disable lock override */
1117 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1119 /* Enable lock detect */
1120 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1121 val &= ~PLLX_MISC0_LOCK_ENABLE;
1122 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
1123 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1129 /* Enable lock detect and CPU output */
1130 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1131 pllx->params->ext_misc_reg[0]);
1134 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1135 pllx->params->ext_misc_reg[1]);
1137 /* Configure dyn ramp state machine, disable lock override */
1138 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1141 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1142 pllx->params->ext_misc_reg[3]);
1145 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1146 pllx->params->ext_misc_reg[4]);
1147 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1148 pllx->params->ext_misc_reg[5]);
1153 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
1155 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1157 pllmb->params->defaults_set = true;
1159 if (val & PLL_ENABLE) {
1162 * PLL is ON: check if defaults already set, then set those
1163 * that can be updated in flight.
1165 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
1166 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
1167 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1168 ~mask & PLLMB_MISC1_WRITE_MASK);
1170 if (!pllmb->params->defaults_set)
1171 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1172 /* Enable lock detect */
1173 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1175 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
1176 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1182 /* set IDDQ, enable lock detect */
1183 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
1184 clk_base + pllmb->params->ext_misc_reg[0]);
1190 * VCO is exposed to the clock tree directly along with post-divider output.
1191 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
1194 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1198 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
1199 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
1200 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1202 mask |= PLLP_MISC0_IDDQ;
1203 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1204 ~mask & PLLP_MISC0_WRITE_MASK);
1206 /* Ignore branch controls */
1207 val = PLLP_MISC1_DEFAULT_VALUE;
1208 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1209 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1210 ~mask & PLLP_MISC1_WRITE_MASK);
1213 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1216 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1218 pllp->params->defaults_set = true;
1220 if (val & PLL_ENABLE) {
1223 * PLL is ON: check if defaults already set, then set those
1224 * that can be updated in flight.
1226 pllp_check_defaults(pllp, true);
1227 if (!pllp->params->defaults_set)
1228 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1230 /* Enable lock detect */
1231 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1232 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1234 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
1235 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1241 /* set IDDQ, enable lock detect */
1242 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
1243 clk_base + pllp->params->ext_misc_reg[0]);
1245 /* Preserve branch control */
1246 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1247 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1249 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1250 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1256 * VCO is exposed to the clock tree directly along with post-divider output.
1257 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1260 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1265 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1266 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1267 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1268 _pll_misc_chk_default(clk_base, params, 0, val,
1269 ~mask & PLLU_MISC0_WRITE_MASK);
1271 val = PLLU_MISC1_DEFAULT_VALUE;
1272 mask = PLLU_MISC1_LOCK_OVERRIDE;
1273 _pll_misc_chk_default(clk_base, params, 1, val,
1274 ~mask & PLLU_MISC1_WRITE_MASK);
1277 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1279 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1281 pllu->defaults_set = true;
1283 if (val & PLL_ENABLE) {
1286 * PLL is ON: check if defaults already set, then set those
1287 * that can be updated in flight.
1289 pllu_check_defaults(pllu, false);
1290 if (!pllu->defaults_set)
1291 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1293 /* Enable lock detect */
1294 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1295 val &= ~PLLU_MISC0_LOCK_ENABLE;
1296 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1297 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1299 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1300 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1301 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1302 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1308 /* set IDDQ, enable lock detect */
1309 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1310 clk_base + pllu->ext_misc_reg[0]);
1311 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1312 clk_base + pllu->ext_misc_reg[1]);
1316 #define mask(w) ((1 << (w)) - 1)
1317 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1318 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1319 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1320 mask(p->params->div_nmp->divp_width))
1322 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1323 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1324 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1326 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1327 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1328 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1330 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1331 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1337 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1338 udelay(PLL_LOCKDET_DELAY);
1339 val = readl_relaxed(clk_base + reg);
1340 if ((val & mask) == mask) {
1341 udelay(PLL_LOCKDET_DELAY);
1348 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1349 struct tegra_clk_pll_freq_table *cfg)
1351 u32 val, base, ndiv_new_mask;
1353 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1354 << PLLX_MISC2_NDIV_NEW_SHIFT;
1356 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1357 val &= (~ndiv_new_mask);
1358 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1359 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1362 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1363 val |= PLLX_MISC2_EN_DYNRAMP;
1364 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1367 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1368 PLLX_MISC2_DYNRAMP_DONE);
1370 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1371 (~divn_mask_shifted(pllx));
1372 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1373 writel_relaxed(base, clk_base + pllx->params->base_reg);
1376 val &= ~PLLX_MISC2_EN_DYNRAMP;
1377 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1380 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1381 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1382 cfg->input_rate / cfg->m * cfg->n /
1383 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1389 * Common configuration for PLLs with fixed input divider policy:
1390 * - always set fixed M-value based on the reference rate
1391 * - always set P-value value 1:1 for output rates above VCO minimum, and
1392 * choose minimum necessary P-value for output rates below VCO maximum
1393 * - calculate N-value based on selected M and P
1394 * - calculate SDM_DIN fractional part
1396 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1397 struct tegra_clk_pll_freq_table *cfg,
1398 unsigned long rate, unsigned long input_rate)
1400 struct tegra_clk_pll *pll = to_clk_pll(hw);
1401 struct tegra_clk_pll_params *params = pll->params;
1403 unsigned long cf, p_rate;
1409 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1410 p = DIV_ROUND_UP(params->vco_min, rate);
1411 p = params->round_p_to_pdiv(p, &pdiv);
1413 p = rate >= params->vco_min ? 1 : -EINVAL;
1419 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1422 /* Store P as HW value, as that is what is expected */
1423 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1426 if (p_rate > params->vco_max)
1427 p_rate = params->vco_max;
1428 cf = input_rate / cfg->m;
1429 cfg->n = p_rate / cf;
1432 cfg->output_rate = input_rate;
1433 if (params->sdm_ctrl_reg) {
1434 unsigned long rem = p_rate - cf * cfg->n;
1435 /* If ssc is enabled SDM enabled as well, even for integer n */
1436 if (rem || params->ssc_ctrl_reg) {
1437 u64 s = rem * PLL_SDM_COEFF;
1440 s -= PLL_SDM_COEFF / 2;
1441 cfg->sdm_data = sdin_din_to_data(s);
1443 cfg->output_rate *= sdin_get_n_eff(cfg);
1444 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1446 cfg->output_rate *= cfg->n;
1447 cfg->output_rate /= p * cfg->m;
1450 cfg->input_rate = input_rate;
1456 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1458 * @cfg: struct tegra_clk_pll_freq_table * cfg
1461 * Fvco = Fref * NDIV / MDIV
1463 * For fractional mode:
1464 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1466 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1468 cfg->n = sdin_get_n_eff(cfg);
1469 cfg->m *= PLL_SDM_COEFF;
1472 static unsigned long
1473 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1474 unsigned long parent_rate)
1476 unsigned long vco_min = params->vco_min;
1478 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1479 vco_min = min(vco_min, params->vco_min);
1484 static struct div_nmp pllx_nmp = {
1493 * PLL post divider maps - two types: quasi-linear and exponential
1496 #define PLL_QLIN_PDIV_MAX 16
1497 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1498 { .pdiv = 1, .hw_val = 0 },
1499 { .pdiv = 2, .hw_val = 1 },
1500 { .pdiv = 3, .hw_val = 2 },
1501 { .pdiv = 4, .hw_val = 3 },
1502 { .pdiv = 5, .hw_val = 4 },
1503 { .pdiv = 6, .hw_val = 5 },
1504 { .pdiv = 8, .hw_val = 6 },
1505 { .pdiv = 9, .hw_val = 7 },
1506 { .pdiv = 10, .hw_val = 8 },
1507 { .pdiv = 12, .hw_val = 9 },
1508 { .pdiv = 15, .hw_val = 10 },
1509 { .pdiv = 16, .hw_val = 11 },
1510 { .pdiv = 18, .hw_val = 12 },
1511 { .pdiv = 20, .hw_val = 13 },
1512 { .pdiv = 24, .hw_val = 14 },
1513 { .pdiv = 30, .hw_val = 15 },
1514 { .pdiv = 32, .hw_val = 16 },
1517 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1522 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1523 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1526 return pll_qlin_pdiv_to_hw[i].pdiv;
1534 #define PLL_EXPO_PDIV_MAX 7
1535 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1536 { .pdiv = 1, .hw_val = 0 },
1537 { .pdiv = 2, .hw_val = 1 },
1538 { .pdiv = 4, .hw_val = 2 },
1539 { .pdiv = 8, .hw_val = 3 },
1540 { .pdiv = 16, .hw_val = 4 },
1541 { .pdiv = 32, .hw_val = 5 },
1542 { .pdiv = 64, .hw_val = 6 },
1543 { .pdiv = 128, .hw_val = 7 },
1546 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1554 if (i <= PLL_EXPO_PDIV_MAX) {
1563 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1565 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1566 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1567 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1568 { 0, 0, 0, 0, 0, 0 },
1571 static struct tegra_clk_pll_params pll_x_params = {
1572 .input_min = 12000000,
1573 .input_max = 800000000,
1576 .vco_min = 1350000000,
1577 .vco_max = 3000000000UL,
1578 .base_reg = PLLX_BASE,
1579 .misc_reg = PLLX_MISC0,
1580 .lock_mask = PLL_BASE_LOCK,
1581 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1583 .ext_misc_reg[0] = PLLX_MISC0,
1584 .ext_misc_reg[1] = PLLX_MISC1,
1585 .ext_misc_reg[2] = PLLX_MISC2,
1586 .ext_misc_reg[3] = PLLX_MISC3,
1587 .ext_misc_reg[4] = PLLX_MISC4,
1588 .ext_misc_reg[5] = PLLX_MISC5,
1589 .iddq_reg = PLLX_MISC3,
1590 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1591 .max_p = PLL_QLIN_PDIV_MAX,
1593 .dyn_ramp_reg = PLLX_MISC2,
1596 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1597 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1598 .div_nmp = &pllx_nmp,
1599 .freq_table = pll_x_freq_table,
1600 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1601 .dyn_ramp = tegra210_pllx_dyn_ramp,
1602 .set_defaults = tegra210_pllx_set_defaults,
1603 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1606 static struct div_nmp pllc_nmp = {
1615 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1616 { 12000000, 510000000, 85, 1, 2, 0 },
1617 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1618 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1619 { 0, 0, 0, 0, 0, 0 },
1622 static struct tegra_clk_pll_params pll_c_params = {
1623 .input_min = 12000000,
1624 .input_max = 700000000,
1627 .vco_min = 600000000,
1628 .vco_max = 1200000000,
1629 .base_reg = PLLC_BASE,
1630 .misc_reg = PLLC_MISC0,
1631 .lock_mask = PLL_BASE_LOCK,
1633 .iddq_reg = PLLC_MISC1,
1634 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1635 .reset_reg = PLLC_MISC0,
1636 .reset_bit_idx = PLLCX_RESET_BIT,
1637 .max_p = PLL_QLIN_PDIV_MAX,
1638 .ext_misc_reg[0] = PLLC_MISC0,
1639 .ext_misc_reg[1] = PLLC_MISC1,
1640 .ext_misc_reg[2] = PLLC_MISC2,
1641 .ext_misc_reg[3] = PLLC_MISC3,
1642 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1643 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1645 .div_nmp = &pllc_nmp,
1646 .freq_table = pll_cx_freq_table,
1647 .flags = TEGRA_PLL_USE_LOCK,
1648 .set_defaults = _pllc_set_defaults,
1649 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1652 static struct div_nmp pllcx_nmp = {
1661 static struct tegra_clk_pll_params pll_c2_params = {
1662 .input_min = 12000000,
1663 .input_max = 700000000,
1666 .vco_min = 600000000,
1667 .vco_max = 1200000000,
1668 .base_reg = PLLC2_BASE,
1669 .misc_reg = PLLC2_MISC0,
1670 .iddq_reg = PLLC2_MISC1,
1671 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1672 .reset_reg = PLLC2_MISC0,
1673 .reset_bit_idx = PLLCX_RESET_BIT,
1674 .lock_mask = PLLCX_BASE_LOCK,
1676 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1677 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1679 .div_nmp = &pllcx_nmp,
1680 .max_p = PLL_QLIN_PDIV_MAX,
1681 .ext_misc_reg[0] = PLLC2_MISC0,
1682 .ext_misc_reg[1] = PLLC2_MISC1,
1683 .ext_misc_reg[2] = PLLC2_MISC2,
1684 .ext_misc_reg[3] = PLLC2_MISC3,
1685 .freq_table = pll_cx_freq_table,
1686 .flags = TEGRA_PLL_USE_LOCK,
1687 .set_defaults = _pllc2_set_defaults,
1688 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1691 static struct tegra_clk_pll_params pll_c3_params = {
1692 .input_min = 12000000,
1693 .input_max = 700000000,
1696 .vco_min = 600000000,
1697 .vco_max = 1200000000,
1698 .base_reg = PLLC3_BASE,
1699 .misc_reg = PLLC3_MISC0,
1700 .lock_mask = PLLCX_BASE_LOCK,
1702 .iddq_reg = PLLC3_MISC1,
1703 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1704 .reset_reg = PLLC3_MISC0,
1705 .reset_bit_idx = PLLCX_RESET_BIT,
1706 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1707 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1709 .div_nmp = &pllcx_nmp,
1710 .max_p = PLL_QLIN_PDIV_MAX,
1711 .ext_misc_reg[0] = PLLC3_MISC0,
1712 .ext_misc_reg[1] = PLLC3_MISC1,
1713 .ext_misc_reg[2] = PLLC3_MISC2,
1714 .ext_misc_reg[3] = PLLC3_MISC3,
1715 .freq_table = pll_cx_freq_table,
1716 .flags = TEGRA_PLL_USE_LOCK,
1717 .set_defaults = _pllc3_set_defaults,
1718 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1721 static struct div_nmp pllss_nmp = {
1730 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1731 { 12000000, 600000000, 50, 1, 1, 0 },
1732 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1733 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1734 { 0, 0, 0, 0, 0, 0 },
1737 static const struct clk_div_table pll_vco_post_div_table[] = {
1738 { .val = 0, .div = 1 },
1739 { .val = 1, .div = 2 },
1740 { .val = 2, .div = 3 },
1741 { .val = 3, .div = 4 },
1742 { .val = 4, .div = 5 },
1743 { .val = 5, .div = 6 },
1744 { .val = 6, .div = 8 },
1745 { .val = 7, .div = 10 },
1746 { .val = 8, .div = 12 },
1747 { .val = 9, .div = 16 },
1748 { .val = 10, .div = 12 },
1749 { .val = 11, .div = 16 },
1750 { .val = 12, .div = 20 },
1751 { .val = 13, .div = 24 },
1752 { .val = 14, .div = 32 },
1753 { .val = 0, .div = 0 },
1756 static struct tegra_clk_pll_params pll_c4_vco_params = {
1757 .input_min = 9600000,
1758 .input_max = 800000000,
1761 .vco_min = 500000000,
1762 .vco_max = 1080000000,
1763 .base_reg = PLLC4_BASE,
1764 .misc_reg = PLLC4_MISC0,
1765 .lock_mask = PLL_BASE_LOCK,
1767 .max_p = PLL_QLIN_PDIV_MAX,
1768 .ext_misc_reg[0] = PLLC4_MISC0,
1769 .iddq_reg = PLLC4_BASE,
1770 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1771 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1772 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1774 .div_nmp = &pllss_nmp,
1775 .freq_table = pll_c4_vco_freq_table,
1776 .set_defaults = tegra210_pllc4_set_defaults,
1777 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1778 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1781 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1782 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1783 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1784 { 38400000, 297600000, 93, 4, 3, 0 },
1785 { 38400000, 400000000, 125, 4, 3, 0 },
1786 { 38400000, 532800000, 111, 4, 2, 0 },
1787 { 38400000, 665600000, 104, 3, 2, 0 },
1788 { 38400000, 800000000, 125, 3, 2, 0 },
1789 { 38400000, 931200000, 97, 4, 1, 0 },
1790 { 38400000, 1065600000, 111, 4, 1, 0 },
1791 { 38400000, 1200000000, 125, 4, 1, 0 },
1792 { 38400000, 1331200000, 104, 3, 1, 0 },
1793 { 38400000, 1459200000, 76, 2, 1, 0 },
1794 { 38400000, 1600000000, 125, 3, 1, 0 },
1795 { 0, 0, 0, 0, 0, 0 },
1798 static struct div_nmp pllm_nmp = {
1801 .override_divm_shift = 0,
1804 .override_divn_shift = 8,
1807 .override_divp_shift = 27,
1810 static struct tegra_clk_pll_params pll_m_params = {
1811 .input_min = 9600000,
1812 .input_max = 500000000,
1815 .vco_min = 800000000,
1816 .vco_max = 1866000000,
1817 .base_reg = PLLM_BASE,
1818 .misc_reg = PLLM_MISC2,
1819 .lock_mask = PLL_BASE_LOCK,
1820 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1822 .iddq_reg = PLLM_MISC2,
1823 .iddq_bit_idx = PLLM_IDDQ_BIT,
1824 .max_p = PLL_QLIN_PDIV_MAX,
1825 .ext_misc_reg[0] = PLLM_MISC2,
1826 .ext_misc_reg[1] = PLLM_MISC1,
1827 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1828 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1829 .div_nmp = &pllm_nmp,
1830 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1831 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1832 .freq_table = pll_m_freq_table,
1833 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1834 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1837 static struct tegra_clk_pll_params pll_mb_params = {
1838 .input_min = 9600000,
1839 .input_max = 500000000,
1842 .vco_min = 800000000,
1843 .vco_max = 1866000000,
1844 .base_reg = PLLMB_BASE,
1845 .misc_reg = PLLMB_MISC1,
1846 .lock_mask = PLL_BASE_LOCK,
1848 .iddq_reg = PLLMB_MISC1,
1849 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1850 .max_p = PLL_QLIN_PDIV_MAX,
1851 .ext_misc_reg[0] = PLLMB_MISC1,
1852 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1853 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1854 .div_nmp = &pllm_nmp,
1855 .freq_table = pll_m_freq_table,
1856 .flags = TEGRA_PLL_USE_LOCK,
1857 .set_defaults = tegra210_pllmb_set_defaults,
1858 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1862 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1863 /* PLLE special case: use cpcon field to store cml divider value */
1864 { 672000000, 100000000, 125, 42, 0, 13 },
1865 { 624000000, 100000000, 125, 39, 0, 13 },
1866 { 336000000, 100000000, 125, 21, 0, 13 },
1867 { 312000000, 100000000, 200, 26, 0, 14 },
1868 { 38400000, 100000000, 125, 2, 0, 14 },
1869 { 12000000, 100000000, 200, 1, 0, 14 },
1870 { 0, 0, 0, 0, 0, 0 },
1873 static struct div_nmp plle_nmp = {
1882 static struct tegra_clk_pll_params pll_e_params = {
1883 .input_min = 12000000,
1884 .input_max = 800000000,
1887 .vco_min = 1600000000,
1888 .vco_max = 2500000000U,
1889 .base_reg = PLLE_BASE,
1890 .misc_reg = PLLE_MISC0,
1891 .aux_reg = PLLE_AUX,
1892 .lock_mask = PLLE_MISC_LOCK,
1893 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1895 .div_nmp = &plle_nmp,
1896 .freq_table = pll_e_freq_table,
1897 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1898 TEGRA_PLL_HAS_LOCK_ENABLE,
1899 .fixed_rate = 100000000,
1900 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1903 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1904 { 12000000, 672000000, 56, 1, 1, 0 },
1905 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1906 { 38400000, 672000000, 70, 4, 1, 0 },
1907 { 0, 0, 0, 0, 0, 0 },
1910 static struct div_nmp pllre_nmp = {
1919 static struct tegra_clk_pll_params pll_re_vco_params = {
1920 .input_min = 9600000,
1921 .input_max = 800000000,
1924 .vco_min = 350000000,
1925 .vco_max = 700000000,
1926 .base_reg = PLLRE_BASE,
1927 .misc_reg = PLLRE_MISC0,
1928 .lock_mask = PLLRE_MISC_LOCK,
1930 .max_p = PLL_QLIN_PDIV_MAX,
1931 .ext_misc_reg[0] = PLLRE_MISC0,
1932 .iddq_reg = PLLRE_MISC0,
1933 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1934 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1935 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1936 .div_nmp = &pllre_nmp,
1937 .freq_table = pll_re_vco_freq_table,
1938 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
1939 .set_defaults = tegra210_pllre_set_defaults,
1940 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1943 static struct div_nmp pllp_nmp = {
1952 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1953 { 12000000, 408000000, 34, 1, 1, 0 },
1954 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1955 { 0, 0, 0, 0, 0, 0 },
1958 static struct tegra_clk_pll_params pll_p_params = {
1959 .input_min = 9600000,
1960 .input_max = 800000000,
1963 .vco_min = 350000000,
1964 .vco_max = 700000000,
1965 .base_reg = PLLP_BASE,
1966 .misc_reg = PLLP_MISC0,
1967 .lock_mask = PLL_BASE_LOCK,
1969 .iddq_reg = PLLP_MISC0,
1970 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1971 .ext_misc_reg[0] = PLLP_MISC0,
1972 .ext_misc_reg[1] = PLLP_MISC1,
1973 .div_nmp = &pllp_nmp,
1974 .freq_table = pll_p_freq_table,
1975 .fixed_rate = 408000000,
1976 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1977 .set_defaults = tegra210_pllp_set_defaults,
1978 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1981 static struct tegra_clk_pll_params pll_a1_params = {
1982 .input_min = 12000000,
1983 .input_max = 700000000,
1986 .vco_min = 600000000,
1987 .vco_max = 1200000000,
1988 .base_reg = PLLA1_BASE,
1989 .misc_reg = PLLA1_MISC0,
1990 .lock_mask = PLLCX_BASE_LOCK,
1992 .iddq_reg = PLLA1_MISC1,
1993 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1994 .reset_reg = PLLA1_MISC0,
1995 .reset_bit_idx = PLLCX_RESET_BIT,
1996 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1997 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1998 .div_nmp = &pllc_nmp,
1999 .ext_misc_reg[0] = PLLA1_MISC0,
2000 .ext_misc_reg[1] = PLLA1_MISC1,
2001 .ext_misc_reg[2] = PLLA1_MISC2,
2002 .ext_misc_reg[3] = PLLA1_MISC3,
2003 .freq_table = pll_cx_freq_table,
2004 .flags = TEGRA_PLL_USE_LOCK,
2005 .set_defaults = _plla1_set_defaults,
2006 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2009 static struct div_nmp plla_nmp = {
2018 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
2019 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
2020 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
2021 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2022 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
2023 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
2024 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
2025 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
2026 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
2027 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2028 { 0, 0, 0, 0, 0, 0, 0 },
2031 static struct tegra_clk_pll_params pll_a_params = {
2032 .input_min = 12000000,
2033 .input_max = 800000000,
2036 .vco_min = 500000000,
2037 .vco_max = 1000000000,
2038 .base_reg = PLLA_BASE,
2039 .misc_reg = PLLA_MISC0,
2040 .lock_mask = PLL_BASE_LOCK,
2042 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2043 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2044 .iddq_reg = PLLA_BASE,
2045 .iddq_bit_idx = PLLA_IDDQ_BIT,
2046 .div_nmp = &plla_nmp,
2047 .sdm_din_reg = PLLA_MISC1,
2048 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2049 .sdm_ctrl_reg = PLLA_MISC2,
2050 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
2051 .ext_misc_reg[0] = PLLA_MISC0,
2052 .ext_misc_reg[1] = PLLA_MISC1,
2053 .ext_misc_reg[2] = PLLA_MISC2,
2054 .freq_table = pll_a_freq_table,
2055 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
2056 .set_defaults = tegra210_plla_set_defaults,
2057 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2058 .set_gain = tegra210_clk_pll_set_gain,
2059 .adjust_vco = tegra210_clk_adjust_vco_min,
2062 static struct div_nmp plld_nmp = {
2071 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
2072 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2073 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2074 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2075 { 0, 0, 0, 0, 0, 0, 0 },
2078 static struct tegra_clk_pll_params pll_d_params = {
2079 .input_min = 12000000,
2080 .input_max = 800000000,
2083 .vco_min = 750000000,
2084 .vco_max = 1500000000,
2085 .base_reg = PLLD_BASE,
2086 .misc_reg = PLLD_MISC0,
2087 .lock_mask = PLL_BASE_LOCK,
2089 .iddq_reg = PLLD_MISC0,
2090 .iddq_bit_idx = PLLD_IDDQ_BIT,
2091 .round_p_to_pdiv = pll_expo_p_to_pdiv,
2092 .pdiv_tohw = pll_expo_pdiv_to_hw,
2093 .div_nmp = &plld_nmp,
2094 .sdm_din_reg = PLLD_MISC0,
2095 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2096 .sdm_ctrl_reg = PLLD_MISC0,
2097 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
2098 .ext_misc_reg[0] = PLLD_MISC0,
2099 .ext_misc_reg[1] = PLLD_MISC1,
2100 .freq_table = pll_d_freq_table,
2101 .flags = TEGRA_PLL_USE_LOCK,
2103 .set_defaults = tegra210_plld_set_defaults,
2104 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2105 .set_gain = tegra210_clk_pll_set_gain,
2106 .adjust_vco = tegra210_clk_adjust_vco_min,
2109 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
2110 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2111 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2112 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2113 { 0, 0, 0, 0, 0, 0, 0 },
2116 /* s/w policy, always tegra_pll_ref */
2117 static struct tegra_clk_pll_params pll_d2_params = {
2118 .input_min = 12000000,
2119 .input_max = 800000000,
2122 .vco_min = 750000000,
2123 .vco_max = 1500000000,
2124 .base_reg = PLLD2_BASE,
2125 .misc_reg = PLLD2_MISC0,
2126 .lock_mask = PLL_BASE_LOCK,
2128 .iddq_reg = PLLD2_BASE,
2129 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2130 .sdm_din_reg = PLLD2_MISC3,
2131 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2132 .sdm_ctrl_reg = PLLD2_MISC1,
2133 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
2134 /* disable spread-spectrum for pll_d2 */
2136 .ssc_ctrl_en_mask = 0,
2137 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2138 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2139 .div_nmp = &pllss_nmp,
2140 .ext_misc_reg[0] = PLLD2_MISC0,
2141 .ext_misc_reg[1] = PLLD2_MISC1,
2142 .ext_misc_reg[2] = PLLD2_MISC2,
2143 .ext_misc_reg[3] = PLLD2_MISC3,
2144 .max_p = PLL_QLIN_PDIV_MAX,
2146 .freq_table = tegra210_pll_d2_freq_table,
2147 .set_defaults = tegra210_plld2_set_defaults,
2148 .flags = TEGRA_PLL_USE_LOCK,
2149 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2150 .set_gain = tegra210_clk_pll_set_gain,
2151 .adjust_vco = tegra210_clk_adjust_vco_min,
2154 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
2155 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2156 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
2157 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2158 { 0, 0, 0, 0, 0, 0, 0 },
2161 static struct tegra_clk_pll_params pll_dp_params = {
2162 .input_min = 12000000,
2163 .input_max = 800000000,
2166 .vco_min = 750000000,
2167 .vco_max = 1500000000,
2168 .base_reg = PLLDP_BASE,
2169 .misc_reg = PLLDP_MISC,
2170 .lock_mask = PLL_BASE_LOCK,
2172 .iddq_reg = PLLDP_BASE,
2173 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2174 .sdm_din_reg = PLLDP_SS_CTRL2,
2175 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2176 .sdm_ctrl_reg = PLLDP_SS_CFG,
2177 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
2178 .ssc_ctrl_reg = PLLDP_SS_CFG,
2179 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
2180 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2181 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2182 .div_nmp = &pllss_nmp,
2183 .ext_misc_reg[0] = PLLDP_MISC,
2184 .ext_misc_reg[1] = PLLDP_SS_CFG,
2185 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2186 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2187 .max_p = PLL_QLIN_PDIV_MAX,
2189 .freq_table = pll_dp_freq_table,
2190 .set_defaults = tegra210_plldp_set_defaults,
2191 .flags = TEGRA_PLL_USE_LOCK,
2192 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2193 .set_gain = tegra210_clk_pll_set_gain,
2194 .adjust_vco = tegra210_clk_adjust_vco_min,
2197 static struct div_nmp pllu_nmp = {
2206 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2207 { 12000000, 480000000, 40, 1, 0, 0 },
2208 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
2209 { 38400000, 480000000, 25, 2, 0, 0 },
2210 { 0, 0, 0, 0, 0, 0 },
2213 static struct tegra_clk_pll_params pll_u_vco_params = {
2214 .input_min = 9600000,
2215 .input_max = 800000000,
2218 .vco_min = 350000000,
2219 .vco_max = 700000000,
2220 .base_reg = PLLU_BASE,
2221 .misc_reg = PLLU_MISC0,
2222 .lock_mask = PLL_BASE_LOCK,
2224 .iddq_reg = PLLU_MISC0,
2225 .iddq_bit_idx = PLLU_IDDQ_BIT,
2226 .ext_misc_reg[0] = PLLU_MISC0,
2227 .ext_misc_reg[1] = PLLU_MISC1,
2228 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2229 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2230 .div_nmp = &pllu_nmp,
2231 .freq_table = pll_u_freq_table,
2232 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2235 struct utmi_clk_param {
2236 /* Oscillator Frequency in KHz */
2238 /* UTMIP PLL Enable Delay Count */
2239 u8 enable_delay_count;
2240 /* UTMIP PLL Stable count */
2242 /* UTMIP PLL Active delay count */
2243 u8 active_delay_count;
2244 /* UTMIP PLL Xtal frequency count */
2245 u16 xtal_freq_count;
2248 static const struct utmi_clk_param utmi_parameters[] = {
2250 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2251 .stable_count = 0x0, .active_delay_count = 0x6,
2252 .xtal_freq_count = 0x80
2254 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2255 .stable_count = 0x33, .active_delay_count = 0x05,
2256 .xtal_freq_count = 0x7f
2258 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2259 .stable_count = 0x4b, .active_delay_count = 0x06,
2260 .xtal_freq_count = 0xbb
2262 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2263 .stable_count = 0x2f, .active_delay_count = 0x08,
2264 .xtal_freq_count = 0x76
2266 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2267 .stable_count = 0x66, .active_delay_count = 0x09,
2268 .xtal_freq_count = 0xfe
2270 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2271 .stable_count = 0x41, .active_delay_count = 0x0a,
2272 .xtal_freq_count = 0xa4
2276 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2277 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2278 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2279 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2280 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2281 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2282 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2283 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2284 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2285 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2286 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2287 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2288 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2289 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2290 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2291 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2292 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2293 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2294 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2295 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2296 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2297 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2298 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2299 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2300 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2301 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2302 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2303 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2304 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2305 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2306 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2307 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2308 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2309 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2310 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2311 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2312 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2313 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2314 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2315 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2316 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2317 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2318 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2319 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2320 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2321 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2322 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2323 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2324 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2325 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2326 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2327 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2328 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2329 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2330 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2331 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2332 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2333 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2334 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2335 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2336 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2337 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2338 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2339 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2340 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2341 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2342 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2343 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2344 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2345 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2346 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2347 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2348 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2349 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2350 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2351 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
2352 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2353 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2354 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2355 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2356 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2357 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2358 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2359 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2360 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2361 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2362 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2363 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2364 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2365 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2366 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2367 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2368 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2369 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2370 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2371 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2372 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2373 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2374 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2375 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2376 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2377 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2378 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2379 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2380 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2381 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2382 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2383 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2384 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2385 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2386 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2387 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2388 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2389 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2390 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2391 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2392 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2393 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2394 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2395 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2396 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2397 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2398 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2399 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2400 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2401 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2402 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2403 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2404 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2405 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2406 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2407 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2408 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2409 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2410 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2411 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2412 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
2413 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2414 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2415 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2416 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2417 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2418 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2419 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2420 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2421 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2422 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2423 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2424 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2425 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2426 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2427 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2428 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2429 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2430 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2431 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2432 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2433 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2434 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2435 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2436 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2437 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2438 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2439 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2440 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2441 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2442 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2443 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2444 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2445 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2446 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
2447 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2448 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2449 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2450 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2451 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2452 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2453 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2454 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2455 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2456 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2457 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2458 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2459 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2460 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2461 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2462 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2463 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2464 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2465 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2466 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2467 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2468 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2469 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2470 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2471 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2472 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2473 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2474 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2475 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2476 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2477 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2478 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2479 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2480 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2481 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2482 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2485 static struct tegra_devclk devclks[] __initdata = {
2486 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2487 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2488 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2489 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2490 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2491 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2492 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2493 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2494 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2495 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2496 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2497 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2498 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2499 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2500 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2501 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2502 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2503 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2504 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2505 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2506 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2507 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2508 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2509 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2510 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2511 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2512 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2513 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2514 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2515 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2516 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2517 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2518 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2519 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2520 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2521 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2522 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2523 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2524 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2525 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2526 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2527 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2528 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2529 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2530 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2531 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2532 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2533 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2534 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2535 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2536 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2537 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2538 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2539 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2540 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2541 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2542 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2543 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2544 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2545 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2546 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2547 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2548 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2549 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 },
2552 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2553 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2554 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2557 static const char * const aclk_parents[] = {
2558 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2562 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
2563 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
2564 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
2565 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
2566 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
2567 TEGRA210_CLK_HOST1X};
2568 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2569 TEGRA210_CLK_XUSB_DEV };
2570 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2571 TEGRA210_CLK_XUSB_SS };
2572 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
2573 TEGRA210_CLK_XUSB_SS };
2574 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
2575 TEGRA210_CLK_PLL_D };
2576 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
2577 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
2578 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
2579 TEGRA210_CLK_D_AUDIO };
2580 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
2582 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
2583 [TEGRA_POWERGATE_VENC] = {
2584 .handle_lvl2_ovr = tegra210_venc_mbist_war,
2585 .num_clks = ARRAY_SIZE(venc_slcg_clkids),
2586 .clk_init_data = venc_slcg_clkids,
2588 [TEGRA_POWERGATE_SATA] = {
2589 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2590 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2591 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2593 [TEGRA_POWERGATE_MPE] = {
2594 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2595 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2596 .lvl2_mask = BIT(29),
2598 [TEGRA_POWERGATE_SOR] = {
2599 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2600 .num_clks = ARRAY_SIZE(sor_slcg_clkids),
2601 .clk_init_data = sor_slcg_clkids,
2602 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2603 .lvl2_mask = BIT(1) | BIT(2),
2605 [TEGRA_POWERGATE_DIS] = {
2606 .handle_lvl2_ovr = tegra210_disp_mbist_war,
2607 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2608 .clk_init_data = disp_slcg_clkids,
2610 [TEGRA_POWERGATE_DISB] = {
2611 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2612 .clk_init_data = disp_slcg_clkids,
2613 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2614 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2615 .lvl2_mask = BIT(2),
2617 [TEGRA_POWERGATE_XUSBA] = {
2618 .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
2619 .clk_init_data = xusba_slcg_clkids,
2620 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2621 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2622 .lvl2_mask = BIT(30) | BIT(31),
2624 [TEGRA_POWERGATE_XUSBB] = {
2625 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
2626 .clk_init_data = xusbb_slcg_clkids,
2627 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2628 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2629 .lvl2_mask = BIT(30) | BIT(31),
2631 [TEGRA_POWERGATE_XUSBC] = {
2632 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
2633 .clk_init_data = xusbc_slcg_clkids,
2634 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2635 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2636 .lvl2_mask = BIT(30) | BIT(31),
2638 [TEGRA_POWERGATE_VIC] = {
2639 .num_clks = ARRAY_SIZE(vic_slcg_clkids),
2640 .clk_init_data = vic_slcg_clkids,
2641 .handle_lvl2_ovr = tegra210_vic_mbist_war,
2643 [TEGRA_POWERGATE_NVDEC] = {
2644 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
2645 .clk_init_data = nvdec_slcg_clkids,
2646 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2647 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2648 .lvl2_mask = BIT(9) | BIT(31),
2650 [TEGRA_POWERGATE_NVJPG] = {
2651 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
2652 .clk_init_data = nvjpg_slcg_clkids,
2653 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2654 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2655 .lvl2_mask = BIT(9) | BIT(31),
2657 [TEGRA_POWERGATE_AUD] = {
2658 .num_clks = ARRAY_SIZE(ape_slcg_clkids),
2659 .clk_init_data = ape_slcg_clkids,
2660 .handle_lvl2_ovr = tegra210_ape_mbist_war,
2662 [TEGRA_POWERGATE_VE2] = {
2663 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2664 .lvl2_offset = LVL2_CLK_GATE_OVRD,
2665 .lvl2_mask = BIT(22),
2669 int tegra210_clk_handle_mbist_war(unsigned int id)
2672 struct tegra210_domain_mbist_war *mbist_war;
2674 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
2675 WARN(1, "unknown domain id in MBIST WAR handler\n");
2679 mbist_war = &tegra210_pg_mbist_war[id];
2680 if (!mbist_war->handle_lvl2_ovr)
2683 if (mbist_war->num_clks && !mbist_war->clks)
2686 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
2690 mutex_lock(&lvl2_ovr_lock);
2692 mbist_war->handle_lvl2_ovr(mbist_war);
2694 mutex_unlock(&lvl2_ovr_lock);
2696 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
2701 void tegra210_put_utmipll_in_iddq(void)
2705 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2707 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2708 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2712 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2713 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2715 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2717 void tegra210_put_utmipll_out_iddq(void)
2721 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2722 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2723 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2725 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2727 static void tegra210_utmi_param_configure(void)
2732 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2733 if (osc_freq == utmi_parameters[i].osc_frequency)
2737 if (i >= ARRAY_SIZE(utmi_parameters)) {
2738 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2743 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2744 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2745 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2749 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2751 /* Program UTMIP PLL stable and active counts */
2752 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2753 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2754 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2756 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2758 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2759 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2761 /* Program UTMIP PLL delay and oscillator frequency counts */
2762 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2764 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2766 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2768 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2770 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2772 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2773 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2775 /* Remove power downs from UTMIP PLL control bits */
2776 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2777 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2778 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2779 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2783 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2784 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2785 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2786 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2787 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2788 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2789 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2790 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2791 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2793 /* Setup HW control of UTMIPLL */
2794 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2795 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2796 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2797 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2799 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2800 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2801 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2802 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2806 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2807 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2808 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2812 /* Enable HW control UTMIPLL */
2813 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2814 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2815 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2818 static int tegra210_enable_pllu(void)
2820 struct tegra_clk_pll_freq_table *fentry;
2821 struct tegra_clk_pll pllu;
2824 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2825 if (fentry->input_rate == pll_ref_freq)
2829 if (!fentry->input_rate) {
2830 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2834 /* clear IDDQ bit */
2835 pllu.params = &pll_u_vco_params;
2836 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2837 reg &= ~BIT(pllu.params->iddq_bit_idx);
2838 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2841 reg = readl_relaxed(clk_base + PLLU_BASE);
2842 reg &= ~GENMASK(20, 0);
2844 reg |= fentry->n << 8;
2845 reg |= fentry->p << 16;
2846 writel(reg, clk_base + PLLU_BASE);
2849 writel(reg, clk_base + PLLU_BASE);
2851 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
2852 reg & PLL_BASE_LOCK, 2, 1000);
2853 if (!(reg & PLL_BASE_LOCK)) {
2854 pr_err("Timed out waiting for PLL_U to lock\n");
2861 static int tegra210_init_pllu(void)
2866 tegra210_pllu_set_defaults(&pll_u_vco_params);
2867 /* skip initialization when pllu is in hw controlled mode */
2868 reg = readl_relaxed(clk_base + PLLU_BASE);
2869 if (reg & PLLU_BASE_OVERRIDE) {
2870 if (!(reg & PLL_ENABLE)) {
2871 err = tegra210_enable_pllu();
2877 /* enable hw controlled mode */
2878 reg = readl_relaxed(clk_base + PLLU_BASE);
2879 reg &= ~PLLU_BASE_OVERRIDE;
2880 writel(reg, clk_base + PLLU_BASE);
2882 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2883 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2884 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2885 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2886 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2887 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2888 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2890 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2891 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2892 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2895 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2896 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2897 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2900 reg = readl_relaxed(clk_base + PLLU_BASE);
2901 reg &= ~PLLU_BASE_CLKENABLE_USB;
2902 writel_relaxed(reg, clk_base + PLLU_BASE);
2905 /* enable UTMIPLL hw control if not yet done by the bootloader */
2906 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2907 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2908 tegra210_utmi_param_configure();
2913 static const char * const sor1_out_parents[] = {
2915 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
2916 * the sor1_pad_clkout parent appears twice in the list below. This is
2917 * merely to support clk_get_parent() if firmware happened to set
2918 * these bits to 0b11. While not an invalid setting, code should
2919 * always set the bits to 0b01 to select sor1_pad_clkout.
2921 "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout",
2924 static const char * const sor1_parents[] = {
2925 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
2928 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2930 static struct tegra_periph_init_data tegra210_periph[] = {
2931 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
2932 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
2933 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,
2934 sor1_parents_idx, 0, &sor1_lock),
2937 static const char * const la_parents[] = {
2938 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
2941 static struct tegra_clk_periph tegra210_la =
2942 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
2944 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2945 void __iomem *pmc_base)
2951 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2953 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2955 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2957 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2959 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
2961 clks[TEGRA210_CLK_DPAUX] = clk;
2963 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
2965 clks[TEGRA210_CLK_DPAUX1] = clk;
2967 clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents,
2968 ARRAY_SIZE(sor1_out_parents), 0,
2969 clk_base + CLK_SOURCE_SOR1, 14, 0x3,
2970 0, NULL, &sor1_lock);
2971 clks[TEGRA210_CLK_SOR1_OUT] = clk;
2974 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2975 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
2976 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
2979 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2981 periph_clk_enb_refcnt);
2982 clks[TEGRA210_CLK_DSIA] = clk;
2985 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2987 periph_clk_enb_refcnt);
2988 clks[TEGRA210_CLK_DSIB] = clk;
2991 clk = tegra_clk_register_periph("la", la_parents,
2992 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
2994 clks[TEGRA210_CLK_LA] = clk;
2997 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2998 ARRAY_SIZE(mux_pllmcp_clkm), 0,
2999 clk_base + CLK_SOURCE_EMC,
3000 29, 3, 0, &emc_lock);
3002 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
3004 clks[TEGRA210_CLK_MC] = clk;
3007 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3009 clk_register_clkdev(clk, "cml0", NULL);
3010 clks[TEGRA210_CLK_CML0] = clk;
3013 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3015 clk_register_clkdev(clk, "cml1", NULL);
3016 clks[TEGRA210_CLK_CML1] = clk;
3018 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3019 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3021 clks[TEGRA210_CLK_ACLK] = clk;
3023 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3024 CLK_SOURCE_SDMMC2, 9,
3025 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3026 clks[TEGRA210_CLK_SDMMC2] = clk;
3028 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3029 CLK_SOURCE_SDMMC4, 15,
3030 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3031 clks[TEGRA210_CLK_SDMMC4] = clk;
3033 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
3034 struct tegra_periph_init_data *init = &tegra210_periph[i];
3037 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
3039 pr_warn("clock %u not found\n", init->clk_id);
3043 clk = tegra_clk_register_periph_data(clk_base, init);
3047 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3050 static void __init tegra210_pll_init(void __iomem *clk_base,
3056 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3057 pmc, 0, &pll_c_params, NULL);
3058 if (!WARN_ON(IS_ERR(clk)))
3059 clk_register_clkdev(clk, "pll_c", NULL);
3060 clks[TEGRA210_CLK_PLL_C] = clk;
3063 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3064 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3066 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3067 clk_base + PLLC_OUT, 1, 0,
3068 CLK_SET_RATE_PARENT, 0, NULL);
3069 clk_register_clkdev(clk, "pll_c_out1", NULL);
3070 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3073 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3074 CLK_SET_RATE_PARENT, 1, 1);
3075 clk_register_clkdev(clk, "pll_c_ud", NULL);
3076 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3079 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3080 pmc, 0, &pll_c2_params, NULL);
3081 clk_register_clkdev(clk, "pll_c2", NULL);
3082 clks[TEGRA210_CLK_PLL_C2] = clk;
3085 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3086 pmc, 0, &pll_c3_params, NULL);
3087 clk_register_clkdev(clk, "pll_c3", NULL);
3088 clks[TEGRA210_CLK_PLL_C3] = clk;
3091 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3092 CLK_SET_RATE_GATE, &pll_m_params, NULL);
3093 clk_register_clkdev(clk, "pll_m", NULL);
3094 clks[TEGRA210_CLK_PLL_M] = clk;
3097 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3098 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
3099 clk_register_clkdev(clk, "pll_mb", NULL);
3100 clks[TEGRA210_CLK_PLL_MB] = clk;
3103 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3104 CLK_SET_RATE_PARENT, 1, 1);
3105 clk_register_clkdev(clk, "pll_m_ud", NULL);
3106 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3109 if (!tegra210_init_pllu()) {
3110 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3112 clk_register_clkdev(clk, "pll_u_vco", NULL);
3113 clks[TEGRA210_CLK_PLL_U] = clk;
3117 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3118 clk_base + PLLU_BASE, 16, 4, 0,
3119 pll_vco_post_div_table, NULL);
3120 clk_register_clkdev(clk, "pll_u_out", NULL);
3121 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3124 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3125 clk_base + PLLU_OUTA, 0,
3126 TEGRA_DIVIDER_ROUND_UP,
3127 8, 8, 1, &pll_u_lock);
3128 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3129 clk_base + PLLU_OUTA, 1, 0,
3130 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3131 clk_register_clkdev(clk, "pll_u_out1", NULL);
3132 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3135 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3136 clk_base + PLLU_OUTA, 0,
3137 TEGRA_DIVIDER_ROUND_UP,
3138 24, 8, 1, &pll_u_lock);
3139 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3140 clk_base + PLLU_OUTA, 17, 16,
3141 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3142 clk_register_clkdev(clk, "pll_u_out2", NULL);
3143 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3146 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3147 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3148 22, 0, &pll_u_lock);
3149 clk_register_clkdev(clk, "pll_u_480M", NULL);
3150 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3153 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3154 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3155 23, 0, &pll_u_lock);
3156 clk_register_clkdev(clk, "pll_u_60M", NULL);
3157 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3160 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3161 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3162 25, 0, &pll_u_lock);
3163 clk_register_clkdev(clk, "pll_u_48M", NULL);
3164 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3167 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3168 &pll_d_params, &pll_d_lock);
3169 clk_register_clkdev(clk, "pll_d", NULL);
3170 clks[TEGRA210_CLK_PLL_D] = clk;
3173 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3174 CLK_SET_RATE_PARENT, 1, 2);
3175 clk_register_clkdev(clk, "pll_d_out0", NULL);
3176 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3179 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3182 &pll_re_lock, pll_ref_freq);
3183 clk_register_clkdev(clk, "pll_re_vco", NULL);
3184 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3186 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3187 clk_base + PLLRE_BASE, 16, 5, 0,
3188 pll_vco_post_div_table, &pll_re_lock);
3189 clk_register_clkdev(clk, "pll_re_out", NULL);
3190 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3192 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3193 clk_base + PLLRE_OUT1, 0,
3194 TEGRA_DIVIDER_ROUND_UP,
3196 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3197 clk_base + PLLRE_OUT1, 1, 0,
3198 CLK_SET_RATE_PARENT, 0, NULL);
3199 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3202 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3203 clk_base, 0, &pll_e_params, NULL);
3204 clk_register_clkdev(clk, "pll_e", NULL);
3205 clks[TEGRA210_CLK_PLL_E] = clk;
3208 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3209 0, &pll_c4_vco_params, NULL, pll_ref_freq);
3210 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3211 clks[TEGRA210_CLK_PLL_C4] = clk;
3214 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3215 clk_base + PLLC4_BASE, 19, 4, 0,
3216 pll_vco_post_div_table, NULL);
3217 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3218 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3221 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3222 CLK_SET_RATE_PARENT, 1, 3);
3223 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3224 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3227 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3228 CLK_SET_RATE_PARENT, 1, 5);
3229 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3230 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3233 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3234 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3236 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3237 clk_base + PLLC4_OUT, 1, 0,
3238 CLK_SET_RATE_PARENT, 0, NULL);
3239 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3240 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3243 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3244 0, &pll_dp_params, NULL);
3245 clk_register_clkdev(clk, "pll_dp", NULL);
3246 clks[TEGRA210_CLK_PLL_DP] = clk;
3249 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3250 0, &pll_d2_params, NULL);
3251 clk_register_clkdev(clk, "pll_d2", NULL);
3252 clks[TEGRA210_CLK_PLL_D2] = clk;
3255 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3256 CLK_SET_RATE_PARENT, 1, 1);
3257 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3258 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3261 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3262 CLK_SET_RATE_PARENT, 1, 2);
3263 clk_register_clkdev(clk, "pll_p_out2", NULL);
3264 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3268 /* Tegra210 CPU clock and reset control functions */
3269 static void tegra210_wait_cpu_in_reset(u32 cpu)
3274 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3276 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
3279 static void tegra210_disable_cpu_clock(u32 cpu)
3281 /* flow controller would take care in the power sequence. */
3284 #ifdef CONFIG_PM_SLEEP
3285 static void tegra210_cpu_clock_suspend(void)
3287 /* switch coresite to clk_m, save off original source */
3288 tegra210_cpu_clk_sctx.clk_csite_src =
3289 readl(clk_base + CLK_SOURCE_CSITE);
3290 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3293 static void tegra210_cpu_clock_resume(void)
3295 writel(tegra210_cpu_clk_sctx.clk_csite_src,
3296 clk_base + CLK_SOURCE_CSITE);
3300 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
3301 .wait_for_reset = tegra210_wait_cpu_in_reset,
3302 .disable_clock = tegra210_disable_cpu_clock,
3303 #ifdef CONFIG_PM_SLEEP
3304 .suspend = tegra210_cpu_clock_suspend,
3305 .resume = tegra210_cpu_clock_resume,
3309 static const struct of_device_id pmc_match[] __initconst = {
3310 { .compatible = "nvidia,tegra210-pmc" },
3314 static struct tegra_clk_init_table init_table[] __initdata = {
3315 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3316 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3317 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3318 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3319 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
3320 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
3321 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
3322 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
3323 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
3324 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3325 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3326 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3327 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3328 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3329 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3330 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3331 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3332 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3333 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3334 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3335 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
3336 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3337 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3338 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3339 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3340 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3341 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3342 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3343 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3344 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3345 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3346 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3347 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3348 /* TODO find a way to enable this on-demand */
3349 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3350 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3351 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3352 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3353 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3354 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3355 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3356 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3357 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3358 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3359 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3360 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3361 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3362 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3363 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3364 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3365 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3366 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3367 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3368 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3369 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3370 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3371 /* This MUST be the last entry. */
3372 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3376 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3378 * Program an initial clock rate and enable or disable clocks needed
3379 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
3380 * called by assigning a pointer to it to tegra_clk_apply_init_table -
3381 * this will be called as an arch_initcall. No return value.
3383 static void __init tegra210_clock_apply_init_table(void)
3385 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
3389 * tegra210_car_barrier - wait for pending writes to the CAR to complete
3391 * Wait for any outstanding writes to the CAR MMIO space from this CPU
3392 * to complete before continuing execution. No return value.
3394 static void tegra210_car_barrier(void)
3396 readl_relaxed(clk_base + RST_DFLL_DVCO);
3400 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3402 * Assert the reset line of the DFLL's DVCO. No return value.
3404 static void tegra210_clock_assert_dfll_dvco_reset(void)
3408 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3409 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3410 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3411 tegra210_car_barrier();
3415 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3417 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
3418 * operate. No return value.
3420 static void tegra210_clock_deassert_dfll_dvco_reset(void)
3424 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3425 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3426 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3427 tegra210_car_barrier();
3430 static int tegra210_reset_assert(unsigned long id)
3432 if (id == TEGRA210_RST_DFLL_DVCO)
3433 tegra210_clock_assert_dfll_dvco_reset();
3434 else if (id == TEGRA210_RST_ADSP)
3435 writel(GENMASK(26, 21) | BIT(7),
3436 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3443 static int tegra210_reset_deassert(unsigned long id)
3445 if (id == TEGRA210_RST_DFLL_DVCO)
3446 tegra210_clock_deassert_dfll_dvco_reset();
3447 else if (id == TEGRA210_RST_ADSP) {
3448 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3450 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
3451 * a delay of 5us ensures that it's at least
3452 * 6 * adsp_cpu_cycle_period long.
3455 writel(GENMASK(26, 22) | BIT(7),
3456 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3463 static void tegra210_mbist_clk_init(void)
3467 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
3468 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
3469 struct clk_bulk_data *clk_data;
3474 clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
3476 if (WARN_ON(!clk_data))
3479 tegra210_pg_mbist_war[i].clks = clk_data;
3480 for (j = 0; j < num_clks; j++) {
3481 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
3482 struct clk *clk = clks[clk_id];
3484 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3486 tegra210_pg_mbist_war[i].clks = NULL;
3489 clk_data[j].clk = clk;
3495 * tegra210_clock_init - Tegra210-specific clock initialization
3496 * @np: struct device_node * of the DT node for the SoC CAR IP block
3498 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
3499 * to be called by the OF init code when a DT node with the
3500 * "nvidia,tegra210-car" string is encountered, and declared with
3501 * CLK_OF_DECLARE. No return value.
3503 static void __init tegra210_clock_init(struct device_node *np)
3505 struct device_node *node;
3506 u32 value, clk_m_div;
3508 clk_base = of_iomap(np, 0);
3510 pr_err("ioremap tegra210 CAR failed\n");
3514 node = of_find_matching_node(NULL, pmc_match);
3516 pr_err("Failed to find pmc node\n");
3521 pmc_base = of_iomap(node, 0);
3523 pr_err("Can't map pmc registers\n");
3528 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
3530 pr_err("ioremap tegra210 APE failed\n");
3534 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
3536 pr_err("ioremap tegra210 DISPA failed\n");
3540 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
3542 pr_err("ioremap tegra210 VIC failed\n");
3546 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3547 TEGRA210_CAR_BANK_COUNT);
3551 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3552 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3554 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3555 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
3556 &osc_freq, &pll_ref_freq) < 0)
3559 tegra_fixed_clk_init(tegra210_clks);
3560 tegra210_pll_init(clk_base, pmc_base);
3561 tegra210_periph_clk_init(clk_base, pmc_base);
3562 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3563 tegra210_audio_plls,
3564 ARRAY_SIZE(tegra210_audio_plls), 24576000);
3565 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3567 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3568 value = readl(clk_base + PLLD_BASE);
3570 writel(value, clk_base + PLLD_BASE);
3572 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3574 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
3576 tegra_init_special_resets(2, tegra210_reset_assert,
3577 tegra210_reset_deassert);
3579 tegra_add_of_provider(np, of_clk_src_onecell_get);
3580 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3582 tegra210_mbist_clk_init();
3584 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
3586 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);