drivers/clk/ti/adpll.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License as
   4  * published by the Free Software Foundation version 2.
   5  *
   6  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   7  * kind, whether express or implied; without even the implied warranty
   8  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
   9  * GNU General Public License for more details.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/math64.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/string.h>
  22
  23 #define ADPLL_PLLSS_MMR_LOCK_OFFSET     0x00    /* Managed by MPPULL */
  24 #define ADPLL_PLLSS_MMR_LOCK_ENABLED    0x1f125B64
  25 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC    0x1eda4c3d
  26
  27 #define ADPLL_PWRCTRL_OFFSET            0x00
  28 #define ADPLL_PWRCTRL_PONIN             5
  29 #define ADPLL_PWRCTRL_PGOODIN           4
  30 #define ADPLL_PWRCTRL_RET               3
  31 #define ADPLL_PWRCTRL_ISORET            2
  32 #define ADPLL_PWRCTRL_ISOSCAN           1
  33 #define ADPLL_PWRCTRL_OFFMODE           0
  34
  35 #define ADPLL_CLKCTRL_OFFSET            0x04
  36 #define ADPLL_CLKCTRL_CLKDCOLDOEN       29
  37 #define ADPLL_CLKCTRL_IDLE              23
  38 #define ADPLL_CLKCTRL_CLKOUTEN          20
  39 #define ADPLL_CLKINPHIFSEL_ADPLL_S      19      /* REVISIT: which bit? */
  40 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
  41 #define ADPLL_CLKCTRL_ULOWCLKEN         18
  42 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ    17
  43 #define ADPLL_CLKCTRL_M2PWDNZ           16
  44 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S   15
  45 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
  46 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S    12
  47 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S  10
  48 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
  49 #define ADPLL_CLKCTRL_TINITZ            0
  50
  51 #define ADPLL_TENABLE_OFFSET            0x08
  52 #define ADPLL_TENABLEDIV_OFFSET         0x8c
  53
  54 #define ADPLL_M2NDIV_OFFSET             0x10
  55 #define ADPLL_M2NDIV_M2                 16
  56 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH   5
  57 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH  7
  58
  59 #define ADPLL_MN2DIV_OFFSET             0x14
  60 #define ADPLL_MN2DIV_N2                 16
  61
  62 #define ADPLL_FRACDIV_OFFSET            0x18
  63 #define ADPLL_FRACDIV_REGSD             24
  64 #define ADPLL_FRACDIV_FRACTIONALM       0
  65 #define ADPLL_FRACDIV_FRACTIONALM_MASK  0x3ffff
  66
  67 #define ADPLL_BWCTRL_OFFSET             0x1c
  68 #define ADPLL_BWCTRL_BWCONTROL          1
  69 #define ADPLL_BWCTRL_BW_INCR_DECRZ      0
  70
  71 #define ADPLL_RESERVED_OFFSET           0x20
  72
  73 #define ADPLL_STATUS_OFFSET             0x24
  74 #define ADPLL_STATUS_PONOUT             31
  75 #define ADPLL_STATUS_PGOODOUT           30
  76 #define ADPLL_STATUS_LDOPWDN            29
  77 #define ADPLL_STATUS_RECAL_BSTATUS3     28
  78 #define ADPLL_STATUS_RECAL_OPPIN        27
  79 #define ADPLL_STATUS_PHASELOCK          10
  80 #define ADPLL_STATUS_FREQLOCK           9
  81 #define ADPLL_STATUS_BYPASSACK          8
  82 #define ADPLL_STATUS_LOSSREF            6
  83 #define ADPLL_STATUS_CLKOUTENACK        5
  84 #define ADPLL_STATUS_LOCK2              4
  85 #define ADPLL_STATUS_M2CHANGEACK        3
  86 #define ADPLL_STATUS_HIGHJITTER         1
  87 #define ADPLL_STATUS_BYPASS             0
  88 #define ADPLL_STATUS_PREPARED_MASK      (BIT(ADPLL_STATUS_PHASELOCK) | \
  89                                          BIT(ADPLL_STATUS_FREQLOCK))
  90
  91 #define ADPLL_M3DIV_OFFSET              0x28    /* Only on MPUPLL */
  92 #define ADPLL_M3DIV_M3                  0
  93 #define ADPLL_M3DIV_M3_WIDTH            5
  94 #define ADPLL_M3DIV_M3_MASK             0x1f
  95
  96 #define ADPLL_RAMPCTRL_OFFSET           0x2c    /* Only on MPUPLL */
  97 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL     19
  98 #define ADPLL_RAMPCTRL_CLKRAMPRATE      16
  99 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN   0
 100
 101 #define MAX_ADPLL_INPUTS                3
 102 #define MAX_ADPLL_OUTPUTS               4
 103 #define ADPLL_MAX_RETRIES               5
 104
 105 #define to_dco(_hw)     container_of(_hw, struct ti_adpll_dco_data, hw)
 106 #define to_adpll(_hw)   container_of(_hw, struct ti_adpll_data, dco)
 107 #define to_clkout(_hw)  container_of(_hw, struct ti_adpll_clkout_data, hw)
 108
 109 enum ti_adpll_clocks {
 110         TI_ADPLL_DCO,
 111         TI_ADPLL_DCO_GATE,
 112         TI_ADPLL_N2,
 113         TI_ADPLL_M2,
 114         TI_ADPLL_M2_GATE,
 115         TI_ADPLL_BYPASS,
 116         TI_ADPLL_HIF,
 117         TI_ADPLL_DIV2,
 118         TI_ADPLL_CLKOUT,
 119         TI_ADPLL_CLKOUT2,
 120         TI_ADPLL_M3,
 121 };
 122
 123 #define TI_ADPLL_NR_CLOCKS      (TI_ADPLL_M3 + 1)
 124
 125 enum ti_adpll_inputs {
 126         TI_ADPLL_CLKINP,
 127         TI_ADPLL_CLKINPULOW,
 128         TI_ADPLL_CLKINPHIF,
 129 };
 130
 131 enum ti_adpll_s_outputs {
 132         TI_ADPLL_S_DCOCLKLDO,
 133         TI_ADPLL_S_CLKOUT,
 134         TI_ADPLL_S_CLKOUTX2,
 135         TI_ADPLL_S_CLKOUTHIF,
 136 };
 137
 138 enum ti_adpll_lj_outputs {
 139         TI_ADPLL_LJ_CLKDCOLDO,
 140         TI_ADPLL_LJ_CLKOUT,
 141         TI_ADPLL_LJ_CLKOUTLDO,
 142 };
 143
 144 struct ti_adpll_platform_data {
 145         const bool is_type_s;
 146         const int nr_max_inputs;
 147         const int nr_max_outputs;
 148         const int output_index;
 149 };
 150
 151 struct ti_adpll_clock {
 152         struct clk *clk;
 153         struct clk_lookup *cl;
 154         void (*unregister)(struct clk *clk);
 155 };
 156
 157 struct ti_adpll_dco_data {
 158         struct clk_hw hw;
 159 };
 160
 161 struct ti_adpll_clkout_data {
 162         struct ti_adpll_data *adpll;
 163         struct clk_gate gate;
 164         struct clk_hw hw;
 165 };
 166
 167 struct ti_adpll_data {
 168         struct device *dev;
 169         const struct ti_adpll_platform_data *c;
 170         struct device_node *np;
 171         unsigned long pa;
 172         void __iomem *iobase;
 173         void __iomem *regs;
 174         spinlock_t lock;        /* For ADPLL shared register access */
 175         const char *parent_names[MAX_ADPLL_INPUTS];
 176         struct clk *parent_clocks[MAX_ADPLL_INPUTS];
 177         struct ti_adpll_clock *clocks;
 178         struct clk_onecell_data outputs;
 179         struct ti_adpll_dco_data dco;
 180 };
 181
 182 static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
 183                                          int output_index,
 184                                          const char *postfix)
 185 {
 186         const char *name;
 187         int err;
 188
 189         if (output_index >= 0) {
 190                 err = of_property_read_string_index(d->np,
 191                                                     "clock-output-names",
 192                                                     output_index,
 193                                                     &name);
 194                 if (err)
 195                         return NULL;
 196         } else {
 197                 const char *base_name = "adpll";
 198                 char *buf;
 199
 200                 buf = devm_kzalloc(d->dev, 8 + 1 + strlen(base_name) + 1 +
 201                                     strlen(postfix), GFP_KERNEL);
 202                 if (!buf)
 203                         return NULL;
 204                 sprintf(buf, "%08lx.%s.%s", d->pa, base_name, postfix);
 205                 name = buf;
 206         }
 207
 208         return name;
 209 }
 210
 211 #define ADPLL_MAX_CON_ID        16      /* See MAX_CON_ID */
 212
 213 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
 214                                 int index, int output_index, const char *name,
 215                                 void (*unregister)(struct clk *clk))
 216 {
 217         struct clk_lookup *cl;
 218         const char *postfix = NULL;
 219         char con_id[ADPLL_MAX_CON_ID];
 220
 221         d->clocks[index].clk = clock;
 222         d->clocks[index].unregister = unregister;
 223
 224         /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
 225         postfix = strrchr(name, '.');
 226         if (postfix && strlen(postfix) > 1) {
 227                 if (strlen(postfix) > ADPLL_MAX_CON_ID)
 228                         dev_warn(d->dev, "clock %s con_id lookup may fail\n",
 229                                  name);
 230                 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
 231                 cl = clkdev_create(clock, con_id, NULL);
 232                 if (!cl)
 233                         return -ENOMEM;
 234                 d->clocks[index].cl = cl;
 235         } else {
 236                 dev_warn(d->dev, "no con_id for clock %s\n", name);
 237         }
 238
 239         if (output_index < 0)
 240                 return 0;
 241
 242         d->outputs.clks[output_index] = clock;
 243         d->outputs.clk_num++;
 244
 245         return 0;
 246 }
 247
 248 static int ti_adpll_init_divider(struct ti_adpll_data *d,
 249                                  enum ti_adpll_clocks index,
 250                                  int output_index, char *name,
 251                                  struct clk *parent_clock,
 252                                  void __iomem *reg,
 253                                  u8 shift, u8 width,
 254                                  u8 clk_divider_flags)
 255 {
 256         const char *child_name;
 257         const char *parent_name;
 258         struct clk *clock;
 259
 260         child_name = ti_adpll_clk_get_name(d, output_index, name);
 261         if (!child_name)
 262                 return -EINVAL;
 263
 264         parent_name = __clk_get_name(parent_clock);
 265         clock = clk_register_divider(d->dev, child_name, parent_name, 0,
 266                                      reg, shift, width, clk_divider_flags,
 267                                      &d->lock);
 268         if (IS_ERR(clock)) {
 269                 dev_err(d->dev, "failed to register divider %s: %li\n",
 270                         name, PTR_ERR(clock));
 271                 return PTR_ERR(clock);
 272         }
 273
 274         return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
 275                                     clk_unregister_divider);
 276 }
 277
 278 static int ti_adpll_init_mux(struct ti_adpll_data *d,
 279                              enum ti_adpll_clocks index,
 280                              char *name, struct clk *clk0,
 281                              struct clk *clk1,
 282                              void __iomem *reg,
 283                              u8 shift)
 284 {
 285         const char *child_name;
 286         const char *parents[2];
 287         struct clk *clock;
 288
 289         child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
 290         if (!child_name)
 291                 return -ENOMEM;
 292         parents[0] = __clk_get_name(clk0);
 293         parents[1] = __clk_get_name(clk1);
 294         clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
 295                                  reg, shift, 1, 0, &d->lock);
 296         if (IS_ERR(clock)) {
 297                 dev_err(d->dev, "failed to register mux %s: %li\n",
 298                         name, PTR_ERR(clock));
 299                 return PTR_ERR(clock);
 300         }
 301
 302         return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
 303                                     clk_unregister_mux);
 304 }
 305
 306 static int ti_adpll_init_gate(struct ti_adpll_data *d,
 307                               enum ti_adpll_clocks index,
 308                               int output_index, char *name,
 309                               struct clk *parent_clock,
 310                               void __iomem *reg,
 311                               u8 bit_idx,
 312                               u8 clk_gate_flags)
 313 {
 314         const char *child_name;
 315         const char *parent_name;
 316         struct clk *clock;
 317
 318         child_name = ti_adpll_clk_get_name(d, output_index, name);
 319         if (!child_name)
 320                 return -EINVAL;
 321
 322         parent_name = __clk_get_name(parent_clock);
 323         clock = clk_register_gate(d->dev, child_name, parent_name, 0,
 324                                   reg, bit_idx, clk_gate_flags,
 325                                   &d->lock);
 326         if (IS_ERR(clock)) {
 327                 dev_err(d->dev, "failed to register gate %s: %li\n",
 328                         name, PTR_ERR(clock));
 329                 return PTR_ERR(clock);
 330         }
 331
 332         return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
 333                                     clk_unregister_gate);
 334 }
 335
 336 static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
 337                                       enum ti_adpll_clocks index,
 338                                       char *name,
 339                                       struct clk *parent_clock,
 340                                       unsigned int mult,
 341                                       unsigned int div)
 342 {
 343         const char *child_name;
 344         const char *parent_name;
 345         struct clk *clock;
 346
 347         child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
 348         if (!child_name)
 349                 return -ENOMEM;
 350
 351         parent_name = __clk_get_name(parent_clock);
 352         clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
 353                                           0, mult, div);
 354         if (IS_ERR(clock))
 355                 return PTR_ERR(clock);
 356
 357         return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
 358                                     clk_unregister);
 359 }
 360
 361 static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
 362 {
 363         unsigned long flags;
 364         u32 v;
 365
 366         spin_lock_irqsave(&d->lock, flags);
 367         v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
 368         v |= BIT(ADPLL_CLKCTRL_IDLE);
 369         writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
 370         spin_unlock_irqrestore(&d->lock, flags);
 371 }
 372
 373 static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
 374 {
 375         unsigned long flags;
 376         u32 v;
 377
 378         spin_lock_irqsave(&d->lock, flags);
 379         v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
 380         v &= ~BIT(ADPLL_CLKCTRL_IDLE);
 381         writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
 382         spin_unlock_irqrestore(&d->lock, flags);
 383 }
 384
 385 static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
 386 {
 387         u32 v;
 388
 389         v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
 390
 391         return v & BIT(ADPLL_STATUS_BYPASS);
 392 }
 393
 394 /*
 395  * Locked and bypass are not actually mutually exclusive:  if you only care
 396  * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
 397  * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
 398  */
 399 static bool ti_adpll_is_locked(struct ti_adpll_data *d)
 400 {
 401         u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
 402
 403         return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
 404 }
 405
 406 static int ti_adpll_wait_lock(struct ti_adpll_data *d)
 407 {
 408         int retries = ADPLL_MAX_RETRIES;
 409
 410         do {
 411                 if (ti_adpll_is_locked(d))
 412                         return 0;
 413                 usleep_range(200, 300);
 414         } while (retries--);
 415
 416         dev_err(d->dev, "pll failed to lock\n");
 417         return -ETIMEDOUT;
 418 }
 419
 420 static int ti_adpll_prepare(struct clk_hw *hw)
 421 {
 422         struct ti_adpll_dco_data *dco = to_dco(hw);
 423         struct ti_adpll_data *d = to_adpll(dco);
 424
 425         ti_adpll_clear_idle_bypass(d);
 426         ti_adpll_wait_lock(d);
 427
 428         return 0;
 429 }
 430
 431 static void ti_adpll_unprepare(struct clk_hw *hw)
 432 {
 433         struct ti_adpll_dco_data *dco = to_dco(hw);
 434         struct ti_adpll_data *d = to_adpll(dco);
 435
 436         ti_adpll_set_idle_bypass(d);
 437 }
 438
 439 static int ti_adpll_is_prepared(struct clk_hw *hw)
 440 {
 441         struct ti_adpll_dco_data *dco = to_dco(hw);
 442         struct ti_adpll_data *d = to_adpll(dco);
 443
 444         return ti_adpll_is_locked(d);
 445 }
 446
 447 /*
 448  * Note that the DCO clock is never subject to bypass: if the PLL is off,
 449  * dcoclk is low.
 450  */
 451 static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
 452                                           unsigned long parent_rate)
 453 {
 454         struct ti_adpll_dco_data *dco = to_dco(hw);
 455         struct ti_adpll_data *d = to_adpll(dco);
 456         u32 frac_m, divider, v;
 457         u64 rate;
 458         unsigned long flags;
 459
 460         if (ti_adpll_clock_is_bypass(d))
 461                 return 0;
 462
 463         spin_lock_irqsave(&d->lock, flags);
 464         frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
 465         frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
 466         rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
 467         rate += frac_m;
 468         rate *= parent_rate;
 469         divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
 470         spin_unlock_irqrestore(&d->lock, flags);
 471
 472         do_div(rate, divider);
 473
 474         if (d->c->is_type_s) {
 475                 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
 476                 if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
 477                         rate *= 4;
 478                 rate *= 2;
 479         }
 480
 481         return rate;
 482 }
 483
 484 /* PLL parent is always clkinp, bypass only affects the children */
 485 static u8 ti_adpll_get_parent(struct clk_hw *hw)
 486 {
 487         return 0;
 488 }
 489
 490 static const struct clk_ops ti_adpll_ops = {
 491         .prepare = ti_adpll_prepare,
 492         .unprepare = ti_adpll_unprepare,
 493         .is_prepared = ti_adpll_is_prepared,
 494         .recalc_rate = ti_adpll_recalc_rate,
 495         .get_parent = ti_adpll_get_parent,
 496 };
 497
 498 static int ti_adpll_init_dco(struct ti_adpll_data *d)
 499 {
 500         struct clk_init_data init;
 501         struct clk *clock;
 502         const char *postfix;
 503         int width, err;
 504
 505         d->outputs.clks = devm_kcalloc(d->dev,
 506                                        MAX_ADPLL_OUTPUTS,
 507                                        sizeof(struct clk *),
 508                                        GFP_KERNEL);
 509         if (!d->outputs.clks)
 510                 return -ENOMEM;
 511
 512         if (d->c->output_index < 0)
 513                 postfix = "dco";
 514         else
 515                 postfix = NULL;
 516
 517         init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
 518         if (!init.name)
 519                 return -EINVAL;
 520
 521         init.parent_names = d->parent_names;
 522         init.num_parents = d->c->nr_max_inputs;
 523         init.ops = &ti_adpll_ops;
 524         init.flags = CLK_GET_RATE_NOCACHE;
 525         d->dco.hw.init = &init;
 526
 527         if (d->c->is_type_s)
 528                 width = 5;
 529         else
 530                 width = 4;
 531
 532         /* Internal input clock divider N2 */
 533         err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
 534                                     d->parent_clocks[TI_ADPLL_CLKINP],
 535                                     d->regs + ADPLL_MN2DIV_OFFSET,
 536                                     ADPLL_MN2DIV_N2, width, 0);
 537         if (err)
 538                 return err;
 539
 540         clock = devm_clk_register(d->dev, &d->dco.hw);
 541         if (IS_ERR(clock))
 542                 return PTR_ERR(clock);
 543
 544         return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
 545                                     init.name, NULL);
 546 }
 547
 548 static int ti_adpll_clkout_enable(struct clk_hw *hw)
 549 {
 550         struct ti_adpll_clkout_data *co = to_clkout(hw);
 551         struct clk_hw *gate_hw = &co->gate.hw;
 552
 553         __clk_hw_set_clk(gate_hw, hw);
 554
 555         return clk_gate_ops.enable(gate_hw);
 556 }
 557
 558 static void ti_adpll_clkout_disable(struct clk_hw *hw)
 559 {
 560         struct ti_adpll_clkout_data *co = to_clkout(hw);
 561         struct clk_hw *gate_hw = &co->gate.hw;
 562
 563         __clk_hw_set_clk(gate_hw, hw);
 564         clk_gate_ops.disable(gate_hw);
 565 }
 566
 567 static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
 568 {
 569         struct ti_adpll_clkout_data *co = to_clkout(hw);
 570         struct clk_hw *gate_hw = &co->gate.hw;
 571
 572         __clk_hw_set_clk(gate_hw, hw);
 573
 574         return clk_gate_ops.is_enabled(gate_hw);
 575 }
 576
 577 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
 578 static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
 579 {
 580         struct ti_adpll_clkout_data *co = to_clkout(hw);
 581         struct ti_adpll_data *d = co->adpll;
 582
 583         return ti_adpll_clock_is_bypass(d);
 584 }
 585
 586 static int ti_adpll_init_clkout(struct ti_adpll_data *d,
 587                                 enum ti_adpll_clocks index,
 588                                 int output_index, int gate_bit,
 589                                 char *name, struct clk *clk0,
 590                                 struct clk *clk1)
 591 {
 592         struct ti_adpll_clkout_data *co;
 593         struct clk_init_data init;
 594         struct clk_ops *ops;
 595         const char *parent_names[2];
 596         const char *child_name;
 597         struct clk *clock;
 598         int err;
 599
 600         co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
 601         if (!co)
 602                 return -ENOMEM;
 603         co->adpll = d;
 604
 605         err = of_property_read_string_index(d->np,
 606                                             "clock-output-names",
 607                                             output_index,
 608                                             &child_name);
 609         if (err)
 610                 return err;
 611
 612         ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
 613         if (!ops)
 614                 return -ENOMEM;
 615
 616         init.name = child_name;
 617         init.ops = ops;
 618         init.flags = 0;
 619         co->hw.init = &init;
 620         parent_names[0] = __clk_get_name(clk0);
 621         parent_names[1] = __clk_get_name(clk1);
 622         init.parent_names = parent_names;
 623         init.num_parents = 2;
 624
 625         ops->get_parent = ti_adpll_clkout_get_parent;
 626         ops->determine_rate = __clk_mux_determine_rate;
 627         if (gate_bit) {
 628                 co->gate.lock = &d->lock;
 629                 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
 630                 co->gate.bit_idx = gate_bit;
 631                 ops->enable = ti_adpll_clkout_enable;
 632                 ops->disable = ti_adpll_clkout_disable;
 633                 ops->is_enabled = ti_adpll_clkout_is_enabled;
 634         }
 635
 636         clock = devm_clk_register(d->dev, &co->hw);
 637         if (IS_ERR(clock)) {
 638                 dev_err(d->dev, "failed to register output %s: %li\n",
 639                         name, PTR_ERR(clock));
 640                 return PTR_ERR(clock);
 641         }
 642
 643         return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
 644                                     NULL);
 645 }
 646
 647 static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
 648 {
 649         int err;
 650
 651         if (!d->c->is_type_s)
 652                 return 0;
 653
 654         /* Internal mux, sources from divider N2 or clkinpulow */
 655         err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
 656                                 d->clocks[TI_ADPLL_N2].clk,
 657                                 d->parent_clocks[TI_ADPLL_CLKINPULOW],
 658                                 d->regs + ADPLL_CLKCTRL_OFFSET,
 659                                 ADPLL_CLKCTRL_ULOWCLKEN);
 660         if (err)
 661                 return err;
 662
 663         /* Internal divider M2, sources DCO */
 664         err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
 665                                     d->clocks[TI_ADPLL_DCO].clk,
 666                                     d->regs + ADPLL_M2NDIV_OFFSET,
 667                                     ADPLL_M2NDIV_M2,
 668                                     ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
 669                                     CLK_DIVIDER_ONE_BASED);
 670         if (err)
 671                 return err;
 672
 673         /* Internal fixed divider, after M2 before clkout */
 674         err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
 675                                          d->clocks[TI_ADPLL_M2].clk,
 676                                          1, 2);
 677         if (err)
 678                 return err;
 679
 680         /* Output clkout with a mux and gate, sources from div2 or bypass */
 681         err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
 682                                    ADPLL_CLKCTRL_CLKOUTEN, "clkout",
 683                                    d->clocks[TI_ADPLL_DIV2].clk,
 684                                    d->clocks[TI_ADPLL_BYPASS].clk);
 685         if (err)
 686                 return err;
 687
 688         /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
 689         err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
 690                                    "clkout2", d->clocks[TI_ADPLL_M2].clk,
 691                                    d->clocks[TI_ADPLL_BYPASS].clk);
 692         if (err)
 693                 return err;
 694
 695         /* Internal mux, sources from DCO and clkinphif */
 696         if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
 697                 err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
 698                                         d->clocks[TI_ADPLL_DCO].clk,
 699                                         d->parent_clocks[TI_ADPLL_CLKINPHIF],
 700                                         d->regs + ADPLL_CLKCTRL_OFFSET,
 701                                         ADPLL_CLKINPHIFSEL_ADPLL_S);
 702                 if (err)
 703                         return err;
 704         }
 705
 706         /* Output clkouthif with a divider M3, sources from hif */
 707         err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
 708                                     d->clocks[TI_ADPLL_HIF].clk,
 709                                     d->regs + ADPLL_M3DIV_OFFSET,
 710                                     ADPLL_M3DIV_M3,
 711                                     ADPLL_M3DIV_M3_WIDTH,
 712                                     CLK_DIVIDER_ONE_BASED);
 713         if (err)
 714                 return err;
 715
 716         /* Output clock dcoclkldo is the DCO */
 717
 718         return 0;
 719 }
 720
 721 static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
 722 {
 723         int err;
 724
 725         if (d->c->is_type_s)
 726                 return 0;
 727
 728         /* Output clkdcoldo, gated output of DCO */
 729         err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
 730                                  "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
 731                                  d->regs + ADPLL_CLKCTRL_OFFSET,
 732                                  ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
 733         if (err)
 734                 return err;
 735
 736         /* Internal divider M2, sources from DCO */
 737         err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
 738                                     "m2", d->clocks[TI_ADPLL_DCO].clk,
 739                                     d->regs + ADPLL_M2NDIV_OFFSET,
 740                                     ADPLL_M2NDIV_M2,
 741                                     ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
 742                                     CLK_DIVIDER_ONE_BASED);
 743         if (err)
 744                 return err;
 745
 746         /* Output clkoutldo, gated output of M2 */
 747         err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
 748                                  "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
 749                                  d->regs + ADPLL_CLKCTRL_OFFSET,
 750                                  ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
 751                                  0);
 752         if (err)
 753                 return err;
 754
 755         /* Internal mux, sources from divider N2 or clkinpulow */
 756         err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
 757                                 d->clocks[TI_ADPLL_N2].clk,
 758                                 d->parent_clocks[TI_ADPLL_CLKINPULOW],
 759                                 d->regs + ADPLL_CLKCTRL_OFFSET,
 760                                 ADPLL_CLKCTRL_ULOWCLKEN);
 761         if (err)
 762                 return err;
 763
 764         /* Output clkout, sources M2 or bypass */
 765         err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
 766                                    ADPLL_CLKCTRL_CLKOUTEN, "clkout",
 767                                    d->clocks[TI_ADPLL_M2].clk,
 768                                    d->clocks[TI_ADPLL_BYPASS].clk);
 769         if (err)
 770                 return err;
 771
 772         return 0;
 773 }
 774
 775 static void ti_adpll_free_resources(struct ti_adpll_data *d)
 776 {
 777         int i;
 778
 779         for (i = TI_ADPLL_M3; i >= 0; i--) {
 780                 struct ti_adpll_clock *ac = &d->clocks[i];
 781
 782                 if (!ac || IS_ERR_OR_NULL(ac->clk))
 783                         continue;
 784                 if (ac->cl)
 785                         clkdev_drop(ac->cl);
 786                 if (ac->unregister)
 787                         ac->unregister(ac->clk);
 788         }
 789 }
 790
 791 /* MPU PLL manages the lock register for all PLLs */
 792 static void ti_adpll_unlock_all(void __iomem *reg)
 793 {
 794         u32 v;
 795
 796         v = readl_relaxed(reg);
 797         if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
 798                 writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
 799 }
 800
 801 static int ti_adpll_init_registers(struct ti_adpll_data *d)
 802 {
 803         int register_offset = 0;
 804
 805         if (d->c->is_type_s) {
 806                 register_offset = 8;
 807                 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
 808         }
 809
 810         d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
 811
 812         return 0;
 813 }
 814
 815 static int ti_adpll_init_inputs(struct ti_adpll_data *d)
 816 {
 817         const char *error = "need at least %i inputs";
 818         struct clk *clock;
 819         int nr_inputs;
 820
 821         nr_inputs = of_clk_get_parent_count(d->np);
 822         if (nr_inputs < d->c->nr_max_inputs) {
 823                 dev_err(d->dev, error, nr_inputs);
 824                 return -EINVAL;
 825         }
 826         of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
 827
 828         clock = devm_clk_get(d->dev, d->parent_names[0]);
 829         if (IS_ERR(clock)) {
 830                 dev_err(d->dev, "could not get clkinp\n");
 831                 return PTR_ERR(clock);
 832         }
 833         d->parent_clocks[TI_ADPLL_CLKINP] = clock;
 834
 835         clock = devm_clk_get(d->dev, d->parent_names[1]);
 836         if (IS_ERR(clock)) {
 837                 dev_err(d->dev, "could not get clkinpulow clock\n");
 838                 return PTR_ERR(clock);
 839         }
 840         d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
 841
 842         if (d->c->is_type_s) {
 843                 clock =  devm_clk_get(d->dev, d->parent_names[2]);
 844                 if (IS_ERR(clock)) {
 845                         dev_err(d->dev, "could not get clkinphif clock\n");
 846                         return PTR_ERR(clock);
 847                 }
 848                 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
 849         }
 850
 851         return 0;
 852 }
 853
 854 static const struct ti_adpll_platform_data ti_adpll_type_s = {
 855         .is_type_s = true,
 856         .nr_max_inputs = MAX_ADPLL_INPUTS,
 857         .nr_max_outputs = MAX_ADPLL_OUTPUTS,
 858         .output_index = TI_ADPLL_S_DCOCLKLDO,
 859 };
 860
 861 static const struct ti_adpll_platform_data ti_adpll_type_lj = {
 862         .is_type_s = false,
 863         .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
 864         .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
 865         .output_index = -EINVAL,
 866 };
 867
 868 static const struct of_device_id ti_adpll_match[] = {
 869         { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
 870         { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
 871         {},
 872 };
 873 MODULE_DEVICE_TABLE(of, ti_adpll_match);
 874
 875 static int ti_adpll_probe(struct platform_device *pdev)
 876 {
 877         struct device_node *node = pdev->dev.of_node;
 878         struct device *dev = &pdev->dev;
 879         const struct of_device_id *match;
 880         const struct ti_adpll_platform_data *pdata;
 881         struct ti_adpll_data *d;
 882         struct resource *res;
 883         int err;
 884
 885         match = of_match_device(ti_adpll_match, dev);
 886         if (match)
 887                 pdata = match->data;
 888         else
 889                 return -ENODEV;
 890
 891         d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
 892         if (!d)
 893                 return -ENOMEM;
 894         d->dev = dev;
 895         d->np = node;
 896         d->c = pdata;
 897         dev_set_drvdata(d->dev, d);
 898         spin_lock_init(&d->lock);
 899
 900         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 901         if (!res)
 902                 return -ENODEV;
 903         d->pa = res->start;
 904
 905         d->iobase = devm_ioremap_resource(dev, res);
 906         if (IS_ERR(d->iobase)) {
 907                 dev_err(dev, "could not get IO base: %li\n",
 908                         PTR_ERR(d->iobase));
 909                 return PTR_ERR(d->iobase);
 910         }
 911
 912         err = ti_adpll_init_registers(d);
 913         if (err)
 914                 return err;
 915
 916         err = ti_adpll_init_inputs(d);
 917         if (err)
 918                 return err;
 919
 920         d->clocks = devm_kcalloc(d->dev,
 921                                  TI_ADPLL_NR_CLOCKS,
 922                                  sizeof(struct ti_adpll_clock),
 923                                  GFP_KERNEL);
 924         if (!d->clocks)
 925                 return -ENOMEM;
 926
 927         err = ti_adpll_init_dco(d);
 928         if (err) {
 929                 dev_err(dev, "could not register dco: %i\n", err);
 930                 goto free;
 931         }
 932
 933         err = ti_adpll_init_children_adpll_s(d);
 934         if (err)
 935                 goto free;
 936         err = ti_adpll_init_children_adpll_lj(d);
 937         if (err)
 938                 goto free;
 939
 940         err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
 941         if (err)
 942                 goto free;
 943
 944         return 0;
 945
 946 free:
 947         WARN_ON(1);
 948         ti_adpll_free_resources(d);
 949
 950         return err;
 951 }
 952
 953 static int ti_adpll_remove(struct platform_device *pdev)
 954 {
 955         struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
 956
 957         ti_adpll_free_resources(d);
 958
 959         return 0;
 960 }
 961
 962 static struct platform_driver ti_adpll_driver = {
 963         .driver = {
 964                 .name = "ti-adpll",
 965                 .of_match_table = ti_adpll_match,
 966         },
 967         .probe = ti_adpll_probe,
 968         .remove = ti_adpll_remove,
 969 };
 970
 971 static int __init ti_adpll_init(void)
 972 {
 973         return platform_driver_register(&ti_adpll_driver);
 974 }
 975 core_initcall(ti_adpll_init);
 976
 977 static void __exit ti_adpll_exit(void)
 978 {
 979         platform_driver_unregister(&ti_adpll_driver);
 980 }
 981 module_exit(ti_adpll_exit);
 982
 983 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
 984 MODULE_ALIAS("platform:dm814-adpll-clock");
 985 MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
 986 MODULE_LICENSE("GPL v2");