2 * OMAP clkctrl clock support
4 * Copyright (C) 2017 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
21 #include <linux/of_address.h>
22 #include <linux/clk/ti.h>
23 #include <linux/delay.h>
24 #include <linux/timekeeping.h>
29 #define OMAP4_MODULEMODE_MASK 0x3
31 #define MODULEMODE_HWCTRL 0x1
32 #define MODULEMODE_SWCTRL 0x2
34 #define OMAP4_IDLEST_MASK (0x3 << 16)
35 #define OMAP4_IDLEST_SHIFT 16
37 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0
38 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
39 #define CLKCTRL_IDLEST_DISABLED 0x3
41 /* These timeouts are in us */
42 #define OMAP4_MAX_MODULE_READY_TIME 2000
43 #define OMAP4_MAX_MODULE_DISABLE_TIME 5000
45 static bool _early_timeout = true;
47 struct omap_clkctrl_provider {
49 struct list_head clocks;
53 struct omap_clkctrl_clk {
57 struct list_head node;
65 static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
69 static u32 _omap4_idlest(u32 val)
71 val &= OMAP4_IDLEST_MASK;
72 val >>= OMAP4_IDLEST_SHIFT;
77 static bool _omap4_is_idle(u32 val)
79 val = _omap4_idlest(val);
81 return val == CLKCTRL_IDLEST_DISABLED;
84 static bool _omap4_is_ready(u32 val)
86 val = _omap4_idlest(val);
88 return val == CLKCTRL_IDLEST_FUNCTIONAL ||
89 val == CLKCTRL_IDLEST_INTERFACE_IDLE;
92 static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
95 * There are two special cases where ktime_to_ns() can't be
96 * used to track the timeouts. First one is during early boot
97 * when the timers haven't been initialized yet. The second
98 * one is during suspend-resume cycle while timekeeping is
99 * being suspended / resumed. Clocksource for the system
100 * can be from a timer that requires pm_runtime access, which
101 * will eventually bring us here with timekeeping_suspended,
102 * during both suspend entry and resume paths. This happens
103 * at least on am43xx platform.
105 if (unlikely(_early_timeout || timekeeping_suspended)) {
106 if (time->cycles++ < timeout) {
111 if (!ktime_to_ns(time->start)) {
112 time->start = ktime_get();
116 if (ktime_us_delta(ktime_get(), time->start) < timeout) {
125 static int __init _omap4_disable_early_timeout(void)
127 _early_timeout = false;
131 arch_initcall(_omap4_disable_early_timeout);
133 static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
135 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
138 union omap4_timeout timeout = { 0 };
141 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
144 "%s: could not enable %s's clockdomain %s: %d\n",
145 __func__, clk_hw_get_name(hw),
146 clk->clkdm_name, ret);
151 if (!clk->enable_bit)
154 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
156 val &= ~OMAP4_MODULEMODE_MASK;
157 val |= clk->enable_bit;
159 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
161 if (clk->flags & NO_IDLEST)
164 /* Wait until module is enabled */
165 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
166 if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
167 pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
175 static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
177 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
179 union omap4_timeout timeout = { 0 };
181 if (!clk->enable_bit)
184 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
186 val &= ~OMAP4_MODULEMODE_MASK;
188 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
190 if (clk->flags & NO_IDLEST)
193 /* Wait until module is disabled */
194 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
195 if (_omap4_is_timeout(&timeout,
196 OMAP4_MAX_MODULE_DISABLE_TIME)) {
197 pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
204 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
207 static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
209 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
212 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
214 if (val & clk->enable_bit)
220 static const struct clk_ops omap4_clkctrl_clk_ops = {
221 .enable = _omap4_clkctrl_clk_enable,
222 .disable = _omap4_clkctrl_clk_disable,
223 .is_enabled = _omap4_clkctrl_clk_is_enabled,
224 .init = omap2_init_clk_clkdm,
227 static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
230 struct omap_clkctrl_provider *provider = data;
231 struct omap_clkctrl_clk *entry;
234 if (clkspec->args_count != 2)
235 return ERR_PTR(-EINVAL);
237 pr_debug("%s: looking for %x:%x\n", __func__,
238 clkspec->args[0], clkspec->args[1]);
240 list_for_each_entry(entry, &provider->clocks, node) {
241 if (entry->reg_offset == clkspec->args[0] &&
242 entry->bit_offset == clkspec->args[1]) {
249 return ERR_PTR(-EINVAL);
255 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
256 struct device_node *node, struct clk_hw *clk_hw,
257 u16 offset, u8 bit, const char * const *parents,
258 int num_parents, const struct clk_ops *ops)
260 struct clk_init_data init = { NULL };
262 struct omap_clkctrl_clk *clkctrl_clk;
265 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
266 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
267 node->parent, node, offset,
270 init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", node,
272 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
273 if (!init.name || !clkctrl_clk) {
278 clk_hw->init = &init;
279 init.parent_names = parents;
280 init.num_parents = num_parents;
284 clk = ti_clk_register(NULL, clk_hw, init.name);
285 if (IS_ERR_OR_NULL(clk)) {
290 clkctrl_clk->reg_offset = offset;
291 clkctrl_clk->bit_offset = bit;
292 clkctrl_clk->clk = clk_hw;
294 list_add(&clkctrl_clk->node, &provider->clocks);
305 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
306 struct device_node *node, u16 offset,
307 const struct omap_clkctrl_bit_data *data,
310 struct clk_hw_omap *clk_hw;
312 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
316 clk_hw->enable_bit = data->bit;
317 clk_hw->enable_reg.ptr = reg;
319 if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
320 data->bit, data->parents, 1,
326 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
327 struct device_node *node, u16 offset,
328 const struct omap_clkctrl_bit_data *data,
331 struct clk_omap_mux *mux;
333 const char * const *pname;
335 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
339 pname = data->parents;
345 mux->mask = num_parents;
346 if (!(mux->flags & CLK_MUX_INDEX_ONE))
349 mux->mask = (1 << fls(mux->mask)) - 1;
351 mux->shift = data->bit;
354 if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
355 data->bit, data->parents, num_parents,
361 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
362 struct device_node *node, u16 offset,
363 const struct omap_clkctrl_bit_data *data,
366 struct clk_omap_divider *div;
367 const struct omap_clkctrl_div_data *div_data = data->data;
370 div = kzalloc(sizeof(*div), GFP_KERNEL);
375 div->shift = data->bit;
376 div->flags = div_data->flags;
378 if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
379 div_flags |= CLKF_INDEX_POWER_OF_TWO;
381 if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
382 div_data->max_div, div_flags,
383 &div->width, &div->table)) {
384 pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
385 node, offset, data->bit);
390 if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
391 data->bit, data->parents, 1,
392 &ti_clk_divider_ops))
397 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
398 struct device_node *node,
399 const struct omap_clkctrl_reg_data *data,
402 const struct omap_clkctrl_bit_data *bits = data->bit_data;
408 switch (bits->type) {
410 _ti_clkctrl_setup_gate(provider, node, data->offset,
415 _ti_clkctrl_setup_div(provider, node, data->offset,
420 _ti_clkctrl_setup_mux(provider, node, data->offset,
425 pr_err("%s: bad subclk type: %d\n", __func__,
433 static void __init _clkctrl_add_provider(void *data,
434 struct device_node *np)
436 of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
439 static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
441 struct omap_clkctrl_provider *provider;
442 const struct omap_clkctrl_data *data = default_clkctrl_data;
443 const struct omap_clkctrl_reg_data *reg_data;
444 struct clk_init_data init = { NULL };
445 struct clk_hw_omap *hw;
447 struct omap_clkctrl_clk *clkctrl_clk;
454 if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
455 of_node_name_eq(node, "clk"))
456 ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
458 addrp = of_get_address(node, 0, NULL, NULL);
459 addr = (u32)of_translate_address(node, addrp);
461 #ifdef CONFIG_ARCH_OMAP4
462 if (of_machine_is_compatible("ti,omap4"))
463 data = omap4_clkctrl_data;
465 #ifdef CONFIG_SOC_OMAP5
466 if (of_machine_is_compatible("ti,omap5"))
467 data = omap5_clkctrl_data;
469 #ifdef CONFIG_SOC_DRA7XX
470 if (of_machine_is_compatible("ti,dra7")) {
471 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
472 data = dra7_clkctrl_compat_data;
474 data = dra7_clkctrl_data;
477 if (of_machine_is_compatible("ti,dra72"))
478 soc_mask = CLKF_SOC_DRA72;
479 if (of_machine_is_compatible("ti,dra74"))
480 soc_mask = CLKF_SOC_DRA74;
481 if (of_machine_is_compatible("ti,dra76"))
482 soc_mask = CLKF_SOC_DRA76;
484 #ifdef CONFIG_SOC_AM33XX
485 if (of_machine_is_compatible("ti,am33xx")) {
486 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
487 data = am3_clkctrl_compat_data;
489 data = am3_clkctrl_data;
492 #ifdef CONFIG_SOC_AM43XX
493 if (of_machine_is_compatible("ti,am4372")) {
494 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
495 data = am4_clkctrl_compat_data;
497 data = am4_clkctrl_data;
500 if (of_machine_is_compatible("ti,am438x")) {
501 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
502 data = am438x_clkctrl_compat_data;
504 data = am438x_clkctrl_data;
507 #ifdef CONFIG_SOC_TI81XX
508 if (of_machine_is_compatible("ti,dm814"))
509 data = dm814_clkctrl_data;
511 if (of_machine_is_compatible("ti,dm816"))
512 data = dm816_clkctrl_data;
515 if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
516 soc_mask |= CLKF_SOC_NONSEC;
519 if (addr == data->addr)
526 pr_err("%pOF not found from clkctrl data.\n", node);
530 provider = kzalloc(sizeof(*provider), GFP_KERNEL);
534 provider->base = of_iomap(node, 0);
536 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) {
537 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
538 if (!provider->clkdm_name) {
544 * Create default clkdm name, replace _cm from end of parent
545 * node name with _clkdm
547 provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
549 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
550 if (!provider->clkdm_name) {
556 * Create default clkdm name, replace _clkctrl from end of
557 * node name with _clkdm
559 provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
562 strcat(provider->clkdm_name, "clkdm");
564 /* Replace any dash from the clkdm name with underscore */
565 c = provider->clkdm_name;
573 INIT_LIST_HEAD(&provider->clocks);
575 /* Generate clocks */
576 reg_data = data->regs;
578 while (reg_data->parent) {
579 if ((reg_data->flags & CLKF_SOC_MASK) &&
580 (reg_data->flags & soc_mask) == 0) {
585 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
589 hw->enable_reg.ptr = provider->base + reg_data->offset;
591 _ti_clkctrl_setup_subclks(provider, node, reg_data,
594 if (reg_data->flags & CLKF_SW_SUP)
595 hw->enable_bit = MODULEMODE_SWCTRL;
596 if (reg_data->flags & CLKF_HW_SUP)
597 hw->enable_bit = MODULEMODE_HWCTRL;
598 if (reg_data->flags & CLKF_NO_IDLEST)
599 hw->flags |= NO_IDLEST;
601 if (reg_data->clkdm_name)
602 hw->clkdm_name = reg_data->clkdm_name;
604 hw->clkdm_name = provider->clkdm_name;
606 init.parent_names = ®_data->parent;
607 init.num_parents = 1;
609 if (reg_data->flags & CLKF_SET_RATE_PARENT)
610 init.flags |= CLK_SET_RATE_PARENT;
611 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
612 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
614 reg_data->offset, 0);
616 init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d",
617 node, reg_data->offset, 0);
618 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
619 if (!init.name || !clkctrl_clk)
622 init.ops = &omap4_clkctrl_clk_ops;
625 clk = ti_clk_register(NULL, &hw->hw, init.name);
626 if (IS_ERR_OR_NULL(clk))
629 clkctrl_clk->reg_offset = reg_data->offset;
630 clkctrl_clk->clk = &hw->hw;
632 list_add(&clkctrl_clk->node, &provider->clocks);
637 ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
638 if (ret == -EPROBE_DEFER)
639 ti_clk_retry_init(node, provider, _clkctrl_add_provider);
648 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
649 _ti_omap4_clkctrl_setup);