2 * Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Irina Tirdea <irina.tirdea@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/err.h>
20 #include <linux/platform_data/x86/clk-pmc-atom.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #define PLT_CLK_NAME_BASE "pmc_plt_clk"
26 #define PMC_CLK_CTL_OFFSET 0x60
27 #define PMC_CLK_CTL_SIZE 4
29 #define PMC_CLK_CTL_GATED_ON_D3 0x0
30 #define PMC_CLK_CTL_FORCE_ON 0x1
31 #define PMC_CLK_CTL_FORCE_OFF 0x2
32 #define PMC_CLK_CTL_RESERVED 0x3
33 #define PMC_MASK_CLK_CTL GENMASK(1, 0)
34 #define PMC_MASK_CLK_FREQ BIT(2)
35 #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
36 #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
38 struct clk_plt_fixed {
40 struct clk_lookup *lookup;
46 struct clk_lookup *lookup;
47 /* protect access to PMC registers */
51 #define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
54 struct clk_plt_fixed **parents;
56 struct clk_plt *clks[PMC_CLK_NUM];
57 struct clk_lookup *mclk_lookup;
60 /* Return an index in parent table */
61 static inline int plt_reg_to_parent(int reg)
63 switch (reg & PMC_MASK_CLK_FREQ) {
65 case PMC_CLK_FREQ_XTAL:
67 case PMC_CLK_FREQ_PLL:
72 /* Return clk index of parent */
73 static inline int plt_parent_to_reg(int index)
78 return PMC_CLK_FREQ_XTAL;
80 return PMC_CLK_FREQ_PLL;
84 /* Abstract status in simpler enabled/disabled value */
85 static inline int plt_reg_to_enabled(int reg)
87 switch (reg & PMC_MASK_CLK_CTL) {
88 case PMC_CLK_CTL_GATED_ON_D3:
89 case PMC_CLK_CTL_FORCE_ON:
90 return 1; /* enabled */
91 case PMC_CLK_CTL_FORCE_OFF:
92 case PMC_CLK_CTL_RESERVED:
94 return 0; /* disabled */
98 static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
103 spin_lock_irqsave(&clk->lock, flags);
105 tmp = readl(clk->reg);
106 tmp = (tmp & ~mask) | (val & mask);
107 writel(tmp, clk->reg);
109 spin_unlock_irqrestore(&clk->lock, flags);
112 static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
114 struct clk_plt *clk = to_clk_plt(hw);
116 plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
121 static u8 plt_clk_get_parent(struct clk_hw *hw)
123 struct clk_plt *clk = to_clk_plt(hw);
126 value = readl(clk->reg);
128 return plt_reg_to_parent(value);
131 static int plt_clk_enable(struct clk_hw *hw)
133 struct clk_plt *clk = to_clk_plt(hw);
135 plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
140 static void plt_clk_disable(struct clk_hw *hw)
142 struct clk_plt *clk = to_clk_plt(hw);
144 plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
147 static int plt_clk_is_enabled(struct clk_hw *hw)
149 struct clk_plt *clk = to_clk_plt(hw);
152 value = readl(clk->reg);
154 return plt_reg_to_enabled(value);
157 static const struct clk_ops plt_clk_ops = {
158 .enable = plt_clk_enable,
159 .disable = plt_clk_disable,
160 .is_enabled = plt_clk_is_enabled,
161 .get_parent = plt_clk_get_parent,
162 .set_parent = plt_clk_set_parent,
163 .determine_rate = __clk_mux_determine_rate,
166 static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
168 const char **parent_names,
171 struct clk_plt *pclk;
172 struct clk_init_data init;
175 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
177 return ERR_PTR(-ENOMEM);
179 init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
180 init.ops = &plt_clk_ops;
182 init.parent_names = parent_names;
183 init.num_parents = num_parents;
185 pclk->hw.init = &init;
186 pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
187 spin_lock_init(&pclk->lock);
189 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
195 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
197 pclk = ERR_PTR(-ENOMEM);
206 static void plt_clk_unregister(struct clk_plt *pclk)
208 clkdev_drop(pclk->lookup);
211 static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
213 const char *parent_name,
214 unsigned long fixed_rate)
216 struct clk_plt_fixed *pclk;
218 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
220 return ERR_PTR(-ENOMEM);
222 pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
224 if (IS_ERR(pclk->clk))
225 return ERR_CAST(pclk->clk);
227 pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
229 clk_hw_unregister_fixed_rate(pclk->clk);
230 return ERR_PTR(-ENOMEM);
236 static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
238 clkdev_drop(pclk->lookup);
239 clk_hw_unregister_fixed_rate(pclk->clk);
242 static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
246 plt_clk_unregister_fixed_rate(data->parents[i]);
249 static void plt_clk_free_parent_names_loop(const char **parent_names,
253 kfree_const(parent_names[i]);
257 static void plt_clk_unregister_loop(struct clk_plt_data *data,
261 plt_clk_unregister(data->clks[i]);
264 static const char **plt_clk_register_parents(struct platform_device *pdev,
265 struct clk_plt_data *data,
266 const struct pmc_clk *clks)
268 const char **parent_names;
274 while (clks[nparents].name)
277 data->parents = devm_kcalloc(&pdev->dev, nparents,
278 sizeof(*data->parents), GFP_KERNEL);
280 return ERR_PTR(-ENOMEM);
282 parent_names = kcalloc(nparents, sizeof(*parent_names),
285 return ERR_PTR(-ENOMEM);
287 for (i = 0; i < nparents; i++) {
289 plt_clk_register_fixed_rate(pdev, clks[i].name,
292 if (IS_ERR(data->parents[i])) {
293 err = PTR_ERR(data->parents[i]);
296 parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
299 data->nparents = nparents;
303 plt_clk_unregister_fixed_rate_loop(data, i);
304 plt_clk_free_parent_names_loop(parent_names, i);
308 static void plt_clk_unregister_parents(struct clk_plt_data *data)
310 plt_clk_unregister_fixed_rate_loop(data, data->nparents);
313 static int plt_clk_probe(struct platform_device *pdev)
315 const struct pmc_clk_data *pmc_data;
316 const char **parent_names;
317 struct clk_plt_data *data;
321 pmc_data = dev_get_platdata(&pdev->dev);
322 if (!pmc_data || !pmc_data->clks)
325 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
329 parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
330 if (IS_ERR(parent_names))
331 return PTR_ERR(parent_names);
333 for (i = 0; i < PMC_CLK_NUM; i++) {
334 data->clks[i] = plt_clk_register(pdev, i, pmc_data->base,
335 parent_names, data->nparents);
336 if (IS_ERR(data->clks[i])) {
337 err = PTR_ERR(data->clks[i]);
338 goto err_unreg_clk_plt;
341 data->mclk_lookup = clkdev_hw_create(&data->clks[3]->hw, "mclk", NULL);
342 if (!data->mclk_lookup) {
344 goto err_unreg_clk_plt;
347 plt_clk_free_parent_names_loop(parent_names, data->nparents);
349 platform_set_drvdata(pdev, data);
353 plt_clk_unregister_loop(data, i);
354 plt_clk_unregister_parents(data);
355 plt_clk_free_parent_names_loop(parent_names, data->nparents);
359 static int plt_clk_remove(struct platform_device *pdev)
361 struct clk_plt_data *data;
363 data = platform_get_drvdata(pdev);
365 clkdev_drop(data->mclk_lookup);
366 plt_clk_unregister_loop(data, PMC_CLK_NUM);
367 plt_clk_unregister_parents(data);
371 static struct platform_driver plt_clk_driver = {
373 .name = "clk-pmc-atom",
375 .probe = plt_clk_probe,
376 .remove = plt_clk_remove,
378 builtin_platform_driver(plt_clk_driver);