drivers/clk/zynq/clkc.c

   1 /*
   2  * Zynq clock controller
   3  *
   4  *  Copyright (C) 2012 - 2013 Xilinx
   5  *
   6  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License v2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/clk/zynq.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/of.h>
  24 #include <linux/slab.h>
  25 #include <linux/string.h>
  26 #include <linux/io.h>
  27
  28 static void __iomem *zynq_slcr_base_priv;
  29
  30 #define SLCR_ARMPLL_CTRL                (zynq_slcr_base_priv + 0x100)
  31 #define SLCR_DDRPLL_CTRL                (zynq_slcr_base_priv + 0x104)
  32 #define SLCR_IOPLL_CTRL                 (zynq_slcr_base_priv + 0x108)
  33 #define SLCR_PLL_STATUS                 (zynq_slcr_base_priv + 0x10c)
  34 #define SLCR_ARM_CLK_CTRL               (zynq_slcr_base_priv + 0x120)
  35 #define SLCR_DDR_CLK_CTRL               (zynq_slcr_base_priv + 0x124)
  36 #define SLCR_DCI_CLK_CTRL               (zynq_slcr_base_priv + 0x128)
  37 #define SLCR_APER_CLK_CTRL              (zynq_slcr_base_priv + 0x12c)
  38 #define SLCR_GEM0_CLK_CTRL              (zynq_slcr_base_priv + 0x140)
  39 #define SLCR_GEM1_CLK_CTRL              (zynq_slcr_base_priv + 0x144)
  40 #define SLCR_SMC_CLK_CTRL               (zynq_slcr_base_priv + 0x148)
  41 #define SLCR_LQSPI_CLK_CTRL             (zynq_slcr_base_priv + 0x14c)
  42 #define SLCR_SDIO_CLK_CTRL              (zynq_slcr_base_priv + 0x150)
  43 #define SLCR_UART_CLK_CTRL              (zynq_slcr_base_priv + 0x154)
  44 #define SLCR_SPI_CLK_CTRL               (zynq_slcr_base_priv + 0x158)
  45 #define SLCR_CAN_CLK_CTRL               (zynq_slcr_base_priv + 0x15c)
  46 #define SLCR_CAN_MIOCLK_CTRL            (zynq_slcr_base_priv + 0x160)
  47 #define SLCR_DBG_CLK_CTRL               (zynq_slcr_base_priv + 0x164)
  48 #define SLCR_PCAP_CLK_CTRL              (zynq_slcr_base_priv + 0x168)
  49 #define SLCR_FPGA0_CLK_CTRL             (zynq_slcr_base_priv + 0x170)
  50 #define SLCR_621_TRUE                   (zynq_slcr_base_priv + 0x1c4)
  51 #define SLCR_SWDT_CLK_SEL               (zynq_slcr_base_priv + 0x304)
  52
  53 #define NUM_MIO_PINS    54
  54
  55 enum zynq_clk {
  56         armpll, ddrpll, iopll,
  57         cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
  58         ddr2x, ddr3x, dci,
  59         lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
  60         sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
  61         usb0_aper, usb1_aper, gem0_aper, gem1_aper,
  62         sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
  63         i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
  64         smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
  65
  66 static struct clk *ps_clk;
  67 static struct clk *clks[clk_max];
  68 static struct clk_onecell_data clk_data;
  69
  70 static DEFINE_SPINLOCK(armpll_lock);
  71 static DEFINE_SPINLOCK(ddrpll_lock);
  72 static DEFINE_SPINLOCK(iopll_lock);
  73 static DEFINE_SPINLOCK(armclk_lock);
  74 static DEFINE_SPINLOCK(ddrclk_lock);
  75 static DEFINE_SPINLOCK(dciclk_lock);
  76 static DEFINE_SPINLOCK(gem0clk_lock);
  77 static DEFINE_SPINLOCK(gem1clk_lock);
  78 static DEFINE_SPINLOCK(canclk_lock);
  79 static DEFINE_SPINLOCK(canmioclk_lock);
  80 static DEFINE_SPINLOCK(dbgclk_lock);
  81 static DEFINE_SPINLOCK(aperclk_lock);
  82
  83 static const char dummy_nm[] __initconst = "dummy_name";
  84
  85 static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
  86 static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
  87 static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
  88 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
  89 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
  90 static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
  91         "can0_mio_mux"};
  92 static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
  93         "can1_mio_mux"};
  94 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
  95         dummy_nm};
  96
  97 static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
  98 static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
  99 static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
 100 static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
 101
 102 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
 103                 const char *clk_name, void __iomem *fclk_ctrl_reg,
 104                 const char **parents)
 105 {
 106         struct clk *clk;
 107         char *mux_name;
 108         char *div0_name;
 109         char *div1_name;
 110         spinlock_t *fclk_lock;
 111         spinlock_t *fclk_gate_lock;
 112         void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
 113
 114         fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
 115         if (!fclk_lock)
 116                 goto err;
 117         fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
 118         if (!fclk_gate_lock)
 119                 goto err;
 120         spin_lock_init(fclk_lock);
 121         spin_lock_init(fclk_gate_lock);
 122
 123         mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
 124         div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
 125         div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
 126
 127         clk = clk_register_mux(NULL, mux_name, parents, 4,
 128                         CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
 129                         fclk_lock);
 130
 131         clk = clk_register_divider(NULL, div0_name, mux_name,
 132                         0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
 133                         CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
 134
 135         clk = clk_register_divider(NULL, div1_name, div0_name,
 136                         CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
 137                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 138                         fclk_lock);
 139
 140         clks[fclk] = clk_register_gate(NULL, clk_name,
 141                         div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
 142                         0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
 143         kfree(mux_name);
 144         kfree(div0_name);
 145         kfree(div1_name);
 146
 147         return;
 148
 149 err:
 150         clks[fclk] = ERR_PTR(-ENOMEM);
 151 }
 152
 153 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
 154                 enum zynq_clk clk1, const char *clk_name0,
 155                 const char *clk_name1, void __iomem *clk_ctrl,
 156                 const char **parents, unsigned int two_gates)
 157 {
 158         struct clk *clk;
 159         char *mux_name;
 160         char *div_name;
 161         spinlock_t *lock;
 162
 163         lock = kmalloc(sizeof(*lock), GFP_KERNEL);
 164         if (!lock)
 165                 goto err;
 166         spin_lock_init(lock);
 167
 168         mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
 169         div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
 170
 171         clk = clk_register_mux(NULL, mux_name, parents, 4,
 172                         CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
 173
 174         clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
 175                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
 176
 177         clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
 178                         CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
 179         if (two_gates)
 180                 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
 181                                 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
 182
 183         kfree(mux_name);
 184         kfree(div_name);
 185
 186         return;
 187
 188 err:
 189         clks[clk0] = ERR_PTR(-ENOMEM);
 190         if (two_gates)
 191                 clks[clk1] = ERR_PTR(-ENOMEM);
 192 }
 193
 194 static void __init zynq_clk_setup(struct device_node *np)
 195 {
 196         int i;
 197         u32 tmp;
 198         int ret;
 199         struct clk *clk;
 200         char *clk_name;
 201         const char *clk_output_name[clk_max];
 202         const char *cpu_parents[4];
 203         const char *periph_parents[4];
 204         const char *swdt_ext_clk_mux_parents[2];
 205         const char *can_mio_mux_parents[NUM_MIO_PINS];
 206
 207         pr_info("Zynq clock init\n");
 208
 209         /* get clock output names from DT */
 210         for (i = 0; i < clk_max; i++) {
 211                 if (of_property_read_string_index(np, "clock-output-names",
 212                                   i, &clk_output_name[i])) {
 213                         pr_err("%s: clock output name not in DT\n", __func__);
 214                         BUG();
 215                 }
 216         }
 217         cpu_parents[0] = clk_output_name[armpll];
 218         cpu_parents[1] = clk_output_name[armpll];
 219         cpu_parents[2] = clk_output_name[ddrpll];
 220         cpu_parents[3] = clk_output_name[iopll];
 221         periph_parents[0] = clk_output_name[iopll];
 222         periph_parents[1] = clk_output_name[iopll];
 223         periph_parents[2] = clk_output_name[armpll];
 224         periph_parents[3] = clk_output_name[ddrpll];
 225
 226         /* ps_clk */
 227         ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
 228         if (ret) {
 229                 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
 230                 tmp = 33333333;
 231         }
 232         ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
 233                         tmp);
 234
 235         /* PLLs */
 236         clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
 237                         SLCR_PLL_STATUS, 0, &armpll_lock);
 238         clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
 239                         armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 240                         SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
 241
 242         clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
 243                         SLCR_PLL_STATUS, 1, &ddrpll_lock);
 244         clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
 245                         ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 246                         SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
 247
 248         clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
 249                         SLCR_PLL_STATUS, 2, &iopll_lock);
 250         clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
 251                         iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 252                         SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
 253
 254         /* CPU clocks */
 255         tmp = readl(SLCR_621_TRUE) & 1;
 256         clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
 257                         CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
 258                         &armclk_lock);
 259         clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
 260                         SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 261                         CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
 262
 263         clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
 264                         "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 265                         SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
 266
 267         clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
 268                         1, 2);
 269         clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
 270                         "cpu_3or2x_div", CLK_IGNORE_UNUSED,
 271                         SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
 272
 273         clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
 274                         2 + tmp);
 275         clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
 276                         "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
 277                         26, 0, &armclk_lock);
 278
 279         clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
 280                         4 + 2 * tmp);
 281         clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
 282                         "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
 283                         0, &armclk_lock);
 284
 285         /* Timers */
 286         swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
 287         for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
 288                 int idx = of_property_match_string(np, "clock-names",
 289                                 swdt_ext_clk_input_names[i]);
 290                 if (idx >= 0)
 291                         swdt_ext_clk_mux_parents[i + 1] =
 292                                 of_clk_get_parent_name(np, idx);
 293                 else
 294                         swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
 295         }
 296         clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
 297                         swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
 298                         CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
 299                         &gem0clk_lock);
 300
 301         /* DDR clocks */
 302         clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
 303                         SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
 304                         CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
 305         clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
 306                         "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
 307         clk_prepare_enable(clks[ddr2x]);
 308         clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
 309                         SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
 310                         CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
 311         clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
 312                         "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
 313         clk_prepare_enable(clks[ddr3x]);
 314
 315         clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
 316                         SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 317                         CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
 318         clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
 319                         CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
 320                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 321                         &dciclk_lock);
 322         clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
 323                         CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
 324                         &dciclk_lock);
 325         clk_prepare_enable(clks[dci]);
 326
 327         /* Peripheral clocks */
 328         for (i = fclk0; i <= fclk3; i++)
 329                 zynq_clk_register_fclk(i, clk_output_name[i],
 330                                 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
 331                                 periph_parents);
 332
 333         zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
 334                         SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
 335
 336         zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
 337                         SLCR_SMC_CLK_CTRL, periph_parents, 0);
 338
 339         zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
 340                         SLCR_PCAP_CLK_CTRL, periph_parents, 0);
 341
 342         zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
 343                         clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
 344                         periph_parents, 1);
 345
 346         zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
 347                         clk_output_name[uart1], SLCR_UART_CLK_CTRL,
 348                         periph_parents, 1);
 349
 350         zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
 351                         clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
 352                         periph_parents, 1);
 353
 354         for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
 355                 int idx = of_property_match_string(np, "clock-names",
 356                                 gem0_emio_input_names[i]);
 357                 if (idx >= 0)
 358                         gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
 359                                         idx);
 360         }
 361         clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
 362                         CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
 363                         &gem0clk_lock);
 364         clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
 365                         SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 366                         CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
 367         clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
 368                         CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
 369                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 370                         &gem0clk_lock);
 371         clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
 372                         CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
 373                         &gem0clk_lock);
 374         clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
 375                         "gem0_emio_mux", CLK_SET_RATE_PARENT,
 376                         SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
 377
 378         for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
 379                 int idx = of_property_match_string(np, "clock-names",
 380                                 gem1_emio_input_names[i]);
 381                 if (idx >= 0)
 382                         gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
 383                                         idx);
 384         }
 385         clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
 386                         CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
 387                         &gem1clk_lock);
 388         clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
 389                         SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 390                         CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
 391         clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
 392                         CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
 393                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 394                         &gem1clk_lock);
 395         clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
 396                         CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
 397                         &gem1clk_lock);
 398         clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
 399                         "gem1_emio_mux", CLK_SET_RATE_PARENT,
 400                         SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
 401
 402         tmp = strlen("mio_clk_00x");
 403         clk_name = kmalloc(tmp, GFP_KERNEL);
 404         for (i = 0; i < NUM_MIO_PINS; i++) {
 405                 int idx;
 406
 407                 snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
 408                 idx = of_property_match_string(np, "clock-names", clk_name);
 409                 if (idx >= 0)
 410                         can_mio_mux_parents[i] = of_clk_get_parent_name(np,
 411                                                 idx);
 412                 else
 413                         can_mio_mux_parents[i] = dummy_nm;
 414         }
 415         kfree(clk_name);
 416         clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
 417                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
 418                         &canclk_lock);
 419         clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
 420                         SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 421                         CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
 422         clk = clk_register_divider(NULL, "can_div1", "can_div0",
 423                         CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
 424                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 425                         &canclk_lock);
 426         clk = clk_register_gate(NULL, "can0_gate", "can_div1",
 427                         CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
 428                         &canclk_lock);
 429         clk = clk_register_gate(NULL, "can1_gate", "can_div1",
 430                         CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
 431                         &canclk_lock);
 432         clk = clk_register_mux(NULL, "can0_mio_mux",
 433                         can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
 434                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
 435                         &canmioclk_lock);
 436         clk = clk_register_mux(NULL, "can1_mio_mux",
 437                         can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
 438                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
 439                         0, &canmioclk_lock);
 440         clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
 441                         can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
 442                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
 443                         &canmioclk_lock);
 444         clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
 445                         can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
 446                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
 447                         0, &canmioclk_lock);
 448
 449         for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
 450                 int idx = of_property_match_string(np, "clock-names",
 451                                 dbgtrc_emio_input_names[i]);
 452                 if (idx >= 0)
 453                         dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
 454                                         idx);
 455         }
 456         clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
 457                         CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
 458                         &dbgclk_lock);
 459         clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
 460                         SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 461                         CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
 462         clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
 463                         CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
 464                         &dbgclk_lock);
 465         clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
 466                         "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
 467                         0, 0, &dbgclk_lock);
 468         clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
 469                         clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
 470                         &dbgclk_lock);
 471
 472         /* One gated clock for all APER clocks. */
 473         clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
 474                         clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
 475                         &aperclk_lock);
 476         clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
 477                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
 478                         &aperclk_lock);
 479         clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
 480                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
 481                         &aperclk_lock);
 482         clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
 483                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
 484                         &aperclk_lock);
 485         clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
 486                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
 487                         &aperclk_lock);
 488         clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
 489                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
 490                         &aperclk_lock);
 491         clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
 492                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
 493                         &aperclk_lock);
 494         clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
 495                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
 496                         &aperclk_lock);
 497         clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
 498                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
 499                         &aperclk_lock);
 500         clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
 501                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
 502                         &aperclk_lock);
 503         clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
 504                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
 505                         &aperclk_lock);
 506         clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
 507                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
 508                         &aperclk_lock);
 509         clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
 510                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
 511                         &aperclk_lock);
 512         clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
 513                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
 514                         &aperclk_lock);
 515         clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
 516                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
 517                         &aperclk_lock);
 518         clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
 519                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
 520                         &aperclk_lock);
 521         clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
 522                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
 523                         &aperclk_lock);
 524         clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
 525                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
 526                         &aperclk_lock);
 527
 528         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 529                 if (IS_ERR(clks[i])) {
 530                         pr_err("Zynq clk %d: register failed with %ld\n",
 531                                i, PTR_ERR(clks[i]));
 532                         BUG();
 533                 }
 534         }
 535
 536         clk_data.clks = clks;
 537         clk_data.clk_num = ARRAY_SIZE(clks);
 538         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 539 }
 540
 541 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
 542
 543 void __init zynq_clock_init(void __iomem *slcr_base)
 544 {
 545         zynq_slcr_base_priv = slcr_base;
 546         of_clk_init(NULL);
 547 }