1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2018 Xilinx
7 * Based on drivers/clk/zynq/clkc.c
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
18 #include "clk-zynqmp.h"
20 #define MAX_PARENT 100
22 #define MAX_NAME_LEN 50
24 #define CLK_TYPE_SHIFT 2
26 #define PM_API_PAYLOAD_LEN 3
28 #define NA_PARENT 0xFFFFFFFF
29 #define DUMMY_PARENT 0xFFFFFFFE
31 #define CLK_TYPE_FIELD_LEN 4
32 #define CLK_TOPOLOGY_NODE_OFFSET 16
33 #define NODES_PER_RESP 3
35 #define CLK_TYPE_FIELD_MASK 0xF
36 #define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
37 #define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
39 #define CLK_PARENTS_ID_LEN 16
40 #define CLK_PARENTS_ID_MASK 0xFFFF
42 /* Flags for parents */
43 #define PARENT_CLK_SELF 0
44 #define PARENT_CLK_NODE1 1
45 #define PARENT_CLK_NODE2 2
46 #define PARENT_CLK_NODE3 3
47 #define PARENT_CLK_NODE4 4
48 #define PARENT_CLK_EXTERNAL 5
50 #define END_OF_CLK_NAME "END_OF_CLK"
51 #define END_OF_TOPOLOGY_NODE 1
52 #define END_OF_PARENTS 1
53 #define RESERVED_CLK_NAME ""
55 #define CLK_VALID_MASK 0x1
63 * struct clock_parent - Clock parent
65 * @id: Parent clock ID
69 char name[MAX_NAME_LEN];
75 * struct zynqmp_clock - Clock
76 * @clk_name: Clock name
77 * @valid: Validity flag of clock
78 * @type: Clock type (Output/External)
79 * @node: Clock topology nodes
80 * @num_nodes: Number of nodes present in topology
81 * @parent: Parent of clock
82 * @num_parents: Number of parents of clock
85 char clk_name[MAX_NAME_LEN];
88 struct clock_topology node[MAX_NODES];
90 struct clock_parent parent[MAX_PARENT];
94 static const char clk_type_postfix[][10] = {
98 [TYPE_DIV1] = "_div1",
99 [TYPE_DIV2] = "_div2",
100 [TYPE_FIXEDFACTOR] = "_ff",
104 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
105 const char * const *parents,
107 const struct clock_topology *nodes)
109 [TYPE_INVALID] = NULL,
110 [TYPE_MUX] = zynqmp_clk_register_mux,
111 [TYPE_PLL] = zynqmp_clk_register_pll,
112 [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
113 [TYPE_DIV1] = zynqmp_clk_register_divider,
114 [TYPE_DIV2] = zynqmp_clk_register_divider,
115 [TYPE_GATE] = zynqmp_clk_register_gate
118 static struct zynqmp_clock *clock;
119 static struct clk_hw_onecell_data *zynqmp_data;
120 static unsigned int clock_max_idx;
121 static const struct zynqmp_eemi_ops *eemi_ops;
124 * zynqmp_is_valid_clock() - Check whether clock is valid or not
125 * @clk_id: Clock index
127 * Return: 1 if clock is valid, 0 if clock is invalid else error code
129 static inline int zynqmp_is_valid_clock(u32 clk_id)
131 if (clk_id > clock_max_idx)
134 return clock[clk_id].valid;
138 * zynqmp_get_clock_name() - Get name of clock from Clock index
139 * @clk_id: Clock index
140 * @clk_name: Name of clock
142 * Return: 0 on success else error code
144 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
148 ret = zynqmp_is_valid_clock(clk_id);
150 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
154 return ret == 0 ? -EINVAL : ret;
158 * zynqmp_get_clock_type() - Get type of clock
159 * @clk_id: Clock index
160 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
162 * Return: 0 on success else error code
164 static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
168 ret = zynqmp_is_valid_clock(clk_id);
170 *type = clock[clk_id].type;
174 return ret == 0 ? -EINVAL : ret;
178 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
179 * @nclocks: Number of clocks in system/board.
181 * Call firmware API to get number of clocks.
183 * Return: 0 on success else error code.
185 static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
187 struct zynqmp_pm_query_data qdata = {0};
188 u32 ret_payload[PAYLOAD_ARG_CNT];
191 qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
193 ret = eemi_ops->query_data(qdata, ret_payload);
194 *nclocks = ret_payload[1];
200 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
201 * @clock_id: ID of the clock to be queried
202 * @name: Name of given clock
204 * This function is used to get name of clock specified by given
207 * Return: Returns 0, in case of error name would be 0
209 static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
211 struct zynqmp_pm_query_data qdata = {0};
212 u32 ret_payload[PAYLOAD_ARG_CNT];
214 qdata.qid = PM_QID_CLOCK_GET_NAME;
215 qdata.arg1 = clock_id;
217 eemi_ops->query_data(qdata, ret_payload);
218 memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
224 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
225 * @clock_id: ID of the clock to be queried
226 * @index: Node index of clock topology
227 * @topology: Buffer to store nodes in topology and flags
229 * This function is used to get topology information for the clock
230 * specified by given clock ID.
232 * This API will return 3 node of topology with a single response. To get
233 * other nodes, master should call same API in loop with new
234 * index till error is returned. E.g First call should have
235 * index 0 which will return nodes 0,1 and 2. Next call, index
236 * should be 3 which will return nodes 3,4 and 5 and so on.
238 * Return: 0 on success else error+reason
240 static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
242 struct zynqmp_pm_query_data qdata = {0};
243 u32 ret_payload[PAYLOAD_ARG_CNT];
246 qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
247 qdata.arg1 = clock_id;
250 ret = eemi_ops->query_data(qdata, ret_payload);
251 memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
257 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
259 * @name: Name of this clock
261 * @parents: Name of this clock's parents
262 * @num_parents: Number of parents
263 * @nodes: Clock topology node
265 * Return: clock hardware to the registered clock
267 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
268 const char * const *parents,
270 const struct clock_topology *nodes)
274 struct zynqmp_pm_query_data qdata = {0};
275 u32 ret_payload[PAYLOAD_ARG_CNT];
278 qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
281 ret = eemi_ops->query_data(qdata, ret_payload);
282 mult = ret_payload[1];
283 div = ret_payload[2];
285 hw = clk_hw_register_fixed_factor(NULL, name,
294 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
295 * @clock_id: Clock ID
296 * @index: Parent index
297 * @parents: 3 parents of the given clock
299 * This function is used to get 3 parents for the clock specified by
302 * This API will return 3 parents with a single response. To get
303 * other parents, master should call same API in loop with new
304 * parent index till error is returned. E.g First call should have
305 * index 0 which will return parents 0,1 and 2. Next call, index
306 * should be 3 which will return parent 3,4 and 5 and so on.
308 * Return: 0 on success else error+reason
310 static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
312 struct zynqmp_pm_query_data qdata = {0};
313 u32 ret_payload[PAYLOAD_ARG_CNT];
316 qdata.qid = PM_QID_CLOCK_GET_PARENTS;
317 qdata.arg1 = clock_id;
320 ret = eemi_ops->query_data(qdata, ret_payload);
321 memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
327 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
328 * @clock_id: Clock ID
329 * @attr: Clock attributes
331 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
333 * Return: 0 on success else error+reason
335 static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
337 struct zynqmp_pm_query_data qdata = {0};
338 u32 ret_payload[PAYLOAD_ARG_CNT];
341 qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
342 qdata.arg1 = clock_id;
344 ret = eemi_ops->query_data(qdata, ret_payload);
345 memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
351 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
353 * @topology: Clock topology
354 * @data: Clock topology data received from firmware
355 * @nnodes: Number of nodes
357 * Return: 0 on success else error+reason
359 static int __zynqmp_clock_get_topology(struct clock_topology *topology,
360 u32 *data, u32 *nnodes)
364 for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
365 if (!(data[i] & CLK_TYPE_FIELD_MASK))
366 return END_OF_TOPOLOGY_NODE;
367 topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
368 topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
370 topology[*nnodes].type_flag =
371 FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
379 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
381 * @clk_id: Clock index
382 * @topology: Clock topology
383 * @num_nodes: Number of nodes
385 * Return: 0 on success else error+reason
387 static int zynqmp_clock_get_topology(u32 clk_id,
388 struct clock_topology *topology,
392 u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
395 for (j = 0; j <= MAX_NODES; j += 3) {
396 ret = zynqmp_pm_clock_get_topology(clk_id, j, pm_resp);
399 ret = __zynqmp_clock_get_topology(topology, pm_resp, num_nodes);
400 if (ret == END_OF_TOPOLOGY_NODE)
408 * __zynqmp_clock_get_topology() - Get parents info of clock from firmware
410 * @parents: Clock parents
411 * @data: Clock parents data received from firmware
412 * @nparent: Number of parent
414 * Return: 0 on success else error+reason
416 static int __zynqmp_clock_get_parents(struct clock_parent *parents, u32 *data,
420 struct clock_parent *parent;
422 for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
423 if (data[i] == NA_PARENT)
424 return END_OF_PARENTS;
426 parent = &parents[i];
427 parent->id = data[i] & CLK_PARENTS_ID_MASK;
428 if (data[i] == DUMMY_PARENT) {
429 strcpy(parent->name, "dummy_name");
432 parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
433 if (zynqmp_get_clock_name(parent->id, parent->name))
443 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
444 * @clk_id: Clock index
445 * @parents: Clock parents
446 * @num_parents: Total number of parents
448 * Return: 0 on success else error+reason
450 static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
454 u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
458 /* Get parents from firmware */
459 ret = zynqmp_pm_clock_get_parents(clk_id, j, pm_resp);
463 ret = __zynqmp_clock_get_parents(&parents[j], pm_resp,
465 if (ret == END_OF_PARENTS)
467 j += PM_API_PAYLOAD_LEN;
468 } while (*num_parents <= MAX_PARENT);
474 * zynqmp_get_parent_list() - Create list of parents name
476 * @clk_id: Clock index
477 * @parent_list: List of parent's name
478 * @num_parents: Total number of parents
480 * Return: 0 on success else error+reason
482 static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
483 const char **parent_list, u32 *num_parents)
486 u32 total_parents = clock[clk_id].num_parents;
487 struct clock_topology *clk_nodes;
488 struct clock_parent *parents;
490 clk_nodes = clock[clk_id].node;
491 parents = clock[clk_id].parent;
493 for (i = 0; i < total_parents; i++) {
494 if (!parents[i].flag) {
495 parent_list[i] = parents[i].name;
496 } else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
497 ret = of_property_match_string(np, "clock-names",
500 strcpy(parents[i].name, "dummy_name");
501 parent_list[i] = parents[i].name;
503 strcat(parents[i].name,
504 clk_type_postfix[clk_nodes[parents[i].flag - 1].
506 parent_list[i] = parents[i].name;
510 *num_parents = total_parents;
515 * zynqmp_register_clk_topology() - Register clock topology
516 * @clk_id: Clock index
517 * @clk_name: Clock Name
518 * @num_parents: Total number of parents
519 * @parent_names: List of parents name
521 * Return: Returns either clock hardware or error+reason
523 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
525 const char **parent_names)
529 char *clk_out = NULL;
530 struct clock_topology *nodes;
531 struct clk_hw *hw = NULL;
533 nodes = clock[clk_id].node;
534 num_nodes = clock[clk_id].num_nodes;
536 for (j = 0; j < num_nodes; j++) {
538 * Clock name received from firmware is output clock name.
539 * Intermediate clock names are postfixed with type of clock.
541 if (j != (num_nodes - 1)) {
542 clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name,
543 clk_type_postfix[nodes[j].type]);
545 clk_out = kasprintf(GFP_KERNEL, "%s", clk_name);
548 if (!clk_topology[nodes[j].type])
551 hw = (*clk_topology[nodes[j].type])(clk_out, clk_id,
556 pr_warn_once("%s() %s register fail with %ld\n",
557 __func__, clk_name, PTR_ERR(hw));
559 parent_names[0] = clk_out;
566 * zynqmp_register_clocks() - Register clocks
569 * Return: 0 on success else error code
571 static int zynqmp_register_clocks(struct device_node *np)
574 u32 i, total_parents = 0, type = 0;
575 const char *parent_names[MAX_PARENT];
577 for (i = 0; i < clock_max_idx; i++) {
578 char clk_name[MAX_NAME_LEN];
580 /* get clock name, continue to next clock if name not found */
581 if (zynqmp_get_clock_name(i, clk_name))
584 /* Check if clock is valid and output clock.
585 * Do not register invalid or external clock.
587 ret = zynqmp_get_clock_type(i, &type);
588 if (ret || type != CLK_TYPE_OUTPUT)
591 /* Get parents of clock*/
592 if (zynqmp_get_parent_list(np, i, parent_names,
594 WARN_ONCE(1, "No parents found for %s\n",
599 zynqmp_data->hws[i] =
600 zynqmp_register_clk_topology(i, clk_name,
605 for (i = 0; i < clock_max_idx; i++) {
606 if (IS_ERR(zynqmp_data->hws[i])) {
607 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
608 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
616 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
618 static void zynqmp_get_clock_info(void)
623 for (i = 0; i < clock_max_idx; i++) {
624 zynqmp_pm_clock_get_name(i, clock[i].clk_name);
625 if (!strcmp(clock[i].clk_name, RESERVED_CLK_NAME))
628 ret = zynqmp_pm_clock_get_attributes(i, &attr);
632 clock[i].valid = attr & CLK_VALID_MASK;
633 clock[i].type = attr >> CLK_TYPE_SHIFT ? CLK_TYPE_EXTERNAL :
637 /* Get topology of all clock */
638 for (i = 0; i < clock_max_idx; i++) {
639 ret = zynqmp_get_clock_type(i, &type);
640 if (ret || type != CLK_TYPE_OUTPUT)
643 ret = zynqmp_clock_get_topology(i, clock[i].node,
644 &clock[i].num_nodes);
648 ret = zynqmp_clock_get_parents(i, clock[i].parent,
649 &clock[i].num_parents);
656 * zynqmp_clk_setup() - Setup the clock framework and register clocks
659 * Return: 0 on success else error code
661 static int zynqmp_clk_setup(struct device_node *np)
665 ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
669 zynqmp_data = kzalloc(sizeof(*zynqmp_data) + sizeof(*zynqmp_data) *
670 clock_max_idx, GFP_KERNEL);
674 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
680 zynqmp_get_clock_info();
681 zynqmp_register_clocks(np);
683 zynqmp_data->num = clock_max_idx;
684 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
689 static int zynqmp_clock_probe(struct platform_device *pdev)
692 struct device *dev = &pdev->dev;
694 eemi_ops = zynqmp_pm_get_eemi_ops();
698 ret = zynqmp_clk_setup(dev->of_node);
703 static const struct of_device_id zynqmp_clock_of_match[] = {
704 {.compatible = "xlnx,zynqmp-clk"},
707 MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
709 static struct platform_driver zynqmp_clock_driver = {
711 .name = "zynqmp_clock",
712 .of_match_table = zynqmp_clock_of_match,
714 .probe = zynqmp_clock_probe,
716 module_platform_driver(zynqmp_clock_driver);