1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/clocksource/arm_arch_timer.c
5 * Copyright (C) 2011 ARM Ltd.
9 #define pr_fmt(fmt) "arch_timer: " fmt
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 #include <linux/sched/clock.h>
25 #include <linux/sched_clock.h>
26 #include <linux/acpi.h>
28 #include <asm/arch_timer.h>
31 #include <clocksource/arm_arch_timer.h>
34 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
36 #define CNTACR(n) (0x40 + ((n) * 4))
37 #define CNTACR_RPCT BIT(0)
38 #define CNTACR_RVCT BIT(1)
39 #define CNTACR_RFRQ BIT(2)
40 #define CNTACR_RVOFF BIT(3)
41 #define CNTACR_RWVT BIT(4)
42 #define CNTACR_RWPT BIT(5)
44 #define CNTVCT_LO 0x08
45 #define CNTVCT_HI 0x0c
47 #define CNTP_TVAL 0x28
49 #define CNTV_TVAL 0x38
52 static unsigned arch_timers_present __initdata;
54 static void __iomem *arch_counter_base;
58 struct clock_event_device evt;
61 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
63 static u32 arch_timer_rate;
64 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
66 static struct clock_event_device __percpu *arch_timer_evt;
68 static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
69 static bool arch_timer_c3stop;
70 static bool arch_timer_mem_use_virtual;
71 static bool arch_counter_suspend_stop;
72 static bool vdso_default = true;
74 static cpumask_t evtstrm_available = CPU_MASK_NONE;
75 static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
77 static int __init early_evtstrm_cfg(char *buf)
79 return strtobool(buf, &evtstrm_enable);
81 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
84 * Architected system timer support.
87 static __always_inline
88 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
89 struct clock_event_device *clk)
91 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
92 struct arch_timer *timer = to_arch_timer(clk);
94 case ARCH_TIMER_REG_CTRL:
95 writel_relaxed(val, timer->base + CNTP_CTL);
97 case ARCH_TIMER_REG_TVAL:
98 writel_relaxed(val, timer->base + CNTP_TVAL);
101 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
102 struct arch_timer *timer = to_arch_timer(clk);
104 case ARCH_TIMER_REG_CTRL:
105 writel_relaxed(val, timer->base + CNTV_CTL);
107 case ARCH_TIMER_REG_TVAL:
108 writel_relaxed(val, timer->base + CNTV_TVAL);
112 arch_timer_reg_write_cp15(access, reg, val);
116 static __always_inline
117 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
118 struct clock_event_device *clk)
122 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
123 struct arch_timer *timer = to_arch_timer(clk);
125 case ARCH_TIMER_REG_CTRL:
126 val = readl_relaxed(timer->base + CNTP_CTL);
128 case ARCH_TIMER_REG_TVAL:
129 val = readl_relaxed(timer->base + CNTP_TVAL);
132 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
133 struct arch_timer *timer = to_arch_timer(clk);
135 case ARCH_TIMER_REG_CTRL:
136 val = readl_relaxed(timer->base + CNTV_CTL);
138 case ARCH_TIMER_REG_TVAL:
139 val = readl_relaxed(timer->base + CNTV_TVAL);
143 val = arch_timer_reg_read_cp15(access, reg);
149 static notrace u64 arch_counter_get_cntpct_stable(void)
151 return __arch_counter_get_cntpct_stable();
154 static notrace u64 arch_counter_get_cntpct(void)
156 return __arch_counter_get_cntpct();
159 static notrace u64 arch_counter_get_cntvct_stable(void)
161 return __arch_counter_get_cntvct_stable();
164 static notrace u64 arch_counter_get_cntvct(void)
166 return __arch_counter_get_cntvct();
170 * Default to cp15 based access because arm64 uses this function for
171 * sched_clock() before DT is probed and the cp15 method is guaranteed
172 * to exist on arm64. arm doesn't use this before DT is probed so even
173 * if we don't have the cp15 accessors we won't have a problem.
175 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
176 EXPORT_SYMBOL_GPL(arch_timer_read_counter);
178 static u64 arch_counter_read(struct clocksource *cs)
180 return arch_timer_read_counter();
183 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
185 return arch_timer_read_counter();
188 static struct clocksource clocksource_counter = {
189 .name = "arch_sys_counter",
191 .read = arch_counter_read,
192 .mask = CLOCKSOURCE_MASK(56),
193 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
196 static struct cyclecounter cyclecounter __ro_after_init = {
197 .read = arch_counter_read_cc,
198 .mask = CLOCKSOURCE_MASK(56),
201 struct ate_acpi_oem_info {
202 char oem_id[ACPI_OEM_ID_SIZE + 1];
203 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
207 #ifdef CONFIG_FSL_ERRATUM_A008585
209 * The number of retries is an arbitrary value well beyond the highest number
210 * of iterations the loop has been observed to take.
212 #define __fsl_a008585_read_reg(reg) ({ \
214 int _retries = 200; \
217 _old = read_sysreg(reg); \
218 _new = read_sysreg(reg); \
220 } while (unlikely(_old != _new) && _retries); \
222 WARN_ON_ONCE(!_retries); \
226 static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
228 return __fsl_a008585_read_reg(cntp_tval_el0);
231 static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
233 return __fsl_a008585_read_reg(cntv_tval_el0);
236 static u64 notrace fsl_a008585_read_cntpct_el0(void)
238 return __fsl_a008585_read_reg(cntpct_el0);
241 static u64 notrace fsl_a008585_read_cntvct_el0(void)
243 return __fsl_a008585_read_reg(cntvct_el0);
247 #ifdef CONFIG_HISILICON_ERRATUM_161010101
249 * Verify whether the value of the second read is larger than the first by
250 * less than 32 is the only way to confirm the value is correct, so clear the
251 * lower 5 bits to check whether the difference is greater than 32 or not.
252 * Theoretically the erratum should not occur more than twice in succession
253 * when reading the system counter, but it is possible that some interrupts
254 * may lead to more than twice read errors, triggering the warning, so setting
255 * the number of retries far beyond the number of iterations the loop has been
258 #define __hisi_161010101_read_reg(reg) ({ \
263 _old = read_sysreg(reg); \
264 _new = read_sysreg(reg); \
266 } while (unlikely((_new - _old) >> 5) && _retries); \
268 WARN_ON_ONCE(!_retries); \
272 static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
274 return __hisi_161010101_read_reg(cntp_tval_el0);
277 static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
279 return __hisi_161010101_read_reg(cntv_tval_el0);
282 static u64 notrace hisi_161010101_read_cntpct_el0(void)
284 return __hisi_161010101_read_reg(cntpct_el0);
287 static u64 notrace hisi_161010101_read_cntvct_el0(void)
289 return __hisi_161010101_read_reg(cntvct_el0);
292 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
294 * Note that trailing spaces are required to properly match
295 * the OEM table information.
299 .oem_table_id = "HIP05 ",
304 .oem_table_id = "HIP06 ",
309 .oem_table_id = "HIP07 ",
312 { /* Sentinel indicating the end of the OEM array */ },
316 #ifdef CONFIG_ARM64_ERRATUM_858921
317 static u64 notrace arm64_858921_read_cntpct_el0(void)
321 old = read_sysreg(cntpct_el0);
322 new = read_sysreg(cntpct_el0);
323 return (((old ^ new) >> 32) & 1) ? old : new;
326 static u64 notrace arm64_858921_read_cntvct_el0(void)
330 old = read_sysreg(cntvct_el0);
331 new = read_sysreg(cntvct_el0);
332 return (((old ^ new) >> 32) & 1) ? old : new;
336 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
338 * The low bits of the counter registers are indeterminate while bit 10 or
339 * greater is rolling over. Since the counter value can jump both backward
340 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
341 * with all ones or all zeros in the low bits. Bound the loop by the maximum
342 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
344 #define __sun50i_a64_read_reg(reg) ({ \
346 int _retries = 150; \
349 _val = read_sysreg(reg); \
351 } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
353 WARN_ON_ONCE(!_retries); \
357 static u64 notrace sun50i_a64_read_cntpct_el0(void)
359 return __sun50i_a64_read_reg(cntpct_el0);
362 static u64 notrace sun50i_a64_read_cntvct_el0(void)
364 return __sun50i_a64_read_reg(cntvct_el0);
367 static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
369 return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
372 static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
374 return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
378 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
379 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
380 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
382 static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
384 static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
385 struct clock_event_device *clk)
390 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
391 ctrl |= ARCH_TIMER_CTRL_ENABLE;
392 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
394 if (access == ARCH_TIMER_PHYS_ACCESS) {
395 cval = evt + arch_counter_get_cntpct();
396 write_sysreg(cval, cntp_cval_el0);
398 cval = evt + arch_counter_get_cntvct();
399 write_sysreg(cval, cntv_cval_el0);
402 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
405 static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
406 struct clock_event_device *clk)
408 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
412 static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
413 struct clock_event_device *clk)
415 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
419 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
420 #ifdef CONFIG_FSL_ERRATUM_A008585
422 .match_type = ate_match_dt,
423 .id = "fsl,erratum-a008585",
424 .desc = "Freescale erratum a005858",
425 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
426 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
427 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
428 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
429 .set_next_event_phys = erratum_set_next_event_tval_phys,
430 .set_next_event_virt = erratum_set_next_event_tval_virt,
433 #ifdef CONFIG_HISILICON_ERRATUM_161010101
435 .match_type = ate_match_dt,
436 .id = "hisilicon,erratum-161010101",
437 .desc = "HiSilicon erratum 161010101",
438 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
439 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
440 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
441 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
442 .set_next_event_phys = erratum_set_next_event_tval_phys,
443 .set_next_event_virt = erratum_set_next_event_tval_virt,
446 .match_type = ate_match_acpi_oem_info,
447 .id = hisi_161010101_oem_info,
448 .desc = "HiSilicon erratum 161010101",
449 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
450 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
451 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
452 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
453 .set_next_event_phys = erratum_set_next_event_tval_phys,
454 .set_next_event_virt = erratum_set_next_event_tval_virt,
457 #ifdef CONFIG_ARM64_ERRATUM_858921
459 .match_type = ate_match_local_cap_id,
460 .id = (void *)ARM64_WORKAROUND_858921,
461 .desc = "ARM erratum 858921",
462 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
463 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
466 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
468 .match_type = ate_match_dt,
469 .id = "allwinner,erratum-unknown1",
470 .desc = "Allwinner erratum UNKNOWN1",
471 .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
472 .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
473 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
474 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
475 .set_next_event_phys = erratum_set_next_event_tval_phys,
476 .set_next_event_virt = erratum_set_next_event_tval_virt,
481 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
485 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
488 const struct device_node *np = arg;
490 return of_property_read_bool(np, wa->id);
494 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
497 return this_cpu_has_cap((uintptr_t)wa->id);
502 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
505 static const struct ate_acpi_oem_info empty_oem_info = {};
506 const struct ate_acpi_oem_info *info = wa->id;
507 const struct acpi_table_header *table = arg;
509 /* Iterate over the ACPI OEM info array, looking for a match */
510 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
511 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
512 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
513 info->oem_revision == table->oem_revision)
522 static const struct arch_timer_erratum_workaround *
523 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
524 ate_match_fn_t match_fn,
529 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
530 if (ool_workarounds[i].match_type != type)
533 if (match_fn(&ool_workarounds[i], arg))
534 return &ool_workarounds[i];
541 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
547 __this_cpu_write(timer_unstable_counter_workaround, wa);
549 for_each_possible_cpu(i)
550 per_cpu(timer_unstable_counter_workaround, i) = wa;
553 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
554 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
557 * Don't use the vdso fastpath if errata require using the
558 * out-of-line counter accessor. We may change our mind pretty
559 * late in the game (with a per-CPU erratum, for example), so
560 * change both the default value and the vdso itself.
562 if (wa->read_cntvct_el0) {
563 clocksource_counter.archdata.vdso_direct = false;
564 vdso_default = false;
568 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
571 const struct arch_timer_erratum_workaround *wa, *__wa;
572 ate_match_fn_t match_fn = NULL;
577 match_fn = arch_timer_check_dt_erratum;
579 case ate_match_local_cap_id:
580 match_fn = arch_timer_check_local_cap_erratum;
583 case ate_match_acpi_oem_info:
584 match_fn = arch_timer_check_acpi_oem_erratum;
591 wa = arch_timer_iterate_errata(type, match_fn, arg);
595 __wa = __this_cpu_read(timer_unstable_counter_workaround);
596 if (__wa && wa != __wa)
597 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
598 wa->desc, __wa->desc);
603 arch_timer_enable_workaround(wa, local);
604 pr_info("Enabling %s workaround for %s\n",
605 local ? "local" : "global", wa->desc);
608 static bool arch_timer_this_cpu_has_cntvct_wa(void)
610 return has_erratum_handler(read_cntvct_el0);
613 static bool arch_timer_counter_has_wa(void)
615 return atomic_read(&timer_unstable_counter_workaround_in_use);
618 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
619 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
620 #define arch_timer_counter_has_wa() ({false;})
621 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
623 static __always_inline irqreturn_t timer_handler(const int access,
624 struct clock_event_device *evt)
628 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
629 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
630 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
631 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
632 evt->event_handler(evt);
639 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
641 struct clock_event_device *evt = dev_id;
643 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
646 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
648 struct clock_event_device *evt = dev_id;
650 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
653 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
655 struct clock_event_device *evt = dev_id;
657 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
660 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
662 struct clock_event_device *evt = dev_id;
664 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
667 static __always_inline int timer_shutdown(const int access,
668 struct clock_event_device *clk)
672 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
673 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
674 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
679 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
681 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
684 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
686 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
689 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
691 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
694 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
696 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
699 static __always_inline void set_next_event(const int access, unsigned long evt,
700 struct clock_event_device *clk)
703 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
704 ctrl |= ARCH_TIMER_CTRL_ENABLE;
705 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
706 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
707 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
710 static int arch_timer_set_next_event_virt(unsigned long evt,
711 struct clock_event_device *clk)
713 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
717 static int arch_timer_set_next_event_phys(unsigned long evt,
718 struct clock_event_device *clk)
720 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
724 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
725 struct clock_event_device *clk)
727 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
731 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
732 struct clock_event_device *clk)
734 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
738 static void __arch_timer_setup(unsigned type,
739 struct clock_event_device *clk)
741 clk->features = CLOCK_EVT_FEAT_ONESHOT;
743 if (type == ARCH_TIMER_TYPE_CP15) {
744 typeof(clk->set_next_event) sne;
746 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
748 if (arch_timer_c3stop)
749 clk->features |= CLOCK_EVT_FEAT_C3STOP;
750 clk->name = "arch_sys_timer";
752 clk->cpumask = cpumask_of(smp_processor_id());
753 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
754 switch (arch_timer_uses_ppi) {
755 case ARCH_TIMER_VIRT_PPI:
756 clk->set_state_shutdown = arch_timer_shutdown_virt;
757 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
758 sne = erratum_handler(set_next_event_virt);
760 case ARCH_TIMER_PHYS_SECURE_PPI:
761 case ARCH_TIMER_PHYS_NONSECURE_PPI:
762 case ARCH_TIMER_HYP_PPI:
763 clk->set_state_shutdown = arch_timer_shutdown_phys;
764 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
765 sne = erratum_handler(set_next_event_phys);
771 clk->set_next_event = sne;
773 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
774 clk->name = "arch_mem_timer";
776 clk->cpumask = cpu_possible_mask;
777 if (arch_timer_mem_use_virtual) {
778 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
779 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
780 clk->set_next_event =
781 arch_timer_set_next_event_virt_mem;
783 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
784 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
785 clk->set_next_event =
786 arch_timer_set_next_event_phys_mem;
790 clk->set_state_shutdown(clk);
792 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
795 static void arch_timer_evtstrm_enable(int divider)
797 u32 cntkctl = arch_timer_get_cntkctl();
799 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
800 /* Set the divider and enable virtual event stream */
801 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
802 | ARCH_TIMER_VIRT_EVT_EN;
803 arch_timer_set_cntkctl(cntkctl);
805 cpu_set_named_feature(EVTSTRM);
807 elf_hwcap |= HWCAP_EVTSTRM;
810 compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
812 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
815 static void arch_timer_configure_evtstream(void)
817 int evt_stream_div, pos;
819 /* Find the closest power of two to the divisor */
820 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
821 pos = fls(evt_stream_div);
822 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
824 /* enable event stream */
825 arch_timer_evtstrm_enable(min(pos, 15));
828 static void arch_counter_set_user_access(void)
830 u32 cntkctl = arch_timer_get_cntkctl();
832 /* Disable user access to the timers and both counters */
833 /* Also disable virtual event stream */
834 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
835 | ARCH_TIMER_USR_VT_ACCESS_EN
836 | ARCH_TIMER_USR_VCT_ACCESS_EN
837 | ARCH_TIMER_VIRT_EVT_EN
838 | ARCH_TIMER_USR_PCT_ACCESS_EN);
841 * Enable user access to the virtual counter if it doesn't
842 * need to be workaround. The vdso may have been already
845 if (arch_timer_this_cpu_has_cntvct_wa())
846 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
848 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
850 arch_timer_set_cntkctl(cntkctl);
853 static bool arch_timer_has_nonsecure_ppi(void)
855 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
856 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
859 static u32 check_ppi_trigger(int irq)
861 u32 flags = irq_get_trigger_type(irq);
863 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
864 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
865 pr_warn("WARNING: Please fix your firmware\n");
866 flags = IRQF_TRIGGER_LOW;
872 static int arch_timer_starting_cpu(unsigned int cpu)
874 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
877 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
879 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
880 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
882 if (arch_timer_has_nonsecure_ppi()) {
883 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
884 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
888 arch_counter_set_user_access();
890 arch_timer_configure_evtstream();
896 * For historical reasons, when probing with DT we use whichever (non-zero)
897 * rate was probed first, and don't verify that others match. If the first node
898 * probed has a clock-frequency property, this overrides the HW register.
900 static void arch_timer_of_configure_rate(u32 rate, struct device_node *np)
902 /* Who has more than one independent system counter? */
906 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
907 arch_timer_rate = rate;
909 /* Check the timer frequency. */
910 if (arch_timer_rate == 0)
911 pr_warn("frequency not available\n");
914 static void arch_timer_banner(unsigned type)
916 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
917 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
918 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
920 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
921 (unsigned long)arch_timer_rate / 1000000,
922 (unsigned long)(arch_timer_rate / 10000) % 100,
923 type & ARCH_TIMER_TYPE_CP15 ?
924 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
926 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
927 type & ARCH_TIMER_TYPE_MEM ?
928 arch_timer_mem_use_virtual ? "virt" : "phys" :
932 u32 arch_timer_get_rate(void)
934 return arch_timer_rate;
937 bool arch_timer_evtstrm_available(void)
940 * We might get called from a preemptible context. This is fine
941 * because availability of the event stream should be always the same
942 * for a preemptible context and context where we might resume a task.
944 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
947 static u64 arch_counter_get_cntvct_mem(void)
949 u32 vct_lo, vct_hi, tmp_hi;
952 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
953 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
954 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
955 } while (vct_hi != tmp_hi);
957 return ((u64) vct_hi << 32) | vct_lo;
960 static struct arch_timer_kvm_info arch_timer_kvm_info;
962 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
964 return &arch_timer_kvm_info;
967 static void __init arch_counter_register(unsigned type)
971 /* Register the CP15 based counter if we have one */
972 if (type & ARCH_TIMER_TYPE_CP15) {
975 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
976 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
977 if (arch_timer_counter_has_wa())
978 rd = arch_counter_get_cntvct_stable;
980 rd = arch_counter_get_cntvct;
982 if (arch_timer_counter_has_wa())
983 rd = arch_counter_get_cntpct_stable;
985 rd = arch_counter_get_cntpct;
988 arch_timer_read_counter = rd;
989 clocksource_counter.archdata.vdso_direct = vdso_default;
991 arch_timer_read_counter = arch_counter_get_cntvct_mem;
994 if (!arch_counter_suspend_stop)
995 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
996 start_count = arch_timer_read_counter();
997 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
998 cyclecounter.mult = clocksource_counter.mult;
999 cyclecounter.shift = clocksource_counter.shift;
1000 timecounter_init(&arch_timer_kvm_info.timecounter,
1001 &cyclecounter, start_count);
1003 /* 56 bits minimum, so we assume worst case rollover */
1004 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
1007 static void arch_timer_stop(struct clock_event_device *clk)
1009 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1011 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1012 if (arch_timer_has_nonsecure_ppi())
1013 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1015 clk->set_state_shutdown(clk);
1018 static int arch_timer_dying_cpu(unsigned int cpu)
1020 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1022 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1024 arch_timer_stop(clk);
1028 #ifdef CONFIG_CPU_PM
1029 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1030 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1031 unsigned long action, void *hcpu)
1033 if (action == CPU_PM_ENTER) {
1034 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1036 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1037 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1038 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1041 if (cpu_have_named_feature(EVTSTRM))
1043 if (elf_hwcap & HWCAP_EVTSTRM)
1045 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1050 static struct notifier_block arch_timer_cpu_pm_notifier = {
1051 .notifier_call = arch_timer_cpu_pm_notify,
1054 static int __init arch_timer_cpu_pm_init(void)
1056 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1059 static void __init arch_timer_cpu_pm_deinit(void)
1061 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1065 static int __init arch_timer_cpu_pm_init(void)
1070 static void __init arch_timer_cpu_pm_deinit(void)
1075 static int __init arch_timer_register(void)
1080 arch_timer_evt = alloc_percpu(struct clock_event_device);
1081 if (!arch_timer_evt) {
1086 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1087 switch (arch_timer_uses_ppi) {
1088 case ARCH_TIMER_VIRT_PPI:
1089 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1090 "arch_timer", arch_timer_evt);
1092 case ARCH_TIMER_PHYS_SECURE_PPI:
1093 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1094 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1095 "arch_timer", arch_timer_evt);
1096 if (!err && arch_timer_has_nonsecure_ppi()) {
1097 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1098 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1099 "arch_timer", arch_timer_evt);
1101 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1105 case ARCH_TIMER_HYP_PPI:
1106 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1107 "arch_timer", arch_timer_evt);
1114 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1118 err = arch_timer_cpu_pm_init();
1120 goto out_unreg_notify;
1122 /* Register and immediately configure the timer on the boot CPU */
1123 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1124 "clockevents/arm/arch_timer:starting",
1125 arch_timer_starting_cpu, arch_timer_dying_cpu);
1127 goto out_unreg_cpupm;
1131 arch_timer_cpu_pm_deinit();
1134 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1135 if (arch_timer_has_nonsecure_ppi())
1136 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1140 free_percpu(arch_timer_evt);
1145 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1149 struct arch_timer *t;
1151 t = kzalloc(sizeof(*t), GFP_KERNEL);
1157 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1159 if (arch_timer_mem_use_virtual)
1160 func = arch_timer_handler_virt_mem;
1162 func = arch_timer_handler_phys_mem;
1164 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1166 pr_err("Failed to request mem timer irq\n");
1173 static const struct of_device_id arch_timer_of_match[] __initconst = {
1174 { .compatible = "arm,armv7-timer", },
1175 { .compatible = "arm,armv8-timer", },
1179 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1180 { .compatible = "arm,armv7-timer-mem", },
1184 static bool __init arch_timer_needs_of_probing(void)
1186 struct device_node *dn;
1187 bool needs_probing = false;
1188 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1190 /* We have two timers, and both device-tree nodes are probed. */
1191 if ((arch_timers_present & mask) == mask)
1195 * Only one type of timer is probed,
1196 * check if we have another type of timer node in device-tree.
1198 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1199 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1201 dn = of_find_matching_node(NULL, arch_timer_of_match);
1203 if (dn && of_device_is_available(dn))
1204 needs_probing = true;
1208 return needs_probing;
1211 static int __init arch_timer_common_init(void)
1213 arch_timer_banner(arch_timers_present);
1214 arch_counter_register(arch_timers_present);
1215 return arch_timer_arch_init();
1219 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1221 * If HYP mode is available, we know that the physical timer
1222 * has been configured to be accessible from PL1. Use it, so
1223 * that a guest can use the virtual timer instead.
1225 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1226 * accesses to CNTP_*_EL1 registers are silently redirected to
1227 * their CNTHP_*_EL2 counterparts, and use a different PPI
1230 * If no interrupt provided for virtual timer, we'll have to
1231 * stick to the physical timer. It'd better be accessible...
1232 * For arm64 we never use the secure interrupt.
1234 * Return: a suitable PPI type for the current system.
1236 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1238 if (is_kernel_in_hyp_mode())
1239 return ARCH_TIMER_HYP_PPI;
1241 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1242 return ARCH_TIMER_VIRT_PPI;
1244 if (IS_ENABLED(CONFIG_ARM64))
1245 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1247 return ARCH_TIMER_PHYS_SECURE_PPI;
1250 static void __init arch_timer_populate_kvm_info(void)
1252 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1253 if (is_kernel_in_hyp_mode())
1254 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1257 static int __init arch_timer_of_init(struct device_node *np)
1262 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1263 pr_warn("multiple nodes in dt, skipping\n");
1267 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1268 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1269 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
1271 arch_timer_populate_kvm_info();
1273 rate = arch_timer_get_cntfrq();
1274 arch_timer_of_configure_rate(rate, np);
1276 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1278 /* Check for globally applicable workarounds */
1279 arch_timer_check_ool_workaround(ate_match_dt, np);
1282 * If we cannot rely on firmware initializing the timer registers then
1283 * we should use the physical timers instead.
1285 if (IS_ENABLED(CONFIG_ARM) &&
1286 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1287 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1289 arch_timer_uses_ppi = arch_timer_select_ppi();
1291 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1292 pr_err("No interrupt available, giving up\n");
1296 /* On some systems, the counter stops ticking when in suspend. */
1297 arch_counter_suspend_stop = of_property_read_bool(np,
1298 "arm,no-tick-in-suspend");
1300 ret = arch_timer_register();
1304 if (arch_timer_needs_of_probing())
1307 return arch_timer_common_init();
1309 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1310 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1313 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1318 base = ioremap(frame->cntbase, frame->size);
1320 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1324 rate = readl_relaxed(base + CNTFRQ);
1331 static struct arch_timer_mem_frame * __init
1332 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1334 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1335 void __iomem *cntctlbase;
1339 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1341 pr_err("Can't map CNTCTLBase @ %pa\n",
1342 &timer_mem->cntctlbase);
1346 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1349 * Try to find a virtual capable frame. Otherwise fall back to a
1350 * physical capable frame.
1352 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1353 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1354 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1356 frame = &timer_mem->frame[i];
1360 /* Try enabling everything, and see what sticks */
1361 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1362 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1364 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1365 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1367 arch_timer_mem_use_virtual = true;
1371 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1377 iounmap(cntctlbase);
1383 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1388 if (arch_timer_mem_use_virtual)
1389 irq = frame->virt_irq;
1391 irq = frame->phys_irq;
1394 pr_err("Frame missing %s irq.\n",
1395 arch_timer_mem_use_virtual ? "virt" : "phys");
1399 if (!request_mem_region(frame->cntbase, frame->size,
1403 base = ioremap(frame->cntbase, frame->size);
1405 pr_err("Can't map frame's registers\n");
1409 ret = arch_timer_mem_register(base, irq);
1415 arch_counter_base = base;
1416 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1421 static int __init arch_timer_mem_of_init(struct device_node *np)
1423 struct arch_timer_mem *timer_mem;
1424 struct arch_timer_mem_frame *frame;
1425 struct device_node *frame_node;
1426 struct resource res;
1430 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1434 if (of_address_to_resource(np, 0, &res))
1436 timer_mem->cntctlbase = res.start;
1437 timer_mem->size = resource_size(&res);
1439 for_each_available_child_of_node(np, frame_node) {
1441 struct arch_timer_mem_frame *frame;
1443 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1444 pr_err(FW_BUG "Missing frame-number.\n");
1445 of_node_put(frame_node);
1448 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1449 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1450 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1451 of_node_put(frame_node);
1454 frame = &timer_mem->frame[n];
1457 pr_err(FW_BUG "Duplicated frame-number.\n");
1458 of_node_put(frame_node);
1462 if (of_address_to_resource(frame_node, 0, &res)) {
1463 of_node_put(frame_node);
1466 frame->cntbase = res.start;
1467 frame->size = resource_size(&res);
1469 frame->virt_irq = irq_of_parse_and_map(frame_node,
1470 ARCH_TIMER_VIRT_SPI);
1471 frame->phys_irq = irq_of_parse_and_map(frame_node,
1472 ARCH_TIMER_PHYS_SPI);
1474 frame->valid = true;
1477 frame = arch_timer_mem_find_best_frame(timer_mem);
1479 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1480 &timer_mem->cntctlbase);
1485 rate = arch_timer_mem_frame_get_cntfrq(frame);
1486 arch_timer_of_configure_rate(rate, np);
1488 ret = arch_timer_mem_frame_register(frame);
1489 if (!ret && !arch_timer_needs_of_probing())
1490 ret = arch_timer_common_init();
1495 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1496 arch_timer_mem_of_init);
1498 #ifdef CONFIG_ACPI_GTDT
1500 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1502 struct arch_timer_mem_frame *frame;
1506 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1507 frame = &timer_mem->frame[i];
1512 rate = arch_timer_mem_frame_get_cntfrq(frame);
1513 if (rate == arch_timer_rate)
1516 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1518 (unsigned long)rate, (unsigned long)arch_timer_rate);
1526 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1528 struct arch_timer_mem *timers, *timer;
1529 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1530 int timer_count, i, ret = 0;
1532 timers = kcalloc(platform_timer_count, sizeof(*timers),
1537 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1538 if (ret || !timer_count)
1542 * While unlikely, it's theoretically possible that none of the frames
1543 * in a timer expose the combination of feature we want.
1545 for (i = 0; i < timer_count; i++) {
1548 frame = arch_timer_mem_find_best_frame(timer);
1552 ret = arch_timer_mem_verify_cntfrq(timer);
1554 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1558 if (!best_frame) /* implies !frame */
1560 * Only complain about missing suitable frames if we
1561 * haven't already found one in a previous iteration.
1563 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1564 &timer->cntctlbase);
1568 ret = arch_timer_mem_frame_register(best_frame);
1574 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1575 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1577 int ret, platform_timer_count;
1579 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1580 pr_warn("already initialized, skipping\n");
1584 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1586 ret = acpi_gtdt_init(table, &platform_timer_count);
1588 pr_err("Failed to init GTDT table.\n");
1592 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1593 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1595 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1596 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1598 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1599 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1601 arch_timer_populate_kvm_info();
1604 * When probing via ACPI, we have no mechanism to override the sysreg
1605 * CNTFRQ value. This *must* be correct.
1607 arch_timer_rate = arch_timer_get_cntfrq();
1608 if (!arch_timer_rate) {
1609 pr_err(FW_BUG "frequency not available.\n");
1613 arch_timer_uses_ppi = arch_timer_select_ppi();
1614 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1615 pr_err("No interrupt available, giving up\n");
1619 /* Always-on capability */
1620 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1622 /* Check for globally applicable workarounds */
1623 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1625 ret = arch_timer_register();
1629 if (platform_timer_count &&
1630 arch_timer_mem_acpi_init(platform_timer_count))
1631 pr_err("Failed to initialize memory-mapped timer.\n");
1633 return arch_timer_common_init();
1635 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);