drivers/clocksource/exynos_mct.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* linux/arch/arm/mach-exynos4/mct.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * EXYNOS4 MCT(Multi-Core Timer) support
   8 */
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/irq.h>
  12 #include <linux/err.h>
  13 #include <linux/clk.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/cpu.h>
  16 #include <linux/delay.h>
  17 #include <linux/percpu.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/clocksource.h>
  22 #include <linux/sched_clock.h>
  23
  24 #define EXYNOS4_MCTREG(x)               (x)
  25 #define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
  26 #define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
  27 #define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
  28 #define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
  29 #define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
  30 #define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
  31 #define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
  32 #define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
  33 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
  34 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
  35 #define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
  36 #define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
  37 #define EXYNOS4_MCT_L_MASK              (0xffffff00)
  38
  39 #define MCT_L_TCNTB_OFFSET              (0x00)
  40 #define MCT_L_ICNTB_OFFSET              (0x08)
  41 #define MCT_L_TCON_OFFSET               (0x20)
  42 #define MCT_L_INT_CSTAT_OFFSET          (0x30)
  43 #define MCT_L_INT_ENB_OFFSET            (0x34)
  44 #define MCT_L_WSTAT_OFFSET              (0x40)
  45 #define MCT_G_TCON_START                (1 << 8)
  46 #define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
  47 #define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
  48 #define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
  49 #define MCT_L_TCON_INT_START            (1 << 1)
  50 #define MCT_L_TCON_TIMER_START          (1 << 0)
  51
  52 #define TICK_BASE_CNT   1
  53
  54 enum {
  55         MCT_INT_SPI,
  56         MCT_INT_PPI
  57 };
  58
  59 enum {
  60         MCT_G0_IRQ,
  61         MCT_G1_IRQ,
  62         MCT_G2_IRQ,
  63         MCT_G3_IRQ,
  64         MCT_L0_IRQ,
  65         MCT_L1_IRQ,
  66         MCT_L2_IRQ,
  67         MCT_L3_IRQ,
  68         MCT_L4_IRQ,
  69         MCT_L5_IRQ,
  70         MCT_L6_IRQ,
  71         MCT_L7_IRQ,
  72         MCT_NR_IRQS,
  73 };
  74
  75 static void __iomem *reg_base;
  76 static unsigned long clk_rate;
  77 static unsigned int mct_int_type;
  78 static int mct_irqs[MCT_NR_IRQS];
  79
  80 struct mct_clock_event_device {
  81         struct clock_event_device evt;
  82         unsigned long base;
  83         char name[10];
  84 };
  85
  86 static void exynos4_mct_write(unsigned int value, unsigned long offset)
  87 {
  88         unsigned long stat_addr;
  89         u32 mask;
  90         u32 i;
  91
  92         writel_relaxed(value, reg_base + offset);
  93
  94         if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
  95                 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
  96                 switch (offset & ~EXYNOS4_MCT_L_MASK) {
  97                 case MCT_L_TCON_OFFSET:
  98                         mask = 1 << 3;          /* L_TCON write status */
  99                         break;
 100                 case MCT_L_ICNTB_OFFSET:
 101                         mask = 1 << 1;          /* L_ICNTB write status */
 102                         break;
 103                 case MCT_L_TCNTB_OFFSET:
 104                         mask = 1 << 0;          /* L_TCNTB write status */
 105                         break;
 106                 default:
 107                         return;
 108                 }
 109         } else {
 110                 switch (offset) {
 111                 case EXYNOS4_MCT_G_TCON:
 112                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 113                         mask = 1 << 16;         /* G_TCON write status */
 114                         break;
 115                 case EXYNOS4_MCT_G_COMP0_L:
 116                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 117                         mask = 1 << 0;          /* G_COMP0_L write status */
 118                         break;
 119                 case EXYNOS4_MCT_G_COMP0_U:
 120                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 121                         mask = 1 << 1;          /* G_COMP0_U write status */
 122                         break;
 123                 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
 124                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 125                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
 126                         break;
 127                 case EXYNOS4_MCT_G_CNT_L:
 128                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 129                         mask = 1 << 0;          /* G_CNT_L write status */
 130                         break;
 131                 case EXYNOS4_MCT_G_CNT_U:
 132                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 133                         mask = 1 << 1;          /* G_CNT_U write status */
 134                         break;
 135                 default:
 136                         return;
 137                 }
 138         }
 139
 140         /* Wait maximum 1 ms until written values are applied */
 141         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
 142                 if (readl_relaxed(reg_base + stat_addr) & mask) {
 143                         writel_relaxed(mask, reg_base + stat_addr);
 144                         return;
 145                 }
 146
 147         panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 148 }
 149
 150 /* Clocksource handling */
 151 static void exynos4_mct_frc_start(void)
 152 {
 153         u32 reg;
 154
 155         reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 156         reg |= MCT_G_TCON_START;
 157         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 158 }
 159
 160 /**
 161  * exynos4_read_count_64 - Read all 64-bits of the global counter
 162  *
 163  * This will read all 64-bits of the global counter taking care to make sure
 164  * that the upper and lower half match.  Note that reading the MCT can be quite
 165  * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
 166  * only) version when possible.
 167  *
 168  * Returns the number of cycles in the global counter.
 169  */
 170 static u64 exynos4_read_count_64(void)
 171 {
 172         unsigned int lo, hi;
 173         u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 174
 175         do {
 176                 hi = hi2;
 177                 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
 178                 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 179         } while (hi != hi2);
 180
 181         return ((u64)hi << 32) | lo;
 182 }
 183
 184 /**
 185  * exynos4_read_count_32 - Read the lower 32-bits of the global counter
 186  *
 187  * This will read just the lower 32-bits of the global counter.  This is marked
 188  * as notrace so it can be used by the scheduler clock.
 189  *
 190  * Returns the number of cycles in the global counter (lower 32 bits).
 191  */
 192 static u32 notrace exynos4_read_count_32(void)
 193 {
 194         return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
 195 }
 196
 197 static u64 exynos4_frc_read(struct clocksource *cs)
 198 {
 199         return exynos4_read_count_32();
 200 }
 201
 202 static void exynos4_frc_resume(struct clocksource *cs)
 203 {
 204         exynos4_mct_frc_start();
 205 }
 206
 207 static struct clocksource mct_frc = {
 208         .name           = "mct-frc",
 209         .rating         = 450,  /* use value higher than ARM arch timer */
 210         .read           = exynos4_frc_read,
 211         .mask           = CLOCKSOURCE_MASK(32),
 212         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 213         .resume         = exynos4_frc_resume,
 214 };
 215
 216 static u64 notrace exynos4_read_sched_clock(void)
 217 {
 218         return exynos4_read_count_32();
 219 }
 220
 221 #if defined(CONFIG_ARM)
 222 static struct delay_timer exynos4_delay_timer;
 223
 224 static cycles_t exynos4_read_current_timer(void)
 225 {
 226         BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
 227                          "cycles_t needs to move to 32-bit for ARM64 usage");
 228         return exynos4_read_count_32();
 229 }
 230 #endif
 231
 232 static int __init exynos4_clocksource_init(void)
 233 {
 234         exynos4_mct_frc_start();
 235
 236 #if defined(CONFIG_ARM)
 237         exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
 238         exynos4_delay_timer.freq = clk_rate;
 239         register_current_timer_delay(&exynos4_delay_timer);
 240 #endif
 241
 242         if (clocksource_register_hz(&mct_frc, clk_rate))
 243                 panic("%s: can't register clocksource\n", mct_frc.name);
 244
 245         sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
 246
 247         return 0;
 248 }
 249
 250 static void exynos4_mct_comp0_stop(void)
 251 {
 252         unsigned int tcon;
 253
 254         tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 255         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 256
 257         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
 258         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 259 }
 260
 261 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
 262 {
 263         unsigned int tcon;
 264         u64 comp_cycle;
 265
 266         tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 267
 268         if (periodic) {
 269                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
 270                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
 271         }
 272
 273         comp_cycle = exynos4_read_count_64() + cycles;
 274         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
 275         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 276
 277         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
 278
 279         tcon |= MCT_G_TCON_COMP0_ENABLE;
 280         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
 281 }
 282
 283 static int exynos4_comp_set_next_event(unsigned long cycles,
 284                                        struct clock_event_device *evt)
 285 {
 286         exynos4_mct_comp0_start(false, cycles);
 287
 288         return 0;
 289 }
 290
 291 static int mct_set_state_shutdown(struct clock_event_device *evt)
 292 {
 293         exynos4_mct_comp0_stop();
 294         return 0;
 295 }
 296
 297 static int mct_set_state_periodic(struct clock_event_device *evt)
 298 {
 299         unsigned long cycles_per_jiffy;
 300
 301         cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
 302                             >> evt->shift);
 303         exynos4_mct_comp0_stop();
 304         exynos4_mct_comp0_start(true, cycles_per_jiffy);
 305         return 0;
 306 }
 307
 308 static struct clock_event_device mct_comp_device = {
 309         .name                   = "mct-comp",
 310         .features               = CLOCK_EVT_FEAT_PERIODIC |
 311                                   CLOCK_EVT_FEAT_ONESHOT,
 312         .rating                 = 250,
 313         .set_next_event         = exynos4_comp_set_next_event,
 314         .set_state_periodic     = mct_set_state_periodic,
 315         .set_state_shutdown     = mct_set_state_shutdown,
 316         .set_state_oneshot      = mct_set_state_shutdown,
 317         .set_state_oneshot_stopped = mct_set_state_shutdown,
 318         .tick_resume            = mct_set_state_shutdown,
 319 };
 320
 321 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
 322 {
 323         struct clock_event_device *evt = dev_id;
 324
 325         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
 326
 327         evt->event_handler(evt);
 328
 329         return IRQ_HANDLED;
 330 }
 331
 332 static struct irqaction mct_comp_event_irq = {
 333         .name           = "mct_comp_irq",
 334         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 335         .handler        = exynos4_mct_comp_isr,
 336         .dev_id         = &mct_comp_device,
 337 };
 338
 339 static int exynos4_clockevent_init(void)
 340 {
 341         mct_comp_device.cpumask = cpumask_of(0);
 342         clockevents_config_and_register(&mct_comp_device, clk_rate,
 343                                         0xf, 0xffffffff);
 344         setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 345
 346         return 0;
 347 }
 348
 349 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 350
 351 /* Clock event handling */
 352 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 353 {
 354         unsigned long tmp;
 355         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
 356         unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 357
 358         tmp = readl_relaxed(reg_base + offset);
 359         if (tmp & mask) {
 360                 tmp &= ~mask;
 361                 exynos4_mct_write(tmp, offset);
 362         }
 363 }
 364
 365 static void exynos4_mct_tick_start(unsigned long cycles,
 366                                    struct mct_clock_event_device *mevt)
 367 {
 368         unsigned long tmp;
 369
 370         exynos4_mct_tick_stop(mevt);
 371
 372         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
 373
 374         /* update interrupt count buffer */
 375         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 376
 377         /* enable MCT tick interrupt */
 378         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 379
 380         tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
 381         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
 382                MCT_L_TCON_INTERVAL_MODE;
 383         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
 384 }
 385
 386 static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 387 {
 388         /* Clear the MCT tick interrupt */
 389         if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
 390                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 391 }
 392
 393 static int exynos4_tick_set_next_event(unsigned long cycles,
 394                                        struct clock_event_device *evt)
 395 {
 396         struct mct_clock_event_device *mevt;
 397
 398         mevt = container_of(evt, struct mct_clock_event_device, evt);
 399         exynos4_mct_tick_start(cycles, mevt);
 400         return 0;
 401 }
 402
 403 static int set_state_shutdown(struct clock_event_device *evt)
 404 {
 405         struct mct_clock_event_device *mevt;
 406
 407         mevt = container_of(evt, struct mct_clock_event_device, evt);
 408         exynos4_mct_tick_stop(mevt);
 409         exynos4_mct_tick_clear(mevt);
 410         return 0;
 411 }
 412
 413 static int set_state_periodic(struct clock_event_device *evt)
 414 {
 415         struct mct_clock_event_device *mevt;
 416         unsigned long cycles_per_jiffy;
 417
 418         mevt = container_of(evt, struct mct_clock_event_device, evt);
 419         cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
 420                             >> evt->shift);
 421         exynos4_mct_tick_stop(mevt);
 422         exynos4_mct_tick_start(cycles_per_jiffy, mevt);
 423         return 0;
 424 }
 425
 426 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 427 {
 428         struct mct_clock_event_device *mevt = dev_id;
 429         struct clock_event_device *evt = &mevt->evt;
 430
 431         /*
 432          * This is for supporting oneshot mode.
 433          * Mct would generate interrupt periodically
 434          * without explicit stopping.
 435          */
 436         if (!clockevent_state_periodic(&mevt->evt))
 437                 exynos4_mct_tick_stop(mevt);
 438
 439         exynos4_mct_tick_clear(mevt);
 440
 441         evt->event_handler(evt);
 442
 443         return IRQ_HANDLED;
 444 }
 445
 446 static int exynos4_mct_starting_cpu(unsigned int cpu)
 447 {
 448         struct mct_clock_event_device *mevt =
 449                 per_cpu_ptr(&percpu_mct_tick, cpu);
 450         struct clock_event_device *evt = &mevt->evt;
 451
 452         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 453         snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
 454
 455         evt->name = mevt->name;
 456         evt->cpumask = cpumask_of(cpu);
 457         evt->set_next_event = exynos4_tick_set_next_event;
 458         evt->set_state_periodic = set_state_periodic;
 459         evt->set_state_shutdown = set_state_shutdown;
 460         evt->set_state_oneshot = set_state_shutdown;
 461         evt->set_state_oneshot_stopped = set_state_shutdown;
 462         evt->tick_resume = set_state_shutdown;
 463         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 464         evt->rating = 500;      /* use value higher than ARM arch timer */
 465
 466         exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 467
 468         if (mct_int_type == MCT_INT_SPI) {
 469
 470                 if (evt->irq == -1)
 471                         return -EIO;
 472
 473                 irq_force_affinity(evt->irq, cpumask_of(cpu));
 474                 enable_irq(evt->irq);
 475         } else {
 476                 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
 477         }
 478         clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
 479                                         0xf, 0x7fffffff);
 480
 481         return 0;
 482 }
 483
 484 static int exynos4_mct_dying_cpu(unsigned int cpu)
 485 {
 486         struct mct_clock_event_device *mevt =
 487                 per_cpu_ptr(&percpu_mct_tick, cpu);
 488         struct clock_event_device *evt = &mevt->evt;
 489
 490         evt->set_state_shutdown(evt);
 491         if (mct_int_type == MCT_INT_SPI) {
 492                 if (evt->irq != -1)
 493                         disable_irq_nosync(evt->irq);
 494                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 495         } else {
 496                 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 497         }
 498         return 0;
 499 }
 500
 501 static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
 502 {
 503         int err, cpu;
 504         struct clk *mct_clk, *tick_clk;
 505
 506         tick_clk = of_clk_get_by_name(np, "fin_pll");
 507         if (IS_ERR(tick_clk))
 508                 panic("%s: unable to determine tick clock rate\n", __func__);
 509         clk_rate = clk_get_rate(tick_clk);
 510
 511         mct_clk = of_clk_get_by_name(np, "mct");
 512         if (IS_ERR(mct_clk))
 513                 panic("%s: unable to retrieve mct clock instance\n", __func__);
 514         clk_prepare_enable(mct_clk);
 515
 516         reg_base = base;
 517         if (!reg_base)
 518                 panic("%s: unable to ioremap mct address space\n", __func__);
 519
 520         if (mct_int_type == MCT_INT_PPI) {
 521
 522                 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
 523                                          exynos4_mct_tick_isr, "MCT",
 524                                          &percpu_mct_tick);
 525                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
 526                      mct_irqs[MCT_L0_IRQ], err);
 527         } else {
 528                 for_each_possible_cpu(cpu) {
 529                         int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
 530                         struct mct_clock_event_device *pcpu_mevt =
 531                                 per_cpu_ptr(&percpu_mct_tick, cpu);
 532
 533                         pcpu_mevt->evt.irq = -1;
 534
 535                         irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
 536                         if (request_irq(mct_irq,
 537                                         exynos4_mct_tick_isr,
 538                                         IRQF_TIMER | IRQF_NOBALANCING,
 539                                         pcpu_mevt->name, pcpu_mevt)) {
 540                                 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",
 541                                                                         cpu);
 542
 543                                 continue;
 544                         }
 545                         pcpu_mevt->evt.irq = mct_irq;
 546                 }
 547         }
 548
 549         /* Install hotplug callbacks which configure the timer on this CPU */
 550         err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
 551                                 "clockevents/exynos4/mct_timer:starting",
 552                                 exynos4_mct_starting_cpu,
 553                                 exynos4_mct_dying_cpu);
 554         if (err)
 555                 goto out_irq;
 556
 557         return 0;
 558
 559 out_irq:
 560         if (mct_int_type == MCT_INT_PPI) {
 561                 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
 562         } else {
 563                 for_each_possible_cpu(cpu) {
 564                         struct mct_clock_event_device *pcpu_mevt =
 565                                 per_cpu_ptr(&percpu_mct_tick, cpu);
 566
 567                         if (pcpu_mevt->evt.irq != -1) {
 568                                 free_irq(pcpu_mevt->evt.irq, pcpu_mevt);
 569                                 pcpu_mevt->evt.irq = -1;
 570                         }
 571                 }
 572         }
 573         return err;
 574 }
 575
 576 static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
 577 {
 578         u32 nr_irqs, i;
 579         int ret;
 580
 581         mct_int_type = int_type;
 582
 583         /* This driver uses only one global timer interrupt */
 584         mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
 585
 586         /*
 587          * Find out the number of local irqs specified. The local
 588          * timer irqs are specified after the four global timer
 589          * irqs are specified.
 590          */
 591         nr_irqs = of_irq_count(np);
 592         for (i = MCT_L0_IRQ; i < nr_irqs; i++)
 593                 mct_irqs[i] = irq_of_parse_and_map(np, i);
 594
 595         ret = exynos4_timer_resources(np, of_iomap(np, 0));
 596         if (ret)
 597                 return ret;
 598
 599         ret = exynos4_clocksource_init();
 600         if (ret)
 601                 return ret;
 602
 603         return exynos4_clockevent_init();
 604 }
 605
 606
 607 static int __init mct_init_spi(struct device_node *np)
 608 {
 609         return mct_init_dt(np, MCT_INT_SPI);
 610 }
 611
 612 static int __init mct_init_ppi(struct device_node *np)
 613 {
 614         return mct_init_dt(np, MCT_INT_PPI);
 615 }
 616 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
 617 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);