drivers/clocksource/timer-stm32.c

   1 /*
   2  * Copyright (C) Maxime Coquelin 2015
   3  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  * License terms:  GNU General Public License (GPL), version 2
   5  *
   6  * Inspired by time-efm32.c from Uwe Kleine-Koenig
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/irq.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/clk.h>
  18 #include <linux/reset.h>
  19 #include <linux/slab.h>
  20
  21 #include "timer-of.h"
  22
  23 #define TIM_CR1         0x00
  24 #define TIM_DIER        0x0c
  25 #define TIM_SR          0x10
  26 #define TIM_EGR         0x14
  27 #define TIM_PSC         0x28
  28 #define TIM_ARR         0x2c
  29
  30 #define TIM_CR1_CEN     BIT(0)
  31 #define TIM_CR1_OPM     BIT(3)
  32 #define TIM_CR1_ARPE    BIT(7)
  33
  34 #define TIM_DIER_UIE    BIT(0)
  35
  36 #define TIM_SR_UIF      BIT(0)
  37
  38 #define TIM_EGR_UG      BIT(0)
  39
  40 static int stm32_clock_event_shutdown(struct clock_event_device *clkevt)
  41 {
  42         struct timer_of *to = to_timer_of(clkevt);
  43
  44         writel_relaxed(0, timer_of_base(to) + TIM_CR1);
  45
  46         return 0;
  47 }
  48
  49 static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt)
  50 {
  51         struct timer_of *to = to_timer_of(clkevt);
  52
  53         writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR);
  54         writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
  55
  56         return 0;
  57 }
  58
  59 static int stm32_clock_event_set_next_event(unsigned long evt,
  60                                             struct clock_event_device *clkevt)
  61 {
  62         struct timer_of *to = to_timer_of(clkevt);
  63
  64         writel_relaxed(evt, timer_of_base(to) + TIM_ARR);
  65         writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,
  66                        timer_of_base(to) + TIM_CR1);
  67
  68         return 0;
  69 }
  70
  71 static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
  72 {
  73         struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
  74         struct timer_of *to = to_timer_of(clkevt);
  75
  76         writel_relaxed(0, timer_of_base(to) + TIM_SR);
  77
  78         clkevt->event_handler(clkevt);
  79
  80         return IRQ_HANDLED;
  81 }
  82
  83 static void __init stm32_clockevent_init(struct timer_of *to)
  84 {
  85         unsigned long max_delta;
  86         int prescaler;
  87
  88         to->clkevt.name = "stm32_clockevent";
  89         to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
  90         to->clkevt.set_state_shutdown = stm32_clock_event_shutdown;
  91         to->clkevt.set_state_periodic = stm32_clock_event_set_periodic;
  92         to->clkevt.set_state_oneshot = stm32_clock_event_shutdown;
  93         to->clkevt.tick_resume = stm32_clock_event_shutdown;
  94         to->clkevt.set_next_event = stm32_clock_event_set_next_event;
  95
  96         /* Detect whether the timer is 16 or 32 bits */
  97         writel_relaxed(~0U, timer_of_base(to) + TIM_ARR);
  98         max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR);
  99         if (max_delta == ~0U) {
 100                 prescaler = 1;
 101                 to->clkevt.rating = 250;
 102         } else {
 103                 prescaler = 1024;
 104                 to->clkevt.rating = 100;
 105         }
 106         writel_relaxed(0, timer_of_base(to) + TIM_ARR);
 107
 108         writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
 109         writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
 110         writel_relaxed(0, timer_of_base(to) + TIM_SR);
 111         writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER);
 112
 113         /* Adjust rate and period given the prescaler value */
 114         to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler);
 115         to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
 116
 117         clockevents_config_and_register(&to->clkevt,
 118                                         timer_of_rate(to), 0x1, max_delta);
 119
 120         pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
 121                 to->np, max_delta == UINT_MAX ? 32 : 16);
 122 }
 123
 124 static int __init stm32_timer_init(struct device_node *node)
 125 {
 126         struct reset_control *rstc;
 127         struct timer_of *to;
 128         int ret;
 129
 130         to = kzalloc(sizeof(*to), GFP_KERNEL);
 131         if (!to)
 132                 return -ENOMEM;
 133
 134         to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
 135         to->of_irq.handler = stm32_clock_event_handler;
 136
 137         ret = timer_of_init(node, to);
 138         if (ret)
 139                 goto err;
 140
 141         rstc = of_reset_control_get(node, NULL);
 142         if (!IS_ERR(rstc)) {
 143                 reset_control_assert(rstc);
 144                 reset_control_deassert(rstc);
 145         }
 146
 147         stm32_clockevent_init(to);
 148         return 0;
 149 err:
 150         kfree(to);
 151         return ret;
 152 }
 153
 154 TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);