2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
39 #define ATOM_RATIOS 0x66a
40 #define ATOM_VIDS 0x66b
41 #define ATOM_TURBO_RATIOS 0x66c
42 #define ATOM_TURBO_VIDS 0x66d
45 #include <acpi/processor.h>
49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
50 #define fp_toint(X) ((X) >> FRAC_BITS)
53 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 static inline int32_t mul_fp(int32_t x, int32_t y)
57 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
60 static inline int32_t div_fp(s64 x, s64 y)
62 return div64_s64((int64_t)x << FRAC_BITS, y);
65 static inline int ceiling_fp(int32_t x)
70 mask = (1 << FRAC_BITS) - 1;
76 static inline u64 mul_ext_fp(u64 x, u64 y)
78 return (x * y) >> EXT_FRAC_BITS;
81 static inline u64 div_ext_fp(u64 x, u64 y)
83 return div64_u64(x << EXT_FRAC_BITS, y);
87 * struct sample - Store performance sample
88 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
89 * performance during last sample period
90 * @busy_scaled: Scaled busy value which is used to calculate next
91 * P state. This can be different than core_avg_perf
92 * to account for cpu idle period
93 * @aperf: Difference of actual performance frequency clock count
94 * read from APERF MSR between last and current sample
95 * @mperf: Difference of maximum performance frequency clock count
96 * read from MPERF MSR between last and current sample
97 * @tsc: Difference of time stamp counter between last and
99 * @freq: Effective frequency calculated from APERF/MPERF
100 * @time: Current time from scheduler
102 * This structure is used in the cpudata structure to store performance sample
103 * data for choosing next P State.
106 int32_t core_avg_perf;
116 * struct pstate_data - Store P state data
117 * @current_pstate: Current requested P state
118 * @min_pstate: Min P state possible for this platform
119 * @max_pstate: Max P state possible for this platform
120 * @max_pstate_physical:This is physical Max P state for a processor
121 * This can be higher than the max_pstate which can
122 * be limited by platform thermal design power limits
123 * @scaling: Scaling factor to convert frequency to cpufreq
125 * @turbo_pstate: Max Turbo P state possible for this platform
127 * Stores the per cpu model P state limits and current P state.
133 int max_pstate_physical;
139 * struct vid_data - Stores voltage information data
140 * @min: VID data for this platform corresponding to
142 * @max: VID data corresponding to the highest P State.
143 * @turbo: VID data for turbo P state
144 * @ratio: Ratio of (vid max - vid min) /
145 * (max P state - Min P State)
147 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
148 * This data is used in Atom platforms, where in addition to target P state,
149 * the voltage data needs to be specified to select next P State.
159 * struct _pid - Stores PID data
160 * @setpoint: Target set point for busyness or performance
161 * @integral: Storage for accumulated error values
162 * @p_gain: PID proportional gain
163 * @i_gain: PID integral gain
164 * @d_gain: PID derivative gain
165 * @deadband: PID deadband
166 * @last_err: Last error storage for integral part of PID calculation
168 * Stores PID coefficients and last error for PID controller.
181 * struct cpudata - Per CPU instance data storage
182 * @cpu: CPU number for this instance data
183 * @update_util: CPUFreq utility callback information
184 * @update_util_set: CPUFreq utility callback is set
185 * @pstate: Stores P state limits for this CPU
186 * @vid: Stores VID limits for this CPU
187 * @pid: Stores PID parameters for this CPU
188 * @last_sample_time: Last Sample time
189 * @prev_aperf: Last APERF value read from APERF MSR
190 * @prev_mperf: Last MPERF value read from MPERF MSR
191 * @prev_tsc: Last timestamp counter (TSC) value
192 * @prev_cummulative_iowait: IO Wait time difference from last and
194 * @sample: Storage for storing last Sample data
195 * @acpi_perf_data: Stores ACPI perf information read from _PSS
196 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
198 * This structure stores per CPU instance data for all CPUs.
203 struct update_util_data update_util;
204 bool update_util_set;
206 struct pstate_data pstate;
210 u64 last_sample_time;
214 u64 prev_cummulative_iowait;
215 struct sample sample;
217 struct acpi_processor_performance acpi_perf_data;
218 bool valid_pss_table;
222 static struct cpudata **all_cpu_data;
225 * struct pid_adjust_policy - Stores static PID configuration data
226 * @sample_rate_ms: PID calculation sample rate in ms
227 * @sample_rate_ns: Sample rate calculation in ns
228 * @deadband: PID deadband
229 * @setpoint: PID Setpoint
230 * @p_gain_pct: PID proportional gain
231 * @i_gain_pct: PID integral gain
232 * @d_gain_pct: PID derivative gain
234 * Stores per CPU model static PID configuration data.
236 struct pstate_adjust_policy {
247 * struct pstate_funcs - Per CPU model specific callbacks
248 * @get_max: Callback to get maximum non turbo effective P state
249 * @get_max_physical: Callback to get maximum non turbo physical P state
250 * @get_min: Callback to get minimum P state
251 * @get_turbo: Callback to get turbo P state
252 * @get_scaling: Callback to get frequency scaling factor
253 * @get_val: Callback to convert P state to actual MSR write value
254 * @get_vid: Callback to get VID data for Atom platforms
255 * @get_target_pstate: Callback to a function to calculate next P state to use
257 * Core and Atom CPU models have different way to get P State limits. This
258 * structure is used to store those callbacks.
260 struct pstate_funcs {
261 int (*get_max)(void);
262 int (*get_max_physical)(void);
263 int (*get_min)(void);
264 int (*get_turbo)(void);
265 int (*get_scaling)(void);
266 u64 (*get_val)(struct cpudata*, int pstate);
267 void (*get_vid)(struct cpudata *);
268 int32_t (*get_target_pstate)(struct cpudata *);
272 * struct cpu_defaults- Per CPU model default config data
273 * @pid_policy: PID config data
274 * @funcs: Callback function data
276 struct cpu_defaults {
277 struct pstate_adjust_policy pid_policy;
278 struct pstate_funcs funcs;
281 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
282 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
284 static struct pstate_adjust_policy pid_params;
285 static struct pstate_funcs pstate_funcs;
286 static int hwp_active;
289 static bool acpi_ppc;
293 * struct perf_limits - Store user and policy limits
294 * @no_turbo: User requested turbo state from intel_pstate sysfs
295 * @turbo_disabled: Platform turbo status either from msr
296 * MSR_IA32_MISC_ENABLE or when maximum available pstate
297 * matches the maximum turbo pstate
298 * @max_perf_pct: Effective maximum performance limit in percentage, this
299 * is minimum of either limits enforced by cpufreq policy
300 * or limits from user set limits via intel_pstate sysfs
301 * @min_perf_pct: Effective minimum performance limit in percentage, this
302 * is maximum of either limits enforced by cpufreq policy
303 * or limits from user set limits via intel_pstate sysfs
304 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
305 * This value is used to limit max pstate
306 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
307 * This value is used to limit min pstate
308 * @max_policy_pct: The maximum performance in percentage enforced by
309 * cpufreq setpolicy interface
310 * @max_sysfs_pct: The maximum performance in percentage enforced by
311 * intel pstate sysfs interface
312 * @min_policy_pct: The minimum performance in percentage enforced by
313 * cpufreq setpolicy interface
314 * @min_sysfs_pct: The minimum performance in percentage enforced by
315 * intel pstate sysfs interface
317 * Storage for user and policy defined limits.
332 static struct perf_limits performance_limits = {
336 .max_perf = int_tofp(1),
338 .min_perf = int_tofp(1),
339 .max_policy_pct = 100,
340 .max_sysfs_pct = 100,
345 static struct perf_limits powersave_limits = {
349 .max_perf = int_tofp(1),
352 .max_policy_pct = 100,
353 .max_sysfs_pct = 100,
358 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
359 static struct perf_limits *limits = &performance_limits;
361 static struct perf_limits *limits = &powersave_limits;
366 static bool intel_pstate_get_ppc_enable_status(void)
368 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
369 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
375 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
384 if (!intel_pstate_get_ppc_enable_status())
387 cpu = all_cpu_data[policy->cpu];
389 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
395 * Check if the control value in _PSS is for PERF_CTL MSR, which should
396 * guarantee that the states returned by it map to the states in our
399 if (cpu->acpi_perf_data.control_register.space_id !=
400 ACPI_ADR_SPACE_FIXED_HARDWARE)
404 * If there is only one entry _PSS, simply ignore _PSS and continue as
405 * usual without taking _PSS into account
407 if (cpu->acpi_perf_data.state_count < 2)
410 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
411 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
412 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
413 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
414 (u32) cpu->acpi_perf_data.states[i].core_frequency,
415 (u32) cpu->acpi_perf_data.states[i].power,
416 (u32) cpu->acpi_perf_data.states[i].control);
420 * The _PSS table doesn't contain whole turbo frequency range.
421 * This just contains +1 MHZ above the max non turbo frequency,
422 * with control value corresponding to max turbo ratio. But
423 * when cpufreq set policy is called, it will call with this
424 * max frequency, which will cause a reduced performance as
425 * this driver uses real max turbo frequency as the max
426 * frequency. So correct this frequency in _PSS table to
427 * correct max turbo frequency based on the turbo state.
428 * Also need to convert to MHz as _PSS freq is in MHz.
430 if (!limits->turbo_disabled)
431 cpu->acpi_perf_data.states[0].core_frequency =
432 policy->cpuinfo.max_freq / 1000;
433 cpu->valid_pss_table = true;
434 pr_debug("_PPC limits will be enforced\n");
439 cpu->valid_pss_table = false;
440 acpi_processor_unregister_performance(policy->cpu);
443 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
447 cpu = all_cpu_data[policy->cpu];
448 if (!cpu->valid_pss_table)
451 acpi_processor_unregister_performance(policy->cpu);
455 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
459 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
464 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
465 int deadband, int integral) {
466 pid->setpoint = int_tofp(setpoint);
467 pid->deadband = int_tofp(deadband);
468 pid->integral = int_tofp(integral);
469 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
472 static inline void pid_p_gain_set(struct _pid *pid, int percent)
474 pid->p_gain = div_fp(percent, 100);
477 static inline void pid_i_gain_set(struct _pid *pid, int percent)
479 pid->i_gain = div_fp(percent, 100);
482 static inline void pid_d_gain_set(struct _pid *pid, int percent)
484 pid->d_gain = div_fp(percent, 100);
487 static signed int pid_calc(struct _pid *pid, int32_t busy)
490 int32_t pterm, dterm, fp_error;
491 int32_t integral_limit;
493 fp_error = pid->setpoint - busy;
495 if (abs(fp_error) <= pid->deadband)
498 pterm = mul_fp(pid->p_gain, fp_error);
500 pid->integral += fp_error;
503 * We limit the integral here so that it will never
504 * get higher than 30. This prevents it from becoming
505 * too large an input over long periods of time and allows
506 * it to get factored out sooner.
508 * The value of 30 was chosen through experimentation.
510 integral_limit = int_tofp(30);
511 if (pid->integral > integral_limit)
512 pid->integral = integral_limit;
513 if (pid->integral < -integral_limit)
514 pid->integral = -integral_limit;
516 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
517 pid->last_err = fp_error;
519 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
520 result = result + (1 << (FRAC_BITS-1));
521 return (signed int)fp_toint(result);
524 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
526 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
527 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
528 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
530 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
533 static inline void intel_pstate_reset_all_pid(void)
537 for_each_online_cpu(cpu) {
538 if (all_cpu_data[cpu])
539 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
543 static inline void update_turbo_state(void)
548 cpu = all_cpu_data[0];
549 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
550 limits->turbo_disabled =
551 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
552 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
555 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
557 int min, hw_min, max, hw_max, cpu, range, adj_range;
560 rdmsrl(MSR_HWP_CAPABILITIES, cap);
561 hw_min = HWP_LOWEST_PERF(cap);
562 hw_max = HWP_HIGHEST_PERF(cap);
563 range = hw_max - hw_min;
565 for_each_cpu(cpu, cpumask) {
566 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
567 adj_range = limits->min_perf_pct * range / 100;
568 min = hw_min + adj_range;
569 value &= ~HWP_MIN_PERF(~0L);
570 value |= HWP_MIN_PERF(min);
572 adj_range = limits->max_perf_pct * range / 100;
573 max = hw_min + adj_range;
574 if (limits->no_turbo) {
575 hw_max = HWP_GUARANTEED_PERF(cap);
580 value &= ~HWP_MAX_PERF(~0L);
581 value |= HWP_MAX_PERF(max);
582 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
586 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
589 intel_pstate_hwp_set(policy->cpus);
594 static void intel_pstate_hwp_set_online_cpus(void)
597 intel_pstate_hwp_set(cpu_online_mask);
601 /************************** debugfs begin ************************/
602 static int pid_param_set(void *data, u64 val)
605 intel_pstate_reset_all_pid();
609 static int pid_param_get(void *data, u64 *val)
614 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
621 static struct pid_param pid_files[] = {
622 {"sample_rate_ms", &pid_params.sample_rate_ms},
623 {"d_gain_pct", &pid_params.d_gain_pct},
624 {"i_gain_pct", &pid_params.i_gain_pct},
625 {"deadband", &pid_params.deadband},
626 {"setpoint", &pid_params.setpoint},
627 {"p_gain_pct", &pid_params.p_gain_pct},
631 static void __init intel_pstate_debug_expose_params(void)
633 struct dentry *debugfs_parent;
638 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
639 if (IS_ERR_OR_NULL(debugfs_parent))
641 while (pid_files[i].name) {
642 debugfs_create_file(pid_files[i].name, 0660,
643 debugfs_parent, pid_files[i].value,
649 /************************** debugfs end ************************/
651 /************************** sysfs begin ************************/
652 #define show_one(file_name, object) \
653 static ssize_t show_##file_name \
654 (struct kobject *kobj, struct attribute *attr, char *buf) \
656 return sprintf(buf, "%u\n", limits->object); \
659 static ssize_t show_turbo_pct(struct kobject *kobj,
660 struct attribute *attr, char *buf)
663 int total, no_turbo, turbo_pct;
666 cpu = all_cpu_data[0];
668 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
669 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
670 turbo_fp = div_fp(no_turbo, total);
671 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
672 return sprintf(buf, "%u\n", turbo_pct);
675 static ssize_t show_num_pstates(struct kobject *kobj,
676 struct attribute *attr, char *buf)
681 cpu = all_cpu_data[0];
682 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
683 return sprintf(buf, "%u\n", total);
686 static ssize_t show_no_turbo(struct kobject *kobj,
687 struct attribute *attr, char *buf)
691 update_turbo_state();
692 if (limits->turbo_disabled)
693 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
695 ret = sprintf(buf, "%u\n", limits->no_turbo);
700 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
701 const char *buf, size_t count)
706 ret = sscanf(buf, "%u", &input);
710 update_turbo_state();
711 if (limits->turbo_disabled) {
712 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
716 limits->no_turbo = clamp_t(int, input, 0, 1);
719 intel_pstate_hwp_set_online_cpus();
724 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
725 const char *buf, size_t count)
730 ret = sscanf(buf, "%u", &input);
734 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
735 limits->max_perf_pct = min(limits->max_policy_pct,
736 limits->max_sysfs_pct);
737 limits->max_perf_pct = max(limits->min_policy_pct,
738 limits->max_perf_pct);
739 limits->max_perf_pct = max(limits->min_perf_pct,
740 limits->max_perf_pct);
741 limits->max_perf = div_fp(limits->max_perf_pct, 100);
744 intel_pstate_hwp_set_online_cpus();
748 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
749 const char *buf, size_t count)
754 ret = sscanf(buf, "%u", &input);
758 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
759 limits->min_perf_pct = max(limits->min_policy_pct,
760 limits->min_sysfs_pct);
761 limits->min_perf_pct = min(limits->max_policy_pct,
762 limits->min_perf_pct);
763 limits->min_perf_pct = min(limits->max_perf_pct,
764 limits->min_perf_pct);
765 limits->min_perf = div_fp(limits->min_perf_pct, 100);
768 intel_pstate_hwp_set_online_cpus();
772 show_one(max_perf_pct, max_perf_pct);
773 show_one(min_perf_pct, min_perf_pct);
775 define_one_global_rw(no_turbo);
776 define_one_global_rw(max_perf_pct);
777 define_one_global_rw(min_perf_pct);
778 define_one_global_ro(turbo_pct);
779 define_one_global_ro(num_pstates);
781 static struct attribute *intel_pstate_attributes[] = {
790 static struct attribute_group intel_pstate_attr_group = {
791 .attrs = intel_pstate_attributes,
794 static void __init intel_pstate_sysfs_expose_params(void)
796 struct kobject *intel_pstate_kobject;
799 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
800 &cpu_subsys.dev_root->kobj);
801 BUG_ON(!intel_pstate_kobject);
802 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
805 /************************** sysfs end ************************/
807 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
809 /* First disable HWP notification interrupt as we don't process them */
810 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
812 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
815 static int atom_get_min_pstate(void)
819 rdmsrl(ATOM_RATIOS, value);
820 return (value >> 8) & 0x7F;
823 static int atom_get_max_pstate(void)
827 rdmsrl(ATOM_RATIOS, value);
828 return (value >> 16) & 0x7F;
831 static int atom_get_turbo_pstate(void)
835 rdmsrl(ATOM_TURBO_RATIOS, value);
839 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
845 val = (u64)pstate << 8;
846 if (limits->no_turbo && !limits->turbo_disabled)
849 vid_fp = cpudata->vid.min + mul_fp(
850 int_tofp(pstate - cpudata->pstate.min_pstate),
853 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
854 vid = ceiling_fp(vid_fp);
856 if (pstate > cpudata->pstate.max_pstate)
857 vid = cpudata->vid.turbo;
862 static int silvermont_get_scaling(void)
866 /* Defined in Table 35-6 from SDM (Sept 2015) */
867 static int silvermont_freq_table[] = {
868 83300, 100000, 133300, 116700, 80000};
870 rdmsrl(MSR_FSB_FREQ, value);
874 return silvermont_freq_table[i];
877 static int airmont_get_scaling(void)
881 /* Defined in Table 35-10 from SDM (Sept 2015) */
882 static int airmont_freq_table[] = {
883 83300, 100000, 133300, 116700, 80000,
884 93300, 90000, 88900, 87500};
886 rdmsrl(MSR_FSB_FREQ, value);
890 return airmont_freq_table[i];
893 static void atom_get_vid(struct cpudata *cpudata)
897 rdmsrl(ATOM_VIDS, value);
898 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
899 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
900 cpudata->vid.ratio = div_fp(
901 cpudata->vid.max - cpudata->vid.min,
902 int_tofp(cpudata->pstate.max_pstate -
903 cpudata->pstate.min_pstate));
905 rdmsrl(ATOM_TURBO_VIDS, value);
906 cpudata->vid.turbo = value & 0x7f;
909 static int core_get_min_pstate(void)
913 rdmsrl(MSR_PLATFORM_INFO, value);
914 return (value >> 40) & 0xFF;
917 static int core_get_max_pstate_physical(void)
921 rdmsrl(MSR_PLATFORM_INFO, value);
922 return (value >> 8) & 0xFF;
925 static int core_get_max_pstate(void)
932 rdmsrl(MSR_PLATFORM_INFO, plat_info);
933 max_pstate = (plat_info >> 8) & 0xFF;
935 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
937 /* Do some sanity checking for safety */
938 if (plat_info & 0x600000000) {
943 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
947 tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl;
948 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
952 /* For level 1 and 2, bits[23:16] contain the ratio */
956 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
957 if (tdp_ratio - 1 == tar) {
959 pr_debug("max_pstate=TAC %x\n", max_pstate);
970 static int core_get_turbo_pstate(void)
975 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
976 nont = core_get_max_pstate();
983 static inline int core_get_scaling(void)
988 static u64 core_get_val(struct cpudata *cpudata, int pstate)
992 val = (u64)pstate << 8;
993 if (limits->no_turbo && !limits->turbo_disabled)
999 static int knl_get_turbo_pstate(void)
1004 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
1005 nont = core_get_max_pstate();
1006 ret = (((value) >> 8) & 0xFF);
1012 static struct cpu_defaults core_params = {
1014 .sample_rate_ms = 10,
1022 .get_max = core_get_max_pstate,
1023 .get_max_physical = core_get_max_pstate_physical,
1024 .get_min = core_get_min_pstate,
1025 .get_turbo = core_get_turbo_pstate,
1026 .get_scaling = core_get_scaling,
1027 .get_val = core_get_val,
1028 .get_target_pstate = get_target_pstate_use_performance,
1032 static struct cpu_defaults silvermont_params = {
1034 .sample_rate_ms = 10,
1042 .get_max = atom_get_max_pstate,
1043 .get_max_physical = atom_get_max_pstate,
1044 .get_min = atom_get_min_pstate,
1045 .get_turbo = atom_get_turbo_pstate,
1046 .get_val = atom_get_val,
1047 .get_scaling = silvermont_get_scaling,
1048 .get_vid = atom_get_vid,
1049 .get_target_pstate = get_target_pstate_use_cpu_load,
1053 static struct cpu_defaults airmont_params = {
1055 .sample_rate_ms = 10,
1063 .get_max = atom_get_max_pstate,
1064 .get_max_physical = atom_get_max_pstate,
1065 .get_min = atom_get_min_pstate,
1066 .get_turbo = atom_get_turbo_pstate,
1067 .get_val = atom_get_val,
1068 .get_scaling = airmont_get_scaling,
1069 .get_vid = atom_get_vid,
1070 .get_target_pstate = get_target_pstate_use_cpu_load,
1074 static struct cpu_defaults knl_params = {
1076 .sample_rate_ms = 10,
1084 .get_max = core_get_max_pstate,
1085 .get_max_physical = core_get_max_pstate_physical,
1086 .get_min = core_get_min_pstate,
1087 .get_turbo = knl_get_turbo_pstate,
1088 .get_scaling = core_get_scaling,
1089 .get_val = core_get_val,
1090 .get_target_pstate = get_target_pstate_use_performance,
1094 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1096 int max_perf = cpu->pstate.turbo_pstate;
1100 if (limits->no_turbo || limits->turbo_disabled)
1101 max_perf = cpu->pstate.max_pstate;
1104 * performance can be limited by user through sysfs, by cpufreq
1105 * policy, or by cpu specific default values determined through
1108 max_perf_adj = fp_toint(max_perf * limits->max_perf);
1109 *max = clamp_t(int, max_perf_adj,
1110 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1112 min_perf = fp_toint(max_perf * limits->min_perf);
1113 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1116 static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate)
1118 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1119 cpu->pstate.current_pstate = pstate;
1122 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1124 int pstate = cpu->pstate.min_pstate;
1126 intel_pstate_record_pstate(cpu, pstate);
1128 * Generally, there is no guarantee that this code will always run on
1129 * the CPU being updated, so force the register update to run on the
1132 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1133 pstate_funcs.get_val(cpu, pstate));
1136 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1138 cpu->pstate.min_pstate = pstate_funcs.get_min();
1139 cpu->pstate.max_pstate = pstate_funcs.get_max();
1140 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1141 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1142 cpu->pstate.scaling = pstate_funcs.get_scaling();
1144 if (pstate_funcs.get_vid)
1145 pstate_funcs.get_vid(cpu);
1147 intel_pstate_set_min_pstate(cpu);
1150 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1152 struct sample *sample = &cpu->sample;
1154 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1157 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1160 unsigned long flags;
1163 local_irq_save(flags);
1164 rdmsrl(MSR_IA32_APERF, aperf);
1165 rdmsrl(MSR_IA32_MPERF, mperf);
1167 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1168 local_irq_restore(flags);
1171 local_irq_restore(flags);
1173 cpu->last_sample_time = cpu->sample.time;
1174 cpu->sample.time = time;
1175 cpu->sample.aperf = aperf;
1176 cpu->sample.mperf = mperf;
1177 cpu->sample.tsc = tsc;
1178 cpu->sample.aperf -= cpu->prev_aperf;
1179 cpu->sample.mperf -= cpu->prev_mperf;
1180 cpu->sample.tsc -= cpu->prev_tsc;
1182 cpu->prev_aperf = aperf;
1183 cpu->prev_mperf = mperf;
1184 cpu->prev_tsc = tsc;
1186 * First time this function is invoked in a given cycle, all of the
1187 * previous sample data fields are equal to zero or stale and they must
1188 * be populated with meaningful numbers for things to work, so assume
1189 * that sample.time will always be reset before setting the utilization
1190 * update hook and make the caller skip the sample then.
1192 return !!cpu->last_sample_time;
1195 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1197 return mul_ext_fp(cpu->sample.core_avg_perf,
1198 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1201 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1203 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1204 cpu->sample.core_avg_perf);
1207 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1209 struct sample *sample = &cpu->sample;
1210 u64 cummulative_iowait, delta_iowait_us;
1211 u64 delta_iowait_mperf;
1215 cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now);
1218 * Convert iowait time into number of IO cycles spent at max_freq.
1219 * IO is considered as busy only for the cpu_load algorithm. For
1220 * performance this is not needed since we always try to reach the
1221 * maximum P-State, so we are already boosting the IOs.
1223 delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait;
1224 delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling *
1225 cpu->pstate.max_pstate, MSEC_PER_SEC);
1227 mperf = cpu->sample.mperf + delta_iowait_mperf;
1228 cpu->prev_cummulative_iowait = cummulative_iowait;
1231 * The load can be estimated as the ratio of the mperf counter
1232 * running at a constant frequency during active periods
1233 * (C0) and the time stamp counter running at the same frequency
1234 * also during C-states.
1236 cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc);
1237 cpu->sample.busy_scaled = cpu_load;
1239 return get_avg_pstate(cpu) - pid_calc(&cpu->pid, cpu_load);
1242 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1244 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1248 * perf_scaled is the average performance during the last sampling
1249 * period scaled by the ratio of the maximum P-state to the P-state
1250 * requested last time (in percent). That measures the system's
1251 * response to the previous P-state selection.
1253 max_pstate = cpu->pstate.max_pstate_physical;
1254 current_pstate = cpu->pstate.current_pstate;
1255 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1256 div_fp(100 * max_pstate, current_pstate));
1259 * Since our utilization update callback will not run unless we are
1260 * in C0, check if the actual elapsed time is significantly greater (3x)
1261 * than our sample interval. If it is, then we were idle for a long
1262 * enough period of time to adjust our performance metric.
1264 duration_ns = cpu->sample.time - cpu->last_sample_time;
1265 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1266 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1267 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1269 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1270 if (sample_ratio < int_tofp(1))
1274 cpu->sample.busy_scaled = perf_scaled;
1275 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1278 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1280 int max_perf, min_perf;
1282 update_turbo_state();
1284 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1285 pstate = clamp_t(int, pstate, min_perf, max_perf);
1286 if (pstate == cpu->pstate.current_pstate)
1289 intel_pstate_record_pstate(cpu, pstate);
1290 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1293 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1295 int from, target_pstate;
1296 struct sample *sample;
1298 from = cpu->pstate.current_pstate;
1300 target_pstate = pstate_funcs.get_target_pstate(cpu);
1302 intel_pstate_update_pstate(cpu, target_pstate);
1304 sample = &cpu->sample;
1305 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1306 fp_toint(sample->busy_scaled),
1308 cpu->pstate.current_pstate,
1312 get_avg_frequency(cpu));
1315 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1316 unsigned long util, unsigned long max)
1318 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1319 u64 delta_ns = time - cpu->sample.time;
1321 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1322 bool sample_taken = intel_pstate_sample(cpu, time);
1325 intel_pstate_calc_avg_perf(cpu);
1327 intel_pstate_adjust_busy_pstate(cpu);
1332 #define ICPU(model, policy) \
1333 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1334 (unsigned long)&policy }
1336 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1337 ICPU(0x2a, core_params),
1338 ICPU(0x2d, core_params),
1339 ICPU(0x37, silvermont_params),
1340 ICPU(0x3a, core_params),
1341 ICPU(0x3c, core_params),
1342 ICPU(0x3d, core_params),
1343 ICPU(0x3e, core_params),
1344 ICPU(0x3f, core_params),
1345 ICPU(0x45, core_params),
1346 ICPU(0x46, core_params),
1347 ICPU(0x47, core_params),
1348 ICPU(0x4c, airmont_params),
1349 ICPU(0x4e, core_params),
1350 ICPU(0x4f, core_params),
1351 ICPU(0x5e, core_params),
1352 ICPU(0x56, core_params),
1353 ICPU(0x57, knl_params),
1356 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1358 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
1359 ICPU(0x56, core_params),
1363 static int intel_pstate_init_cpu(unsigned int cpunum)
1365 struct cpudata *cpu;
1367 if (!all_cpu_data[cpunum])
1368 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
1370 if (!all_cpu_data[cpunum])
1373 cpu = all_cpu_data[cpunum];
1378 intel_pstate_hwp_enable(cpu);
1379 pid_params.sample_rate_ms = 50;
1380 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1383 intel_pstate_get_cpu_pstates(cpu);
1385 intel_pstate_busy_pid_reset(cpu);
1387 pr_debug("controlling: cpu %d\n", cpunum);
1392 static unsigned int intel_pstate_get(unsigned int cpu_num)
1394 struct cpudata *cpu = all_cpu_data[cpu_num];
1396 return cpu ? get_avg_frequency(cpu) : 0;
1399 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1401 struct cpudata *cpu = all_cpu_data[cpu_num];
1403 if (cpu->update_util_set)
1406 /* Prevent intel_pstate_update_util() from using stale data. */
1407 cpu->sample.time = 0;
1408 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1409 intel_pstate_update_util);
1410 cpu->update_util_set = true;
1413 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1415 struct cpudata *cpu_data = all_cpu_data[cpu];
1417 if (!cpu_data->update_util_set)
1420 cpufreq_remove_update_util_hook(cpu);
1421 cpu_data->update_util_set = false;
1422 synchronize_sched();
1425 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1427 limits->no_turbo = 0;
1428 limits->turbo_disabled = 0;
1429 limits->max_perf_pct = 100;
1430 limits->max_perf = int_tofp(1);
1431 limits->min_perf_pct = 100;
1432 limits->min_perf = int_tofp(1);
1433 limits->max_policy_pct = 100;
1434 limits->max_sysfs_pct = 100;
1435 limits->min_policy_pct = 0;
1436 limits->min_sysfs_pct = 0;
1439 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1441 struct cpudata *cpu;
1443 if (!policy->cpuinfo.max_freq)
1446 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1447 policy->cpuinfo.max_freq, policy->max);
1449 cpu = all_cpu_data[0];
1450 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1451 policy->max < policy->cpuinfo.max_freq &&
1452 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1453 pr_debug("policy->max > max non turbo frequency\n");
1454 policy->max = policy->cpuinfo.max_freq;
1457 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1458 limits = &performance_limits;
1459 if (policy->max >= policy->cpuinfo.max_freq) {
1460 pr_debug("set performance\n");
1461 intel_pstate_set_performance_limits(limits);
1465 pr_debug("set powersave\n");
1466 limits = &powersave_limits;
1469 limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
1470 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100);
1471 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1472 policy->cpuinfo.max_freq);
1473 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100);
1475 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1476 limits->min_perf_pct = max(limits->min_policy_pct,
1477 limits->min_sysfs_pct);
1478 limits->min_perf_pct = min(limits->max_policy_pct,
1479 limits->min_perf_pct);
1480 limits->max_perf_pct = min(limits->max_policy_pct,
1481 limits->max_sysfs_pct);
1482 limits->max_perf_pct = max(limits->min_policy_pct,
1483 limits->max_perf_pct);
1485 /* Make sure min_perf_pct <= max_perf_pct */
1486 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1488 limits->min_perf = div_fp(limits->min_perf_pct, 100);
1489 limits->max_perf = div_fp(limits->max_perf_pct, 100);
1490 limits->max_perf = round_up(limits->max_perf, FRAC_BITS);
1493 intel_pstate_set_update_util_hook(policy->cpu);
1495 intel_pstate_hwp_set_policy(policy);
1500 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1502 cpufreq_verify_within_cpu_limits(policy);
1504 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1505 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1511 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1513 int cpu_num = policy->cpu;
1514 struct cpudata *cpu = all_cpu_data[cpu_num];
1516 pr_debug("CPU %d exiting\n", cpu_num);
1518 intel_pstate_clear_update_util_hook(cpu_num);
1523 intel_pstate_set_min_pstate(cpu);
1526 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1528 struct cpudata *cpu;
1531 rc = intel_pstate_init_cpu(policy->cpu);
1535 cpu = all_cpu_data[policy->cpu];
1537 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
1538 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1540 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1542 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1543 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1545 /* cpuinfo and default policy values */
1546 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1547 update_turbo_state();
1548 policy->cpuinfo.max_freq = limits->turbo_disabled ?
1549 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1550 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1552 intel_pstate_init_acpi_perf_limits(policy);
1553 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1554 cpumask_set_cpu(policy->cpu, policy->cpus);
1559 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1561 intel_pstate_exit_perf_limits(policy);
1566 static struct cpufreq_driver intel_pstate_driver = {
1567 .flags = CPUFREQ_CONST_LOOPS,
1568 .verify = intel_pstate_verify_policy,
1569 .setpolicy = intel_pstate_set_policy,
1570 .resume = intel_pstate_hwp_set_policy,
1571 .get = intel_pstate_get,
1572 .init = intel_pstate_cpu_init,
1573 .exit = intel_pstate_cpu_exit,
1574 .stop_cpu = intel_pstate_stop_cpu,
1575 .name = "intel_pstate",
1578 static int __initdata no_load;
1579 static int __initdata no_hwp;
1580 static int __initdata hwp_only;
1581 static unsigned int force_load;
1583 static int intel_pstate_msrs_not_valid(void)
1585 if (!pstate_funcs.get_max() ||
1586 !pstate_funcs.get_min() ||
1587 !pstate_funcs.get_turbo())
1593 static void copy_pid_params(struct pstate_adjust_policy *policy)
1595 pid_params.sample_rate_ms = policy->sample_rate_ms;
1596 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
1597 pid_params.p_gain_pct = policy->p_gain_pct;
1598 pid_params.i_gain_pct = policy->i_gain_pct;
1599 pid_params.d_gain_pct = policy->d_gain_pct;
1600 pid_params.deadband = policy->deadband;
1601 pid_params.setpoint = policy->setpoint;
1604 static void copy_cpu_funcs(struct pstate_funcs *funcs)
1606 pstate_funcs.get_max = funcs->get_max;
1607 pstate_funcs.get_max_physical = funcs->get_max_physical;
1608 pstate_funcs.get_min = funcs->get_min;
1609 pstate_funcs.get_turbo = funcs->get_turbo;
1610 pstate_funcs.get_scaling = funcs->get_scaling;
1611 pstate_funcs.get_val = funcs->get_val;
1612 pstate_funcs.get_vid = funcs->get_vid;
1613 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
1619 static bool intel_pstate_no_acpi_pss(void)
1623 for_each_possible_cpu(i) {
1625 union acpi_object *pss;
1626 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1627 struct acpi_processor *pr = per_cpu(processors, i);
1632 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1633 if (ACPI_FAILURE(status))
1636 pss = buffer.pointer;
1637 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1648 static bool intel_pstate_has_acpi_ppc(void)
1652 for_each_possible_cpu(i) {
1653 struct acpi_processor *pr = per_cpu(processors, i);
1657 if (acpi_has_method(pr->handle, "_PPC"))
1668 struct hw_vendor_info {
1670 char oem_id[ACPI_OEM_ID_SIZE];
1671 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
1675 /* Hardware vendor-specific info that has its own power management modes */
1676 static struct hw_vendor_info vendor_info[] = {
1677 {1, "HP ", "ProLiant", PSS},
1678 {1, "ORACLE", "X4-2 ", PPC},
1679 {1, "ORACLE", "X4-2L ", PPC},
1680 {1, "ORACLE", "X4-2B ", PPC},
1681 {1, "ORACLE", "X3-2 ", PPC},
1682 {1, "ORACLE", "X3-2L ", PPC},
1683 {1, "ORACLE", "X3-2B ", PPC},
1684 {1, "ORACLE", "X4470M2 ", PPC},
1685 {1, "ORACLE", "X4270M3 ", PPC},
1686 {1, "ORACLE", "X4270M2 ", PPC},
1687 {1, "ORACLE", "X4170M2 ", PPC},
1688 {1, "ORACLE", "X4170 M3", PPC},
1689 {1, "ORACLE", "X4275 M3", PPC},
1690 {1, "ORACLE", "X6-2 ", PPC},
1691 {1, "ORACLE", "Sudbury ", PPC},
1695 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1697 struct acpi_table_header hdr;
1698 struct hw_vendor_info *v_info;
1699 const struct x86_cpu_id *id;
1702 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1704 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1705 if ( misc_pwr & (1 << 8))
1709 if (acpi_disabled ||
1710 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
1713 for (v_info = vendor_info; v_info->valid; v_info++) {
1714 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
1715 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1716 ACPI_OEM_TABLE_ID_SIZE))
1717 switch (v_info->oem_pwr_table) {
1719 return intel_pstate_no_acpi_pss();
1721 return intel_pstate_has_acpi_ppc() &&
1728 #else /* CONFIG_ACPI not enabled */
1729 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1730 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1731 #endif /* CONFIG_ACPI */
1733 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
1734 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
1738 static int __init intel_pstate_init(void)
1741 const struct x86_cpu_id *id;
1742 struct cpu_defaults *cpu_def;
1747 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
1748 copy_cpu_funcs(&core_params.funcs);
1750 goto hwp_cpu_matched;
1753 id = x86_match_cpu(intel_pstate_cpu_ids);
1757 cpu_def = (struct cpu_defaults *)id->driver_data;
1759 copy_pid_params(&cpu_def->pid_policy);
1760 copy_cpu_funcs(&cpu_def->funcs);
1762 if (intel_pstate_msrs_not_valid())
1767 * The Intel pstate driver will be ignored if the platform
1768 * firmware has its own power management modes.
1770 if (intel_pstate_platform_pwr_mgmt_exists())
1773 pr_info("Intel P-state driver initializing\n");
1775 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1779 if (!hwp_active && hwp_only)
1782 rc = cpufreq_register_driver(&intel_pstate_driver);
1786 intel_pstate_debug_expose_params();
1787 intel_pstate_sysfs_expose_params();
1790 pr_info("HWP enabled\n");
1795 for_each_online_cpu(cpu) {
1796 if (all_cpu_data[cpu]) {
1797 intel_pstate_clear_update_util_hook(cpu);
1798 kfree(all_cpu_data[cpu]);
1803 vfree(all_cpu_data);
1806 device_initcall(intel_pstate_init);
1808 static int __init intel_pstate_setup(char *str)
1813 if (!strcmp(str, "disable"))
1815 if (!strcmp(str, "no_hwp")) {
1816 pr_info("HWP disabled\n");
1819 if (!strcmp(str, "force"))
1821 if (!strcmp(str, "hwp_only"))
1825 if (!strcmp(str, "support_acpi_ppc"))
1831 early_param("intel_pstate", intel_pstate_setup);
1833 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1834 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1835 MODULE_LICENSE("GPL");