2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/acpi.h>
30 #include <linux/vmalloc.h>
31 #include <trace/events/power.h>
33 #include <asm/div64.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/cpufeature.h>
37 #include <asm/intel-family.h>
39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
58 static inline int32_t mul_fp(int32_t x, int32_t y)
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 static inline int32_t div_fp(s64 x, s64 y)
65 return div64_s64((int64_t)x << FRAC_BITS, y);
68 static inline int ceiling_fp(int32_t x)
73 mask = (1 << FRAC_BITS) - 1;
79 static inline int32_t percent_fp(int percent)
81 return div_fp(percent, 100);
84 static inline u64 mul_ext_fp(u64 x, u64 y)
86 return (x * y) >> EXT_FRAC_BITS;
89 static inline u64 div_ext_fp(u64 x, u64 y)
91 return div64_u64(x << EXT_FRAC_BITS, y);
94 static inline int32_t percent_ext_fp(int percent)
96 return div_ext_fp(percent, 100);
100 * struct sample - Store performance sample
101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
104 * P state. This can be different than core_avg_perf
105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
112 * @time: Current time from scheduler
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
118 int32_t core_avg_perf;
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
136 * @turbo_pstate: Max Turbo P state possible for this platform
137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
140 * Stores the per cpu model P state limits and current P state.
146 int max_pstate_physical;
149 unsigned int max_freq;
150 unsigned int turbo_freq;
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
185 struct global_params {
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
195 * @policy: CPUFreq policy value
196 * @update_util: CPUFreq utility callback information
197 * @update_util_set: CPUFreq utility callback is set
198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
202 * @last_sample_time: Last Sample time
203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
224 * @hwp_req_cached: Cached value of the last HWP Request MSR
225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
226 * @last_io_update: Last time when IO wake flag was set
227 * @sched_flags: Store scheduler flags for possible cross CPU update
228 * @hwp_boost_min: Last HWP boosted min performance
230 * This structure stores per CPU instance data for all CPUs.
236 struct update_util_data update_util;
237 bool update_util_set;
239 struct pstate_data pstate;
243 u64 last_sample_time;
244 u64 aperf_mperf_shift;
248 u64 prev_cummulative_iowait;
249 struct sample sample;
250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
256 unsigned int iowait_boost;
264 unsigned int sched_flags;
268 static struct cpudata **all_cpu_data;
271 * struct pstate_funcs - Per CPU model specific callbacks
272 * @get_max: Callback to get maximum non turbo effective P state
273 * @get_max_physical: Callback to get maximum non turbo physical P state
274 * @get_min: Callback to get minimum P state
275 * @get_turbo: Callback to get turbo P state
276 * @get_scaling: Callback to get frequency scaling factor
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
283 struct pstate_funcs {
284 int (*get_max)(void);
285 int (*get_max_physical)(void);
286 int (*get_min)(void);
287 int (*get_turbo)(void);
288 int (*get_scaling)(void);
289 int (*get_aperf_mperf_shift)(void);
290 u64 (*get_val)(struct cpudata*, int pstate);
291 void (*get_vid)(struct cpudata *);
294 static struct pstate_funcs pstate_funcs __read_mostly;
296 static int hwp_active __read_mostly;
297 static int hwp_mode_bdw __read_mostly;
298 static bool per_cpu_limits __read_mostly;
299 static bool hwp_boost __read_mostly;
301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304 static bool acpi_ppc;
307 static struct global_params global;
309 static DEFINE_MUTEX(intel_pstate_driver_lock);
310 static DEFINE_MUTEX(intel_pstate_limits_lock);
314 static bool intel_pstate_acpi_pm_profile_server(void)
316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
323 static bool intel_pstate_get_ppc_enable_status(void)
325 if (intel_pstate_acpi_pm_profile_server())
331 #ifdef CONFIG_ACPI_CPPC_LIB
333 /* The work item is needed to avoid CPU hotplug locking issues */
334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
336 sched_set_itmt_support();
339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
341 static void intel_pstate_set_itmt_prio(int cpu)
343 struct cppc_perf_caps cppc_perf;
344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
347 ret = cppc_get_perf_caps(cpu, &cppc_perf);
352 * The priorities can be set regardless of whether or not
353 * sched_set_itmt_support(true) has been called and it is valid to
354 * update them at any time after it has been called.
356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
358 if (max_highest_perf <= min_highest_perf) {
359 if (cppc_perf.highest_perf > max_highest_perf)
360 max_highest_perf = cppc_perf.highest_perf;
362 if (cppc_perf.highest_perf < min_highest_perf)
363 min_highest_perf = cppc_perf.highest_perf;
365 if (max_highest_perf > min_highest_perf) {
367 * This code can be run during CPU online under the
368 * CPU hotplug locks, so sched_set_itmt_support()
369 * cannot be called from here. Queue up a work item
372 schedule_work(&sched_itmt_work);
377 static int intel_pstate_get_cppc_guranteed(int cpu)
379 struct cppc_perf_caps cppc_perf;
382 ret = cppc_get_perf_caps(cpu, &cppc_perf);
386 return cppc_perf.guaranteed_perf;
389 #else /* CONFIG_ACPI_CPPC_LIB */
390 static void intel_pstate_set_itmt_prio(int cpu)
393 #endif /* CONFIG_ACPI_CPPC_LIB */
395 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
402 intel_pstate_set_itmt_prio(policy->cpu);
406 if (!intel_pstate_get_ppc_enable_status())
409 cpu = all_cpu_data[policy->cpu];
411 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
417 * Check if the control value in _PSS is for PERF_CTL MSR, which should
418 * guarantee that the states returned by it map to the states in our
421 if (cpu->acpi_perf_data.control_register.space_id !=
422 ACPI_ADR_SPACE_FIXED_HARDWARE)
426 * If there is only one entry _PSS, simply ignore _PSS and continue as
427 * usual without taking _PSS into account
429 if (cpu->acpi_perf_data.state_count < 2)
432 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
433 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
434 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
435 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
436 (u32) cpu->acpi_perf_data.states[i].core_frequency,
437 (u32) cpu->acpi_perf_data.states[i].power,
438 (u32) cpu->acpi_perf_data.states[i].control);
442 * The _PSS table doesn't contain whole turbo frequency range.
443 * This just contains +1 MHZ above the max non turbo frequency,
444 * with control value corresponding to max turbo ratio. But
445 * when cpufreq set policy is called, it will call with this
446 * max frequency, which will cause a reduced performance as
447 * this driver uses real max turbo frequency as the max
448 * frequency. So correct this frequency in _PSS table to
449 * correct max turbo frequency based on the turbo state.
450 * Also need to convert to MHz as _PSS freq is in MHz.
452 if (!global.turbo_disabled)
453 cpu->acpi_perf_data.states[0].core_frequency =
454 policy->cpuinfo.max_freq / 1000;
455 cpu->valid_pss_table = true;
456 pr_debug("_PPC limits will be enforced\n");
461 cpu->valid_pss_table = false;
462 acpi_processor_unregister_performance(policy->cpu);
465 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
469 cpu = all_cpu_data[policy->cpu];
470 if (!cpu->valid_pss_table)
473 acpi_processor_unregister_performance(policy->cpu);
475 #else /* CONFIG_ACPI */
476 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
480 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
484 static inline bool intel_pstate_acpi_pm_profile_server(void)
488 #endif /* CONFIG_ACPI */
490 #ifndef CONFIG_ACPI_CPPC_LIB
491 static int intel_pstate_get_cppc_guranteed(int cpu)
495 #endif /* CONFIG_ACPI_CPPC_LIB */
497 static inline void update_turbo_state(void)
502 cpu = all_cpu_data[0];
503 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
504 global.turbo_disabled =
505 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
506 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
509 static int min_perf_pct_min(void)
511 struct cpudata *cpu = all_cpu_data[0];
512 int turbo_pstate = cpu->pstate.turbo_pstate;
514 return turbo_pstate ?
515 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
518 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
523 if (!static_cpu_has(X86_FEATURE_EPB))
526 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
530 return (s16)(epb & 0x0f);
533 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
537 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
539 * When hwp_req_data is 0, means that caller didn't read
540 * MSR_HWP_REQUEST, so need to read and get EPP.
543 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
548 epp = (hwp_req_data >> 24) & 0xff;
550 /* When there is no EPP present, HWP uses EPB settings */
551 epp = intel_pstate_get_epb(cpu_data);
557 static int intel_pstate_set_epb(int cpu, s16 pref)
562 if (!static_cpu_has(X86_FEATURE_EPB))
565 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
569 epb = (epb & ~0x0f) | pref;
570 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
576 * EPP/EPB display strings corresponding to EPP index in the
577 * energy_perf_strings[]
579 *-------------------------------------
582 * 2 balance_performance
586 static const char * const energy_perf_strings[] = {
589 "balance_performance",
594 static const unsigned int epp_values[] = {
596 HWP_EPP_BALANCE_PERFORMANCE,
597 HWP_EPP_BALANCE_POWERSAVE,
601 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
606 epp = intel_pstate_get_epp(cpu_data, 0);
610 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
611 if (epp == HWP_EPP_PERFORMANCE)
613 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
615 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
619 } else if (static_cpu_has(X86_FEATURE_EPB)) {
622 * 0x00-0x03 : Performance
623 * 0x04-0x07 : Balance performance
624 * 0x08-0x0B : Balance power
626 * The EPB is a 4 bit value, but our ranges restrict the
627 * value which can be set. Here only using top two bits
630 index = (epp >> 2) + 1;
636 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
643 epp = cpu_data->epp_default;
645 mutex_lock(&intel_pstate_limits_lock);
647 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
650 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
654 value &= ~GENMASK_ULL(31, 24);
657 epp = epp_values[pref_index - 1];
659 value |= (u64)epp << 24;
660 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
663 epp = (pref_index - 1) << 2;
664 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
667 mutex_unlock(&intel_pstate_limits_lock);
672 static ssize_t show_energy_performance_available_preferences(
673 struct cpufreq_policy *policy, char *buf)
678 while (energy_perf_strings[i] != NULL)
679 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
681 ret += sprintf(&buf[ret], "\n");
686 cpufreq_freq_attr_ro(energy_performance_available_preferences);
688 static ssize_t store_energy_performance_preference(
689 struct cpufreq_policy *policy, const char *buf, size_t count)
691 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
692 char str_preference[21];
695 ret = sscanf(buf, "%20s", str_preference);
699 ret = match_string(energy_perf_strings, -1, str_preference);
703 intel_pstate_set_energy_pref_index(cpu_data, ret);
707 static ssize_t show_energy_performance_preference(
708 struct cpufreq_policy *policy, char *buf)
710 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
713 preference = intel_pstate_get_energy_pref_index(cpu_data);
717 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
720 cpufreq_freq_attr_rw(energy_performance_preference);
722 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
728 ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
730 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
731 ratio = HWP_GUARANTEED_PERF(cap);
734 cpu = all_cpu_data[policy->cpu];
736 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
739 cpufreq_freq_attr_ro(base_frequency);
741 static struct freq_attr *hwp_cpufreq_attrs[] = {
742 &energy_performance_preference,
743 &energy_performance_available_preferences,
748 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
753 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
754 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
756 *current_max = HWP_GUARANTEED_PERF(cap);
758 *current_max = HWP_HIGHEST_PERF(cap);
760 *phy_max = HWP_HIGHEST_PERF(cap);
763 static void intel_pstate_hwp_set(unsigned int cpu)
765 struct cpudata *cpu_data = all_cpu_data[cpu];
770 max = cpu_data->max_perf_ratio;
771 min = cpu_data->min_perf_ratio;
773 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
776 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
778 value &= ~HWP_MIN_PERF(~0L);
779 value |= HWP_MIN_PERF(min);
781 value &= ~HWP_MAX_PERF(~0L);
782 value |= HWP_MAX_PERF(max);
784 if (cpu_data->epp_policy == cpu_data->policy)
787 cpu_data->epp_policy = cpu_data->policy;
789 if (cpu_data->epp_saved >= 0) {
790 epp = cpu_data->epp_saved;
791 cpu_data->epp_saved = -EINVAL;
795 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
796 epp = intel_pstate_get_epp(cpu_data, value);
797 cpu_data->epp_powersave = epp;
798 /* If EPP read was failed, then don't try to write */
804 /* skip setting EPP, when saved value is invalid */
805 if (cpu_data->epp_powersave < 0)
809 * No need to restore EPP when it is not zero. This
811 * - Policy is not changed
812 * - user has manually changed
813 * - Error reading EPB
815 epp = intel_pstate_get_epp(cpu_data, value);
819 epp = cpu_data->epp_powersave;
822 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
823 value &= ~GENMASK_ULL(31, 24);
824 value |= (u64)epp << 24;
826 intel_pstate_set_epb(cpu, epp);
829 WRITE_ONCE(cpu_data->hwp_req_cached, value);
830 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
833 static void intel_pstate_hwp_force_min_perf(int cpu)
838 value = all_cpu_data[cpu]->hwp_req_cached;
839 value &= ~GENMASK_ULL(31, 0);
840 min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
842 /* Set hwp_max = hwp_min */
843 value |= HWP_MAX_PERF(min_perf);
844 value |= HWP_MIN_PERF(min_perf);
846 /* Set EPP/EPB to min */
847 if (static_cpu_has(X86_FEATURE_HWP_EPP))
848 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
850 intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE);
852 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
855 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
857 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
862 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
867 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
869 static int intel_pstate_resume(struct cpufreq_policy *policy)
874 mutex_lock(&intel_pstate_limits_lock);
876 if (policy->cpu == 0)
877 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
879 all_cpu_data[policy->cpu]->epp_policy = 0;
880 intel_pstate_hwp_set(policy->cpu);
882 mutex_unlock(&intel_pstate_limits_lock);
887 static void intel_pstate_update_policies(void)
891 for_each_possible_cpu(cpu)
892 cpufreq_update_policy(cpu);
895 /************************** sysfs begin ************************/
896 #define show_one(file_name, object) \
897 static ssize_t show_##file_name \
898 (struct kobject *kobj, struct attribute *attr, char *buf) \
900 return sprintf(buf, "%u\n", global.object); \
903 static ssize_t intel_pstate_show_status(char *buf);
904 static int intel_pstate_update_status(const char *buf, size_t size);
906 static ssize_t show_status(struct kobject *kobj,
907 struct attribute *attr, char *buf)
911 mutex_lock(&intel_pstate_driver_lock);
912 ret = intel_pstate_show_status(buf);
913 mutex_unlock(&intel_pstate_driver_lock);
918 static ssize_t store_status(struct kobject *a, struct attribute *b,
919 const char *buf, size_t count)
921 char *p = memchr(buf, '\n', count);
924 mutex_lock(&intel_pstate_driver_lock);
925 ret = intel_pstate_update_status(buf, p ? p - buf : count);
926 mutex_unlock(&intel_pstate_driver_lock);
928 return ret < 0 ? ret : count;
931 static ssize_t show_turbo_pct(struct kobject *kobj,
932 struct attribute *attr, char *buf)
935 int total, no_turbo, turbo_pct;
938 mutex_lock(&intel_pstate_driver_lock);
940 if (!intel_pstate_driver) {
941 mutex_unlock(&intel_pstate_driver_lock);
945 cpu = all_cpu_data[0];
947 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
948 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
949 turbo_fp = div_fp(no_turbo, total);
950 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
952 mutex_unlock(&intel_pstate_driver_lock);
954 return sprintf(buf, "%u\n", turbo_pct);
957 static ssize_t show_num_pstates(struct kobject *kobj,
958 struct attribute *attr, char *buf)
963 mutex_lock(&intel_pstate_driver_lock);
965 if (!intel_pstate_driver) {
966 mutex_unlock(&intel_pstate_driver_lock);
970 cpu = all_cpu_data[0];
971 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
973 mutex_unlock(&intel_pstate_driver_lock);
975 return sprintf(buf, "%u\n", total);
978 static ssize_t show_no_turbo(struct kobject *kobj,
979 struct attribute *attr, char *buf)
983 mutex_lock(&intel_pstate_driver_lock);
985 if (!intel_pstate_driver) {
986 mutex_unlock(&intel_pstate_driver_lock);
990 update_turbo_state();
991 if (global.turbo_disabled)
992 ret = sprintf(buf, "%u\n", global.turbo_disabled);
994 ret = sprintf(buf, "%u\n", global.no_turbo);
996 mutex_unlock(&intel_pstate_driver_lock);
1001 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1002 const char *buf, size_t count)
1007 ret = sscanf(buf, "%u", &input);
1011 mutex_lock(&intel_pstate_driver_lock);
1013 if (!intel_pstate_driver) {
1014 mutex_unlock(&intel_pstate_driver_lock);
1018 mutex_lock(&intel_pstate_limits_lock);
1020 update_turbo_state();
1021 if (global.turbo_disabled) {
1022 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1023 mutex_unlock(&intel_pstate_limits_lock);
1024 mutex_unlock(&intel_pstate_driver_lock);
1028 global.no_turbo = clamp_t(int, input, 0, 1);
1030 if (global.no_turbo) {
1031 struct cpudata *cpu = all_cpu_data[0];
1032 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1034 /* Squash the global minimum into the permitted range. */
1035 if (global.min_perf_pct > pct)
1036 global.min_perf_pct = pct;
1039 mutex_unlock(&intel_pstate_limits_lock);
1041 intel_pstate_update_policies();
1043 mutex_unlock(&intel_pstate_driver_lock);
1048 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1049 const char *buf, size_t count)
1054 ret = sscanf(buf, "%u", &input);
1058 mutex_lock(&intel_pstate_driver_lock);
1060 if (!intel_pstate_driver) {
1061 mutex_unlock(&intel_pstate_driver_lock);
1065 mutex_lock(&intel_pstate_limits_lock);
1067 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1069 mutex_unlock(&intel_pstate_limits_lock);
1071 intel_pstate_update_policies();
1073 mutex_unlock(&intel_pstate_driver_lock);
1078 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1079 const char *buf, size_t count)
1084 ret = sscanf(buf, "%u", &input);
1088 mutex_lock(&intel_pstate_driver_lock);
1090 if (!intel_pstate_driver) {
1091 mutex_unlock(&intel_pstate_driver_lock);
1095 mutex_lock(&intel_pstate_limits_lock);
1097 global.min_perf_pct = clamp_t(int, input,
1098 min_perf_pct_min(), global.max_perf_pct);
1100 mutex_unlock(&intel_pstate_limits_lock);
1102 intel_pstate_update_policies();
1104 mutex_unlock(&intel_pstate_driver_lock);
1109 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1110 struct attribute *attr, char *buf)
1112 return sprintf(buf, "%u\n", hwp_boost);
1115 static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b,
1116 const char *buf, size_t count)
1121 ret = kstrtouint(buf, 10, &input);
1125 mutex_lock(&intel_pstate_driver_lock);
1126 hwp_boost = !!input;
1127 intel_pstate_update_policies();
1128 mutex_unlock(&intel_pstate_driver_lock);
1133 show_one(max_perf_pct, max_perf_pct);
1134 show_one(min_perf_pct, min_perf_pct);
1136 define_one_global_rw(status);
1137 define_one_global_rw(no_turbo);
1138 define_one_global_rw(max_perf_pct);
1139 define_one_global_rw(min_perf_pct);
1140 define_one_global_ro(turbo_pct);
1141 define_one_global_ro(num_pstates);
1142 define_one_global_rw(hwp_dynamic_boost);
1144 static struct attribute *intel_pstate_attributes[] = {
1152 static const struct attribute_group intel_pstate_attr_group = {
1153 .attrs = intel_pstate_attributes,
1156 static void __init intel_pstate_sysfs_expose_params(void)
1158 struct kobject *intel_pstate_kobject;
1161 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1162 &cpu_subsys.dev_root->kobj);
1163 if (WARN_ON(!intel_pstate_kobject))
1166 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1171 * If per cpu limits are enforced there are no global limits, so
1172 * return without creating max/min_perf_pct attributes
1177 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1180 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1184 rc = sysfs_create_file(intel_pstate_kobject,
1185 &hwp_dynamic_boost.attr);
1189 /************************** sysfs end ************************/
1191 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1193 /* First disable HWP notification interrupt as we don't process them */
1194 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1195 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1197 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1198 cpudata->epp_policy = 0;
1199 if (cpudata->epp_default == -EINVAL)
1200 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1203 #define MSR_IA32_POWER_CTL_BIT_EE 19
1205 /* Disable energy efficiency optimization */
1206 static void intel_pstate_disable_ee(int cpu)
1211 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1215 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1216 pr_info("Disabling energy efficiency optimization\n");
1217 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1218 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1222 static int atom_get_min_pstate(void)
1226 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1227 return (value >> 8) & 0x7F;
1230 static int atom_get_max_pstate(void)
1234 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1235 return (value >> 16) & 0x7F;
1238 static int atom_get_turbo_pstate(void)
1242 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1243 return value & 0x7F;
1246 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1252 val = (u64)pstate << 8;
1253 if (global.no_turbo && !global.turbo_disabled)
1254 val |= (u64)1 << 32;
1256 vid_fp = cpudata->vid.min + mul_fp(
1257 int_tofp(pstate - cpudata->pstate.min_pstate),
1258 cpudata->vid.ratio);
1260 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1261 vid = ceiling_fp(vid_fp);
1263 if (pstate > cpudata->pstate.max_pstate)
1264 vid = cpudata->vid.turbo;
1269 static int silvermont_get_scaling(void)
1273 /* Defined in Table 35-6 from SDM (Sept 2015) */
1274 static int silvermont_freq_table[] = {
1275 83300, 100000, 133300, 116700, 80000};
1277 rdmsrl(MSR_FSB_FREQ, value);
1281 return silvermont_freq_table[i];
1284 static int airmont_get_scaling(void)
1288 /* Defined in Table 35-10 from SDM (Sept 2015) */
1289 static int airmont_freq_table[] = {
1290 83300, 100000, 133300, 116700, 80000,
1291 93300, 90000, 88900, 87500};
1293 rdmsrl(MSR_FSB_FREQ, value);
1297 return airmont_freq_table[i];
1300 static void atom_get_vid(struct cpudata *cpudata)
1304 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1305 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1306 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1307 cpudata->vid.ratio = div_fp(
1308 cpudata->vid.max - cpudata->vid.min,
1309 int_tofp(cpudata->pstate.max_pstate -
1310 cpudata->pstate.min_pstate));
1312 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1313 cpudata->vid.turbo = value & 0x7f;
1316 static int core_get_min_pstate(void)
1320 rdmsrl(MSR_PLATFORM_INFO, value);
1321 return (value >> 40) & 0xFF;
1324 static int core_get_max_pstate_physical(void)
1328 rdmsrl(MSR_PLATFORM_INFO, value);
1329 return (value >> 8) & 0xFF;
1332 static int core_get_tdp_ratio(u64 plat_info)
1334 /* Check how many TDP levels present */
1335 if (plat_info & 0x600000000) {
1341 /* Get the TDP level (0, 1, 2) to get ratios */
1342 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1346 /* TDP MSR are continuous starting at 0x648 */
1347 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1348 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1352 /* For level 1 and 2, bits[23:16] contain the ratio */
1353 if (tdp_ctrl & 0x03)
1356 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1357 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1359 return (int)tdp_ratio;
1365 static int core_get_max_pstate(void)
1373 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1374 max_pstate = (plat_info >> 8) & 0xFF;
1376 tdp_ratio = core_get_tdp_ratio(plat_info);
1381 /* Turbo activation ratio is not used on HWP platforms */
1385 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1389 /* Do some sanity checking for safety */
1390 tar_levels = tar & 0xff;
1391 if (tdp_ratio - 1 == tar_levels) {
1392 max_pstate = tar_levels;
1393 pr_debug("max_pstate=TAC %x\n", max_pstate);
1400 static int core_get_turbo_pstate(void)
1405 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1406 nont = core_get_max_pstate();
1407 ret = (value) & 255;
1413 static inline int core_get_scaling(void)
1418 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1422 val = (u64)pstate << 8;
1423 if (global.no_turbo && !global.turbo_disabled)
1424 val |= (u64)1 << 32;
1429 static int knl_get_aperf_mperf_shift(void)
1434 static int knl_get_turbo_pstate(void)
1439 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1440 nont = core_get_max_pstate();
1441 ret = (((value) >> 8) & 0xFF);
1447 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1449 return global.no_turbo || global.turbo_disabled ?
1450 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1453 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1455 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1456 cpu->pstate.current_pstate = pstate;
1458 * Generally, there is no guarantee that this code will always run on
1459 * the CPU being updated, so force the register update to run on the
1462 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1463 pstate_funcs.get_val(cpu, pstate));
1466 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1468 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1471 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1475 update_turbo_state();
1476 pstate = intel_pstate_get_base_pstate(cpu);
1477 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1478 intel_pstate_set_pstate(cpu, pstate);
1481 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1483 cpu->pstate.min_pstate = pstate_funcs.get_min();
1484 cpu->pstate.max_pstate = pstate_funcs.get_max();
1485 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1486 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1487 cpu->pstate.scaling = pstate_funcs.get_scaling();
1488 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1490 if (hwp_active && !hwp_mode_bdw) {
1491 unsigned int phy_max, current_max;
1493 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max);
1494 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1496 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1499 if (pstate_funcs.get_aperf_mperf_shift)
1500 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1502 if (pstate_funcs.get_vid)
1503 pstate_funcs.get_vid(cpu);
1505 intel_pstate_set_min_pstate(cpu);
1509 * Long hold time will keep high perf limits for long time,
1510 * which negatively impacts perf/watt for some workloads,
1511 * like specpower. 3ms is based on experiements on some
1514 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1516 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1518 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1519 u32 max_limit = (hwp_req & 0xff00) >> 8;
1520 u32 min_limit = (hwp_req & 0xff);
1524 * Cases to consider (User changes via sysfs or boot time):
1525 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1527 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1528 * Should result in one level boost only for P0.
1529 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1530 * Should result in two level boost:
1531 * (min + p1)/2 and P1.
1532 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1533 * Should result in three level boost:
1534 * (min + p1)/2, P1 and P0.
1537 /* If max and min are equal or already at max, nothing to boost */
1538 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1541 if (!cpu->hwp_boost_min)
1542 cpu->hwp_boost_min = min_limit;
1544 /* level at half way mark between min and guranteed */
1545 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1547 if (cpu->hwp_boost_min < boost_level1)
1548 cpu->hwp_boost_min = boost_level1;
1549 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1550 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1551 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1552 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1553 cpu->hwp_boost_min = max_limit;
1557 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1558 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1559 cpu->last_update = cpu->sample.time;
1562 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1564 if (cpu->hwp_boost_min) {
1567 /* Check if we are idle for hold time to boost down */
1568 expired = time_after64(cpu->sample.time, cpu->last_update +
1569 hwp_boost_hold_time_ns);
1571 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1572 cpu->hwp_boost_min = 0;
1575 cpu->last_update = cpu->sample.time;
1578 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1581 cpu->sample.time = time;
1583 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1586 cpu->sched_flags = 0;
1588 * Set iowait_boost flag and update time. Since IO WAIT flag
1589 * is set all the time, we can't just conclude that there is
1590 * some IO bound activity is scheduled on this CPU with just
1591 * one occurrence. If we receive at least two in two
1592 * consecutive ticks, then we treat as boost candidate.
1594 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1597 cpu->last_io_update = time;
1600 intel_pstate_hwp_boost_up(cpu);
1603 intel_pstate_hwp_boost_down(cpu);
1607 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1608 u64 time, unsigned int flags)
1610 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1612 cpu->sched_flags |= flags;
1614 if (smp_processor_id() == cpu->cpu)
1615 intel_pstate_update_util_hwp_local(cpu, time);
1618 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1620 struct sample *sample = &cpu->sample;
1622 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1625 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1628 unsigned long flags;
1631 local_irq_save(flags);
1632 rdmsrl(MSR_IA32_APERF, aperf);
1633 rdmsrl(MSR_IA32_MPERF, mperf);
1635 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1636 local_irq_restore(flags);
1639 local_irq_restore(flags);
1641 cpu->last_sample_time = cpu->sample.time;
1642 cpu->sample.time = time;
1643 cpu->sample.aperf = aperf;
1644 cpu->sample.mperf = mperf;
1645 cpu->sample.tsc = tsc;
1646 cpu->sample.aperf -= cpu->prev_aperf;
1647 cpu->sample.mperf -= cpu->prev_mperf;
1648 cpu->sample.tsc -= cpu->prev_tsc;
1650 cpu->prev_aperf = aperf;
1651 cpu->prev_mperf = mperf;
1652 cpu->prev_tsc = tsc;
1654 * First time this function is invoked in a given cycle, all of the
1655 * previous sample data fields are equal to zero or stale and they must
1656 * be populated with meaningful numbers for things to work, so assume
1657 * that sample.time will always be reset before setting the utilization
1658 * update hook and make the caller skip the sample then.
1660 if (cpu->last_sample_time) {
1661 intel_pstate_calc_avg_perf(cpu);
1667 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1669 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1672 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1674 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1675 cpu->sample.core_avg_perf);
1678 static inline int32_t get_target_pstate(struct cpudata *cpu)
1680 struct sample *sample = &cpu->sample;
1681 int32_t busy_frac, boost;
1682 int target, avg_pstate;
1684 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1687 boost = cpu->iowait_boost;
1688 cpu->iowait_boost >>= 1;
1690 if (busy_frac < boost)
1693 sample->busy_scaled = busy_frac * 100;
1695 target = global.no_turbo || global.turbo_disabled ?
1696 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1697 target += target >> 2;
1698 target = mul_fp(target, busy_frac);
1699 if (target < cpu->pstate.min_pstate)
1700 target = cpu->pstate.min_pstate;
1703 * If the average P-state during the previous cycle was higher than the
1704 * current target, add 50% of the difference to the target to reduce
1705 * possible performance oscillations and offset possible performance
1706 * loss related to moving the workload from one CPU to another within
1709 avg_pstate = get_avg_pstate(cpu);
1710 if (avg_pstate > target)
1711 target += (avg_pstate - target) >> 1;
1716 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1718 int max_pstate = intel_pstate_get_base_pstate(cpu);
1721 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1722 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1723 return clamp_t(int, pstate, min_pstate, max_pstate);
1726 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1728 if (pstate == cpu->pstate.current_pstate)
1731 cpu->pstate.current_pstate = pstate;
1732 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1735 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1737 int from = cpu->pstate.current_pstate;
1738 struct sample *sample;
1741 update_turbo_state();
1743 target_pstate = get_target_pstate(cpu);
1744 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1745 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1746 intel_pstate_update_pstate(cpu, target_pstate);
1748 sample = &cpu->sample;
1749 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1750 fp_toint(sample->busy_scaled),
1752 cpu->pstate.current_pstate,
1756 get_avg_frequency(cpu),
1757 fp_toint(cpu->iowait_boost * 100));
1760 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1763 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1766 /* Don't allow remote callbacks */
1767 if (smp_processor_id() != cpu->cpu)
1770 if (flags & SCHED_CPUFREQ_IOWAIT) {
1771 cpu->iowait_boost = int_tofp(1);
1772 cpu->last_update = time;
1774 * The last time the busy was 100% so P-state was max anyway
1775 * so avoid overhead of computation.
1777 if (fp_toint(cpu->sample.busy_scaled) == 100)
1781 } else if (cpu->iowait_boost) {
1782 /* Clear iowait_boost if the CPU may have been idle. */
1783 delta_ns = time - cpu->last_update;
1784 if (delta_ns > TICK_NSEC)
1785 cpu->iowait_boost = 0;
1787 cpu->last_update = time;
1788 delta_ns = time - cpu->sample.time;
1789 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1793 if (intel_pstate_sample(cpu, time))
1794 intel_pstate_adjust_pstate(cpu);
1797 static struct pstate_funcs core_funcs = {
1798 .get_max = core_get_max_pstate,
1799 .get_max_physical = core_get_max_pstate_physical,
1800 .get_min = core_get_min_pstate,
1801 .get_turbo = core_get_turbo_pstate,
1802 .get_scaling = core_get_scaling,
1803 .get_val = core_get_val,
1806 static const struct pstate_funcs silvermont_funcs = {
1807 .get_max = atom_get_max_pstate,
1808 .get_max_physical = atom_get_max_pstate,
1809 .get_min = atom_get_min_pstate,
1810 .get_turbo = atom_get_turbo_pstate,
1811 .get_val = atom_get_val,
1812 .get_scaling = silvermont_get_scaling,
1813 .get_vid = atom_get_vid,
1816 static const struct pstate_funcs airmont_funcs = {
1817 .get_max = atom_get_max_pstate,
1818 .get_max_physical = atom_get_max_pstate,
1819 .get_min = atom_get_min_pstate,
1820 .get_turbo = atom_get_turbo_pstate,
1821 .get_val = atom_get_val,
1822 .get_scaling = airmont_get_scaling,
1823 .get_vid = atom_get_vid,
1826 static const struct pstate_funcs knl_funcs = {
1827 .get_max = core_get_max_pstate,
1828 .get_max_physical = core_get_max_pstate_physical,
1829 .get_min = core_get_min_pstate,
1830 .get_turbo = knl_get_turbo_pstate,
1831 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1832 .get_scaling = core_get_scaling,
1833 .get_val = core_get_val,
1836 #define ICPU(model, policy) \
1837 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1838 (unsigned long)&policy }
1840 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1841 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1842 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1843 ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
1844 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1845 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1846 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1847 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1848 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1849 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1850 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1851 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1852 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1853 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1854 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1855 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1856 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1857 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1858 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1859 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1860 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, core_funcs),
1861 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1864 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1866 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1867 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1868 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1869 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1873 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1874 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1878 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1879 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1880 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1884 static int intel_pstate_init_cpu(unsigned int cpunum)
1886 struct cpudata *cpu;
1888 cpu = all_cpu_data[cpunum];
1891 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1895 all_cpu_data[cpunum] = cpu;
1897 cpu->epp_default = -EINVAL;
1898 cpu->epp_powersave = -EINVAL;
1899 cpu->epp_saved = -EINVAL;
1902 cpu = all_cpu_data[cpunum];
1907 const struct x86_cpu_id *id;
1909 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1911 intel_pstate_disable_ee(cpunum);
1913 intel_pstate_hwp_enable(cpu);
1915 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1916 if (id && intel_pstate_acpi_pm_profile_server())
1920 intel_pstate_get_cpu_pstates(cpu);
1922 pr_debug("controlling: cpu %d\n", cpunum);
1927 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1929 struct cpudata *cpu = all_cpu_data[cpu_num];
1931 if (hwp_active && !hwp_boost)
1934 if (cpu->update_util_set)
1937 /* Prevent intel_pstate_update_util() from using stale data. */
1938 cpu->sample.time = 0;
1939 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1941 intel_pstate_update_util_hwp :
1942 intel_pstate_update_util));
1943 cpu->update_util_set = true;
1946 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1948 struct cpudata *cpu_data = all_cpu_data[cpu];
1950 if (!cpu_data->update_util_set)
1953 cpufreq_remove_update_util_hook(cpu);
1954 cpu_data->update_util_set = false;
1958 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1960 return global.turbo_disabled || global.no_turbo ?
1961 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1964 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1965 struct cpudata *cpu)
1967 int max_freq = intel_pstate_get_max_freq(cpu);
1968 int32_t max_policy_perf, min_policy_perf;
1969 int max_state, turbo_max;
1972 * HWP needs some special consideration, because on BDX the
1973 * HWP_REQUEST uses abstract value to represent performance
1974 * rather than pure ratios.
1977 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1979 max_state = intel_pstate_get_base_pstate(cpu);
1980 turbo_max = cpu->pstate.turbo_pstate;
1983 max_policy_perf = max_state * policy->max / max_freq;
1984 if (policy->max == policy->min) {
1985 min_policy_perf = max_policy_perf;
1987 min_policy_perf = max_state * policy->min / max_freq;
1988 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1989 0, max_policy_perf);
1992 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1993 policy->cpu, max_state,
1994 min_policy_perf, max_policy_perf);
1996 /* Normalize user input to [min_perf, max_perf] */
1997 if (per_cpu_limits) {
1998 cpu->min_perf_ratio = min_policy_perf;
1999 cpu->max_perf_ratio = max_policy_perf;
2001 int32_t global_min, global_max;
2003 /* Global limits are in percent of the maximum turbo P-state. */
2004 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2005 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2006 global_min = clamp_t(int32_t, global_min, 0, global_max);
2008 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2009 global_min, global_max);
2011 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2012 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2013 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2014 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2016 /* Make sure min_perf <= max_perf */
2017 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2018 cpu->max_perf_ratio);
2021 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2022 cpu->max_perf_ratio,
2023 cpu->min_perf_ratio);
2026 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2028 struct cpudata *cpu;
2030 if (!policy->cpuinfo.max_freq)
2033 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2034 policy->cpuinfo.max_freq, policy->max);
2036 cpu = all_cpu_data[policy->cpu];
2037 cpu->policy = policy->policy;
2039 mutex_lock(&intel_pstate_limits_lock);
2041 intel_pstate_update_perf_limits(policy, cpu);
2043 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2045 * NOHZ_FULL CPUs need this as the governor callback may not
2046 * be invoked on them.
2048 intel_pstate_clear_update_util_hook(policy->cpu);
2049 intel_pstate_max_within_limits(cpu);
2051 intel_pstate_set_update_util_hook(policy->cpu);
2056 * When hwp_boost was active before and dynamically it
2057 * was turned off, in that case we need to clear the
2061 intel_pstate_clear_update_util_hook(policy->cpu);
2062 intel_pstate_hwp_set(policy->cpu);
2065 mutex_unlock(&intel_pstate_limits_lock);
2070 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2071 struct cpudata *cpu)
2074 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2075 policy->max < policy->cpuinfo.max_freq &&
2076 policy->max > cpu->pstate.max_freq) {
2077 pr_debug("policy->max > max non turbo frequency\n");
2078 policy->max = policy->cpuinfo.max_freq;
2082 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2084 struct cpudata *cpu = all_cpu_data[policy->cpu];
2086 update_turbo_state();
2087 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2088 intel_pstate_get_max_freq(cpu));
2090 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2091 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2094 intel_pstate_adjust_policy_max(policy, cpu);
2099 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2101 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2104 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2106 pr_debug("CPU %d exiting\n", policy->cpu);
2108 intel_pstate_clear_update_util_hook(policy->cpu);
2110 intel_pstate_hwp_save_state(policy);
2111 intel_pstate_hwp_force_min_perf(policy->cpu);
2113 intel_cpufreq_stop_cpu(policy);
2117 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2119 intel_pstate_exit_perf_limits(policy);
2121 policy->fast_switch_possible = false;
2126 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2128 struct cpudata *cpu;
2131 rc = intel_pstate_init_cpu(policy->cpu);
2135 cpu = all_cpu_data[policy->cpu];
2137 cpu->max_perf_ratio = 0xFF;
2138 cpu->min_perf_ratio = 0;
2140 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2141 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2143 /* cpuinfo and default policy values */
2144 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2145 update_turbo_state();
2146 policy->cpuinfo.max_freq = global.turbo_disabled ?
2147 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2148 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2151 unsigned int max_freq;
2153 max_freq = global.turbo_disabled ?
2154 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2155 if (max_freq < policy->cpuinfo.max_freq)
2156 policy->cpuinfo.max_freq = max_freq;
2159 intel_pstate_init_acpi_perf_limits(policy);
2161 policy->fast_switch_possible = true;
2166 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2168 int ret = __intel_pstate_cpu_init(policy);
2173 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2174 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2176 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2181 static struct cpufreq_driver intel_pstate = {
2182 .flags = CPUFREQ_CONST_LOOPS,
2183 .verify = intel_pstate_verify_policy,
2184 .setpolicy = intel_pstate_set_policy,
2185 .suspend = intel_pstate_hwp_save_state,
2186 .resume = intel_pstate_resume,
2187 .init = intel_pstate_cpu_init,
2188 .exit = intel_pstate_cpu_exit,
2189 .stop_cpu = intel_pstate_stop_cpu,
2190 .name = "intel_pstate",
2193 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2195 struct cpudata *cpu = all_cpu_data[policy->cpu];
2197 update_turbo_state();
2198 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2199 intel_pstate_get_max_freq(cpu));
2201 intel_pstate_adjust_policy_max(policy, cpu);
2203 intel_pstate_update_perf_limits(policy, cpu);
2208 /* Use of trace in passive mode:
2210 * In passive mode the trace core_busy field (also known as the
2211 * performance field, and lablelled as such on the graphs; also known as
2212 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2213 * driver call was via the normal or fast switch path. Various graphs
2214 * output from the intel_pstate_tracer.py utility that include core_busy
2215 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2216 * so we use 10 to indicate the the normal path through the driver, and
2217 * 90 to indicate the fast switch path through the driver.
2218 * The scaled_busy field is not used, and is set to 0.
2221 #define INTEL_PSTATE_TRACE_TARGET 10
2222 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2224 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2226 struct sample *sample;
2228 if (!trace_pstate_sample_enabled())
2231 if (!intel_pstate_sample(cpu, ktime_get()))
2234 sample = &cpu->sample;
2235 trace_pstate_sample(trace_type,
2238 cpu->pstate.current_pstate,
2242 get_avg_frequency(cpu),
2243 fp_toint(cpu->iowait_boost * 100));
2246 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2247 unsigned int target_freq,
2248 unsigned int relation)
2250 struct cpudata *cpu = all_cpu_data[policy->cpu];
2251 struct cpufreq_freqs freqs;
2252 int target_pstate, old_pstate;
2254 update_turbo_state();
2256 freqs.old = policy->cur;
2257 freqs.new = target_freq;
2259 cpufreq_freq_transition_begin(policy, &freqs);
2261 case CPUFREQ_RELATION_L:
2262 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2264 case CPUFREQ_RELATION_H:
2265 target_pstate = freqs.new / cpu->pstate.scaling;
2268 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2271 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2272 old_pstate = cpu->pstate.current_pstate;
2273 if (target_pstate != cpu->pstate.current_pstate) {
2274 cpu->pstate.current_pstate = target_pstate;
2275 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2276 pstate_funcs.get_val(cpu, target_pstate));
2278 freqs.new = target_pstate * cpu->pstate.scaling;
2279 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2280 cpufreq_freq_transition_end(policy, &freqs, false);
2285 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2286 unsigned int target_freq)
2288 struct cpudata *cpu = all_cpu_data[policy->cpu];
2289 int target_pstate, old_pstate;
2291 update_turbo_state();
2293 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2294 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2295 old_pstate = cpu->pstate.current_pstate;
2296 intel_pstate_update_pstate(cpu, target_pstate);
2297 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2298 return target_pstate * cpu->pstate.scaling;
2301 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2303 int ret = __intel_pstate_cpu_init(policy);
2308 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2309 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2310 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2311 policy->cur = policy->cpuinfo.min_freq;
2316 static struct cpufreq_driver intel_cpufreq = {
2317 .flags = CPUFREQ_CONST_LOOPS,
2318 .verify = intel_cpufreq_verify_policy,
2319 .target = intel_cpufreq_target,
2320 .fast_switch = intel_cpufreq_fast_switch,
2321 .init = intel_cpufreq_cpu_init,
2322 .exit = intel_pstate_cpu_exit,
2323 .stop_cpu = intel_cpufreq_stop_cpu,
2324 .name = "intel_cpufreq",
2327 static struct cpufreq_driver *default_driver = &intel_pstate;
2329 static void intel_pstate_driver_cleanup(void)
2334 for_each_online_cpu(cpu) {
2335 if (all_cpu_data[cpu]) {
2336 if (intel_pstate_driver == &intel_pstate)
2337 intel_pstate_clear_update_util_hook(cpu);
2339 kfree(all_cpu_data[cpu]);
2340 all_cpu_data[cpu] = NULL;
2344 intel_pstate_driver = NULL;
2347 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2351 memset(&global, 0, sizeof(global));
2352 global.max_perf_pct = 100;
2354 intel_pstate_driver = driver;
2355 ret = cpufreq_register_driver(intel_pstate_driver);
2357 intel_pstate_driver_cleanup();
2361 global.min_perf_pct = min_perf_pct_min();
2366 static int intel_pstate_unregister_driver(void)
2371 cpufreq_unregister_driver(intel_pstate_driver);
2372 intel_pstate_driver_cleanup();
2377 static ssize_t intel_pstate_show_status(char *buf)
2379 if (!intel_pstate_driver)
2380 return sprintf(buf, "off\n");
2382 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2383 "active" : "passive");
2386 static int intel_pstate_update_status(const char *buf, size_t size)
2390 if (size == 3 && !strncmp(buf, "off", size))
2391 return intel_pstate_driver ?
2392 intel_pstate_unregister_driver() : -EINVAL;
2394 if (size == 6 && !strncmp(buf, "active", size)) {
2395 if (intel_pstate_driver) {
2396 if (intel_pstate_driver == &intel_pstate)
2399 ret = intel_pstate_unregister_driver();
2404 return intel_pstate_register_driver(&intel_pstate);
2407 if (size == 7 && !strncmp(buf, "passive", size)) {
2408 if (intel_pstate_driver) {
2409 if (intel_pstate_driver == &intel_cpufreq)
2412 ret = intel_pstate_unregister_driver();
2417 return intel_pstate_register_driver(&intel_cpufreq);
2423 static int no_load __initdata;
2424 static int no_hwp __initdata;
2425 static int hwp_only __initdata;
2426 static unsigned int force_load __initdata;
2428 static int __init intel_pstate_msrs_not_valid(void)
2430 if (!pstate_funcs.get_max() ||
2431 !pstate_funcs.get_min() ||
2432 !pstate_funcs.get_turbo())
2438 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2440 pstate_funcs.get_max = funcs->get_max;
2441 pstate_funcs.get_max_physical = funcs->get_max_physical;
2442 pstate_funcs.get_min = funcs->get_min;
2443 pstate_funcs.get_turbo = funcs->get_turbo;
2444 pstate_funcs.get_scaling = funcs->get_scaling;
2445 pstate_funcs.get_val = funcs->get_val;
2446 pstate_funcs.get_vid = funcs->get_vid;
2447 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2452 static bool __init intel_pstate_no_acpi_pss(void)
2456 for_each_possible_cpu(i) {
2458 union acpi_object *pss;
2459 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2460 struct acpi_processor *pr = per_cpu(processors, i);
2465 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2466 if (ACPI_FAILURE(status))
2469 pss = buffer.pointer;
2470 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2481 static bool __init intel_pstate_no_acpi_pcch(void)
2486 status = acpi_get_handle(NULL, "\\_SB", &handle);
2487 if (ACPI_FAILURE(status))
2490 return !acpi_has_method(handle, "PCCH");
2493 static bool __init intel_pstate_has_acpi_ppc(void)
2497 for_each_possible_cpu(i) {
2498 struct acpi_processor *pr = per_cpu(processors, i);
2502 if (acpi_has_method(pr->handle, "_PPC"))
2513 /* Hardware vendor-specific info that has its own power management modes */
2514 static struct acpi_platform_list plat_info[] __initdata = {
2515 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2516 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2517 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2518 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2519 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2520 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2521 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2522 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2523 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2524 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2525 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2526 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2527 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2528 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2529 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2533 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2535 const struct x86_cpu_id *id;
2539 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2541 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2542 if ( misc_pwr & (1 << 8))
2546 idx = acpi_match_platform_list(plat_info);
2550 switch (plat_info[idx].data) {
2552 if (!intel_pstate_no_acpi_pss())
2555 return intel_pstate_no_acpi_pcch();
2557 return intel_pstate_has_acpi_ppc() && !force_load;
2563 static void intel_pstate_request_control_from_smm(void)
2566 * It may be unsafe to request P-states control from SMM if _PPC support
2567 * has not been enabled.
2570 acpi_processor_pstate_control();
2572 #else /* CONFIG_ACPI not enabled */
2573 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2574 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2575 static inline void intel_pstate_request_control_from_smm(void) {}
2576 #endif /* CONFIG_ACPI */
2578 #define INTEL_PSTATE_HWP_BROADWELL 0x01
2580 #define ICPU_HWP(model, hwp_mode) \
2581 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2583 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2584 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2585 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2586 ICPU_HWP(X86_MODEL_ANY, 0),
2590 static int __init intel_pstate_init(void)
2592 const struct x86_cpu_id *id;
2598 id = x86_match_cpu(hwp_support_ids);
2600 copy_cpu_funcs(&core_funcs);
2603 hwp_mode_bdw = id->driver_data;
2604 intel_pstate.attr = hwp_cpufreq_attrs;
2605 goto hwp_cpu_matched;
2608 id = x86_match_cpu(intel_pstate_cpu_ids);
2612 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2615 if (intel_pstate_msrs_not_valid())
2620 * The Intel pstate driver will be ignored if the platform
2621 * firmware has its own power management modes.
2623 if (intel_pstate_platform_pwr_mgmt_exists())
2626 if (!hwp_active && hwp_only)
2629 pr_info("Intel P-state driver initializing\n");
2631 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2635 intel_pstate_request_control_from_smm();
2637 intel_pstate_sysfs_expose_params();
2639 mutex_lock(&intel_pstate_driver_lock);
2640 rc = intel_pstate_register_driver(default_driver);
2641 mutex_unlock(&intel_pstate_driver_lock);
2646 pr_info("HWP enabled\n");
2650 device_initcall(intel_pstate_init);
2652 static int __init intel_pstate_setup(char *str)
2657 if (!strcmp(str, "disable")) {
2659 } else if (!strcmp(str, "passive")) {
2660 pr_info("Passive mode enabled\n");
2661 default_driver = &intel_cpufreq;
2664 if (!strcmp(str, "no_hwp")) {
2665 pr_info("HWP disabled\n");
2668 if (!strcmp(str, "force"))
2670 if (!strcmp(str, "hwp_only"))
2672 if (!strcmp(str, "per_cpu_perf_limits"))
2673 per_cpu_limits = true;
2676 if (!strcmp(str, "support_acpi_ppc"))
2682 early_param("intel_pstate", intel_pstate_setup);
2684 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2685 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2686 MODULE_LICENSE("GPL");