drivers/cpufreq/tegra20-cpufreq.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@google.com>
   6  *      Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/cpufreq.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25
  26 static struct cpufreq_frequency_table freq_table[] = {
  27         { .frequency = 216000 },
  28         { .frequency = 312000 },
  29         { .frequency = 456000 },
  30         { .frequency = 608000 },
  31         { .frequency = 760000 },
  32         { .frequency = 816000 },
  33         { .frequency = 912000 },
  34         { .frequency = 1000000 },
  35         { .frequency = CPUFREQ_TABLE_END },
  36 };
  37
  38 #define NUM_CPUS        2
  39
  40 static struct clk *cpu_clk;
  41 static struct clk *pll_x_clk;
  42 static struct clk *pll_p_clk;
  43 static struct clk *emc_clk;
  44 static bool pll_x_prepared;
  45
  46 static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
  47                                            unsigned int index)
  48 {
  49         unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
  50
  51         /*
  52          * Don't switch to intermediate freq if:
  53          * - we are already at it, i.e. policy->cur == ifreq
  54          * - index corresponds to ifreq
  55          */
  56         if ((freq_table[index].frequency == ifreq) || (policy->cur == ifreq))
  57                 return 0;
  58
  59         return ifreq;
  60 }
  61
  62 static int tegra_target_intermediate(struct cpufreq_policy *policy,
  63                                      unsigned int index)
  64 {
  65         int ret;
  66
  67         /*
  68          * Take an extra reference to the main pll so it doesn't turn
  69          * off when we move the cpu off of it as enabling it again while we
  70          * switch to it from tegra_target() would take additional time.
  71          *
  72          * When target-freq is equal to intermediate freq we don't need to
  73          * switch to an intermediate freq and so this routine isn't called.
  74          * Also, we wouldn't be using pll_x anymore and must not take extra
  75          * reference to it, as it can be disabled now to save some power.
  76          */
  77         clk_prepare_enable(pll_x_clk);
  78
  79         ret = clk_set_parent(cpu_clk, pll_p_clk);
  80         if (ret)
  81                 clk_disable_unprepare(pll_x_clk);
  82         else
  83                 pll_x_prepared = true;
  84
  85         return ret;
  86 }
  87
  88 static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
  89 {
  90         unsigned long rate = freq_table[index].frequency;
  91         unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
  92         int ret = 0;
  93
  94         /*
  95          * Vote on memory bus frequency based on cpu frequency
  96          * This sets the minimum frequency, display or avp may request higher
  97          */
  98         if (rate >= 816000)
  99                 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
 100         else if (rate >= 456000)
 101                 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
 102         else
 103                 clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */
 104
 105         /*
 106          * target freq == pll_p, don't need to take extra reference to pll_x_clk
 107          * as it isn't used anymore.
 108          */
 109         if (rate == ifreq)
 110                 return clk_set_parent(cpu_clk, pll_p_clk);
 111
 112         ret = clk_set_rate(pll_x_clk, rate * 1000);
 113         /* Restore to earlier frequency on error, i.e. pll_x */
 114         if (ret)
 115                 pr_err("Failed to change pll_x to %lu\n", rate);
 116
 117         ret = clk_set_parent(cpu_clk, pll_x_clk);
 118         /* This shouldn't fail while changing or restoring */
 119         WARN_ON(ret);
 120
 121         /*
 122          * Drop count to pll_x clock only if we switched to intermediate freq
 123          * earlier while transitioning to a target frequency.
 124          */
 125         if (pll_x_prepared) {
 126                 clk_disable_unprepare(pll_x_clk);
 127                 pll_x_prepared = false;
 128         }
 129
 130         return ret;
 131 }
 132
 133 static int tegra_cpu_init(struct cpufreq_policy *policy)
 134 {
 135         int ret;
 136
 137         if (policy->cpu >= NUM_CPUS)
 138                 return -EINVAL;
 139
 140         clk_prepare_enable(emc_clk);
 141         clk_prepare_enable(cpu_clk);
 142
 143         /* FIXME: what's the actual transition time? */
 144         ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
 145         if (ret) {
 146                 clk_disable_unprepare(cpu_clk);
 147                 clk_disable_unprepare(emc_clk);
 148                 return ret;
 149         }
 150
 151         policy->clk = cpu_clk;
 152         policy->suspend_freq = freq_table[0].frequency;
 153         return 0;
 154 }
 155
 156 static int tegra_cpu_exit(struct cpufreq_policy *policy)
 157 {
 158         clk_disable_unprepare(cpu_clk);
 159         clk_disable_unprepare(emc_clk);
 160         return 0;
 161 }
 162
 163 static struct cpufreq_driver tegra_cpufreq_driver = {
 164         .flags                  = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 165         .verify                 = cpufreq_generic_frequency_table_verify,
 166         .get_intermediate       = tegra_get_intermediate,
 167         .target_intermediate    = tegra_target_intermediate,
 168         .target_index           = tegra_target,
 169         .get                    = cpufreq_generic_get,
 170         .init                   = tegra_cpu_init,
 171         .exit                   = tegra_cpu_exit,
 172         .name                   = "tegra",
 173         .attr                   = cpufreq_generic_attr,
 174         .suspend                = cpufreq_generic_suspend,
 175 };
 176
 177 static int __init tegra_cpufreq_init(void)
 178 {
 179         cpu_clk = clk_get_sys(NULL, "cclk");
 180         if (IS_ERR(cpu_clk))
 181                 return PTR_ERR(cpu_clk);
 182
 183         pll_x_clk = clk_get_sys(NULL, "pll_x");
 184         if (IS_ERR(pll_x_clk))
 185                 return PTR_ERR(pll_x_clk);
 186
 187         pll_p_clk = clk_get_sys(NULL, "pll_p");
 188         if (IS_ERR(pll_p_clk))
 189                 return PTR_ERR(pll_p_clk);
 190
 191         emc_clk = clk_get_sys("cpu", "emc");
 192         if (IS_ERR(emc_clk)) {
 193                 clk_put(cpu_clk);
 194                 return PTR_ERR(emc_clk);
 195         }
 196
 197         return cpufreq_register_driver(&tegra_cpufreq_driver);
 198 }
 199
 200 static void __exit tegra_cpufreq_exit(void)
 201 {
 202         cpufreq_unregister_driver(&tegra_cpufreq_driver);
 203         clk_put(emc_clk);
 204         clk_put(cpu_clk);
 205 }
 206
 207 MODULE_AUTHOR("Colin Cross <ccross@android.com>");
 208 MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
 209 MODULE_LICENSE("GPL");
 210 module_init(tegra_cpufreq_init);
 211 module_exit(tegra_cpufreq_exit);