drivers/crypto/caam/ctrl.c

   1 /* * CAAM control-plane driver backend
   2  * Controller-level driver, kernel property detection, initialization
   3  *
   4  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/of_address.h>
   9 #include <linux/of_irq.h>
  10 #include <linux/sys_soc.h>
  11
  12 #include "compat.h"
  13 #include "regs.h"
  14 #include "intern.h"
  15 #include "jr.h"
  16 #include "desc_constr.h"
  17 #include "ctrl.h"
  18
  19 bool caam_little_end;
  20 EXPORT_SYMBOL(caam_little_end);
  21 bool caam_dpaa2;
  22 EXPORT_SYMBOL(caam_dpaa2);
  23 bool caam_imx;
  24 EXPORT_SYMBOL(caam_imx);
  25
  26 #ifdef CONFIG_CAAM_QI
  27 #include "qi.h"
  28 #endif
  29
  30 /*
  31  * i.MX targets tend to have clock control subsystems that can
  32  * enable/disable clocking to our device.
  33  */
  34 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  35                                                 char *clk_name)
  36 {
  37         return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
  38 }
  39
  40 /*
  41  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  42  * load the JDKEK, TDKEK and TDSK registers
  43  */
  44 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  45 {
  46         u32 *jump_cmd, op_flags;
  47
  48         init_job_desc(desc, 0);
  49
  50         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  51                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  52
  53         /* INIT RNG in non-test mode */
  54         append_operation(desc, op_flags);
  55
  56         if (!handle && do_sk) {
  57                 /*
  58                  * For SH0, Secure Keys must be generated as well
  59                  */
  60
  61                 /* wait for done */
  62                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  63                 set_jump_tgt_here(desc, jump_cmd);
  64
  65                 /*
  66                  * load 1 to clear written reg:
  67                  * resets the done interrrupt and returns the RNG to idle.
  68                  */
  69                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  70
  71                 /* Initialize State Handle  */
  72                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  73                                  OP_ALG_AAI_RNG4_SK);
  74         }
  75
  76         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  77 }
  78
  79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  80 static void build_deinstantiation_desc(u32 *desc, int handle)
  81 {
  82         init_job_desc(desc, 0);
  83
  84         /* Uninstantiate State Handle 0 */
  85         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  86                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  87
  88         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  89 }
  90
  91 /*
  92  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  93  *                        the software (no JR/QI used).
  94  * @ctrldev - pointer to device
  95  * @status - descriptor status, after being run
  96  *
  97  * Return: - 0 if no error occurred
  98  *         - -ENODEV if the DECO couldn't be acquired
  99  *         - -EAGAIN if an error occurred while executing the descriptor
 100  */
 101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 102                                         u32 *status)
 103 {
 104         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 105         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 106         struct caam_deco __iomem *deco = ctrlpriv->deco;
 107         unsigned int timeout = 100000;
 108         u32 deco_dbg_reg, flags;
 109         int i;
 110
 111
 112         if (ctrlpriv->virt_en == 1) {
 113                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 114
 115                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 116                        --timeout)
 117                         cpu_relax();
 118
 119                 timeout = 100000;
 120         }
 121
 122         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 123
 124         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 125                                                                  --timeout)
 126                 cpu_relax();
 127
 128         if (!timeout) {
 129                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 130                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 131                 return -ENODEV;
 132         }
 133
 134         for (i = 0; i < desc_len(desc); i++)
 135                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 136
 137         flags = DECO_JQCR_WHL;
 138         /*
 139          * If the descriptor length is longer than 4 words, then the
 140          * FOUR bit in JRCTRL register must be set.
 141          */
 142         if (desc_len(desc) >= 4)
 143                 flags |= DECO_JQCR_FOUR;
 144
 145         /* Instruct the DECO to execute it */
 146         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 147
 148         timeout = 10000000;
 149         do {
 150                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 151                 /*
 152                  * If an error occured in the descriptor, then
 153                  * the DECO status field will be set to 0x0D
 154                  */
 155                 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
 156                     DESC_DBG_DECO_STAT_HOST_ERR)
 157                         break;
 158                 cpu_relax();
 159         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 160
 161         *status = rd_reg32(&deco->op_status_hi) &
 162                   DECO_OP_STATUS_HI_ERR_MASK;
 163
 164         if (ctrlpriv->virt_en == 1)
 165                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 166
 167         /* Mark the DECO as free */
 168         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 169
 170         if (!timeout)
 171                 return -EAGAIN;
 172
 173         return 0;
 174 }
 175
 176 /*
 177  * instantiate_rng - builds and executes a descriptor on DECO0,
 178  *                   which initializes the RNG block.
 179  * @ctrldev - pointer to device
 180  * @state_handle_mask - bitmask containing the instantiation status
 181  *                      for the RNG4 state handles which exist in
 182  *                      the RNG4 block: 1 if it's been instantiated
 183  *                      by an external entry, 0 otherwise.
 184  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 185  *            Caution: this can be done only once; if the keys need to be
 186  *            regenerated, a POR is required
 187  *
 188  * Return: - 0 if no error occurred
 189  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 190  *         - -ENODEV if DECO0 couldn't be acquired
 191  *         - -EAGAIN if an error occurred when executing the descriptor
 192  *            f.i. there was a RNG hardware error due to not "good enough"
 193  *            entropy being aquired.
 194  */
 195 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 196                            int gen_sk)
 197 {
 198         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 199         struct caam_ctrl __iomem *ctrl;
 200         u32 *desc, status = 0, rdsta_val;
 201         int ret = 0, sh_idx;
 202
 203         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 204         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 205         if (!desc)
 206                 return -ENOMEM;
 207
 208         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 209                 /*
 210                  * If the corresponding bit is set, this state handle
 211                  * was initialized by somebody else, so it's left alone.
 212                  */
 213                 if ((1 << sh_idx) & state_handle_mask)
 214                         continue;
 215
 216                 /* Create the descriptor for instantiating RNG State Handle */
 217                 build_instantiation_desc(desc, sh_idx, gen_sk);
 218
 219                 /* Try to run it through DECO0 */
 220                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 221
 222                 /*
 223                  * If ret is not 0, or descriptor status is not 0, then
 224                  * something went wrong. No need to try the next state
 225                  * handle (if available), bail out here.
 226                  * Also, if for some reason, the State Handle didn't get
 227                  * instantiated although the descriptor has finished
 228                  * without any error (HW optimizations for later
 229                  * CAAM eras), then try again.
 230                  */
 231                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 232                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 233                     !(rdsta_val & (1 << sh_idx)))
 234                         ret = -EAGAIN;
 235                 if (ret)
 236                         break;
 237                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 238                 /* Clear the contents before recreating the descriptor */
 239                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 240         }
 241
 242         kfree(desc);
 243
 244         return ret;
 245 }
 246
 247 /*
 248  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 249  *                     which deinitializes the RNG block.
 250  * @ctrldev - pointer to device
 251  * @state_handle_mask - bitmask containing the instantiation status
 252  *                      for the RNG4 state handles which exist in
 253  *                      the RNG4 block: 1 if it's been instantiated
 254  *
 255  * Return: - 0 if no error occurred
 256  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 257  *         - -ENODEV if DECO0 couldn't be acquired
 258  *         - -EAGAIN if an error occurred when executing the descriptor
 259  */
 260 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 261 {
 262         u32 *desc, status;
 263         int sh_idx, ret = 0;
 264
 265         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 266         if (!desc)
 267                 return -ENOMEM;
 268
 269         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 270                 /*
 271                  * If the corresponding bit is set, then it means the state
 272                  * handle was initialized by us, and thus it needs to be
 273                  * deinitialized as well
 274                  */
 275                 if ((1 << sh_idx) & state_handle_mask) {
 276                         /*
 277                          * Create the descriptor for deinstantating this state
 278                          * handle
 279                          */
 280                         build_deinstantiation_desc(desc, sh_idx);
 281
 282                         /* Try to run it through DECO0 */
 283                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 284
 285                         if (ret ||
 286                             (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
 287                                 dev_err(ctrldev,
 288                                         "Failed to deinstantiate RNG4 SH%d\n",
 289                                         sh_idx);
 290                                 break;
 291                         }
 292                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 293                 }
 294         }
 295
 296         kfree(desc);
 297
 298         return ret;
 299 }
 300
 301 static int caam_remove(struct platform_device *pdev)
 302 {
 303         struct device *ctrldev;
 304         struct caam_drv_private *ctrlpriv;
 305         struct caam_ctrl __iomem *ctrl;
 306
 307         ctrldev = &pdev->dev;
 308         ctrlpriv = dev_get_drvdata(ctrldev);
 309         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 310
 311         /* Remove platform devices under the crypto node */
 312         of_platform_depopulate(ctrldev);
 313
 314 #ifdef CONFIG_CAAM_QI
 315         if (ctrlpriv->qidev)
 316                 caam_qi_shutdown(ctrlpriv->qidev);
 317 #endif
 318
 319         /*
 320          * De-initialize RNG state handles initialized by this driver.
 321          * In case of DPAA 2.x, RNG is managed by MC firmware.
 322          */
 323         if (!caam_dpaa2 && ctrlpriv->rng4_sh_init)
 324                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 325
 326         /* Shut down debug views */
 327 #ifdef CONFIG_DEBUG_FS
 328         debugfs_remove_recursive(ctrlpriv->dfs_root);
 329 #endif
 330
 331         /* Unmap controller region */
 332         iounmap(ctrl);
 333
 334         /* shut clocks off before finalizing shutdown */
 335         clk_disable_unprepare(ctrlpriv->caam_ipg);
 336         clk_disable_unprepare(ctrlpriv->caam_mem);
 337         clk_disable_unprepare(ctrlpriv->caam_aclk);
 338         if (ctrlpriv->caam_emi_slow)
 339                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 340         return 0;
 341 }
 342
 343 /*
 344  * kick_trng - sets the various parameters for enabling the initialization
 345  *             of the RNG4 block in CAAM
 346  * @pdev - pointer to the platform device
 347  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 348  */
 349 static void kick_trng(struct platform_device *pdev, int ent_delay)
 350 {
 351         struct device *ctrldev = &pdev->dev;
 352         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 353         struct caam_ctrl __iomem *ctrl;
 354         struct rng4tst __iomem *r4tst;
 355         u32 val;
 356
 357         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 358         r4tst = &ctrl->r4tst[0];
 359
 360         /* put RNG4 into program mode */
 361         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 362
 363         /*
 364          * Performance-wise, it does not make sense to
 365          * set the delay to a value that is lower
 366          * than the last one that worked (i.e. the state handles
 367          * were instantiated properly. Thus, instead of wasting
 368          * time trying to set the values controlling the sample
 369          * frequency, the function simply returns.
 370          */
 371         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 372               >> RTSDCTL_ENT_DLY_SHIFT;
 373         if (ent_delay <= val)
 374                 goto start_rng;
 375
 376         val = rd_reg32(&r4tst->rtsdctl);
 377         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 378               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 379         wr_reg32(&r4tst->rtsdctl, val);
 380         /* min. freq. count, equal to 1/4 of the entropy sample length */
 381         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 382         /* disable maximum frequency count */
 383         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 384         /* read the control register */
 385         val = rd_reg32(&r4tst->rtmctl);
 386 start_rng:
 387         /*
 388          * select raw sampling in both entropy shifter
 389          * and statistical checker; ; put RNG4 into run mode
 390          */
 391         clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 392 }
 393
 394 /**
 395  * caam_get_era() - Return the ERA of the SEC on SoC, based
 396  * on "sec-era" propery in the DTS. This property is updated by u-boot.
 397  **/
 398 int caam_get_era(void)
 399 {
 400         struct device_node *caam_node;
 401         int ret;
 402         u32 prop;
 403
 404         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 405         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 406         of_node_put(caam_node);
 407
 408         return ret ? -ENOTSUPP : prop;
 409 }
 410 EXPORT_SYMBOL(caam_get_era);
 411
 412 static const struct of_device_id caam_match[] = {
 413         {
 414                 .compatible = "fsl,sec-v4.0",
 415         },
 416         {
 417                 .compatible = "fsl,sec4.0",
 418         },
 419         {},
 420 };
 421 MODULE_DEVICE_TABLE(of, caam_match);
 422
 423 /* Probe routine for CAAM top (controller) level */
 424 static int caam_probe(struct platform_device *pdev)
 425 {
 426         int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 427         u64 caam_id;
 428         static const struct soc_device_attribute imx_soc[] = {
 429                 {.family = "Freescale i.MX"},
 430                 {},
 431         };
 432         struct device *dev;
 433         struct device_node *nprop, *np;
 434         struct caam_ctrl __iomem *ctrl;
 435         struct caam_drv_private *ctrlpriv;
 436         struct clk *clk;
 437 #ifdef CONFIG_DEBUG_FS
 438         struct caam_perfmon *perfmon;
 439 #endif
 440         u32 scfgr, comp_params;
 441         u32 cha_vid_ls;
 442         int pg_size;
 443         int BLOCK_OFFSET = 0;
 444
 445         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 446         if (!ctrlpriv)
 447                 return -ENOMEM;
 448
 449         dev = &pdev->dev;
 450         dev_set_drvdata(dev, ctrlpriv);
 451         nprop = pdev->dev.of_node;
 452
 453         caam_imx = (bool)soc_device_match(imx_soc);
 454
 455         /* Enable clocking */
 456         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 457         if (IS_ERR(clk)) {
 458                 ret = PTR_ERR(clk);
 459                 dev_err(&pdev->dev,
 460                         "can't identify CAAM ipg clk: %d\n", ret);
 461                 return ret;
 462         }
 463         ctrlpriv->caam_ipg = clk;
 464
 465         clk = caam_drv_identify_clk(&pdev->dev, "mem");
 466         if (IS_ERR(clk)) {
 467                 ret = PTR_ERR(clk);
 468                 dev_err(&pdev->dev,
 469                         "can't identify CAAM mem clk: %d\n", ret);
 470                 return ret;
 471         }
 472         ctrlpriv->caam_mem = clk;
 473
 474         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
 475         if (IS_ERR(clk)) {
 476                 ret = PTR_ERR(clk);
 477                 dev_err(&pdev->dev,
 478                         "can't identify CAAM aclk clk: %d\n", ret);
 479                 return ret;
 480         }
 481         ctrlpriv->caam_aclk = clk;
 482
 483         if (!of_machine_is_compatible("fsl,imx6ul")) {
 484                 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
 485                 if (IS_ERR(clk)) {
 486                         ret = PTR_ERR(clk);
 487                         dev_err(&pdev->dev,
 488                                 "can't identify CAAM emi_slow clk: %d\n", ret);
 489                         return ret;
 490                 }
 491                 ctrlpriv->caam_emi_slow = clk;
 492         }
 493
 494         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
 495         if (ret < 0) {
 496                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
 497                 return ret;
 498         }
 499
 500         ret = clk_prepare_enable(ctrlpriv->caam_mem);
 501         if (ret < 0) {
 502                 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
 503                         ret);
 504                 goto disable_caam_ipg;
 505         }
 506
 507         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
 508         if (ret < 0) {
 509                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
 510                 goto disable_caam_mem;
 511         }
 512
 513         if (ctrlpriv->caam_emi_slow) {
 514                 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
 515                 if (ret < 0) {
 516                         dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
 517                                 ret);
 518                         goto disable_caam_aclk;
 519                 }
 520         }
 521
 522         /* Get configuration properties from device tree */
 523         /* First, get register page */
 524         ctrl = of_iomap(nprop, 0);
 525         if (ctrl == NULL) {
 526                 dev_err(dev, "caam: of_iomap() failed\n");
 527                 ret = -ENOMEM;
 528                 goto disable_caam_emi_slow;
 529         }
 530
 531         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 532                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 533
 534         /* Finding the page size for using the CTPR_MS register */
 535         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 536         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 537
 538         /* Allocating the BLOCK_OFFSET based on the supported page size on
 539          * the platform
 540          */
 541         if (pg_size == 0)
 542                 BLOCK_OFFSET = PG_SIZE_4K;
 543         else
 544                 BLOCK_OFFSET = PG_SIZE_64K;
 545
 546         ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
 547         ctrlpriv->assure = (struct caam_assurance __iomem __force *)
 548                            ((__force uint8_t *)ctrl +
 549                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 550                            );
 551         ctrlpriv->deco = (struct caam_deco __iomem __force *)
 552                          ((__force uint8_t *)ctrl +
 553                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 554                          );
 555
 556         /* Get the IRQ of the controller (for security violations only) */
 557         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 558
 559         /*
 560          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 561          * long pointers in master configuration register.
 562          * In case of DPAA 2.x, Management Complex firmware performs
 563          * the configuration.
 564          */
 565         caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
 566         if (!caam_dpaa2)
 567                 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
 568                               MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 569                               MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 570                               (sizeof(dma_addr_t) == sizeof(u64) ?
 571                                MCFGR_LONG_PTR : 0));
 572
 573         /*
 574          *  Read the Compile Time paramters and SCFGR to determine
 575          * if Virtualization is enabled for this platform
 576          */
 577         scfgr = rd_reg32(&ctrl->scfgr);
 578
 579         ctrlpriv->virt_en = 0;
 580         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 581                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 582                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 583                  */
 584                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 585                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 586                        (scfgr & SCFGR_VIRT_EN)))
 587                                 ctrlpriv->virt_en = 1;
 588         } else {
 589                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 590                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 591                                 ctrlpriv->virt_en = 1;
 592         }
 593
 594         if (ctrlpriv->virt_en == 1)
 595                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 596                               JRSTART_JR1_START | JRSTART_JR2_START |
 597                               JRSTART_JR3_START);
 598
 599         if (sizeof(dma_addr_t) == sizeof(u64)) {
 600                 if (caam_dpaa2)
 601                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
 602                 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 603                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 604                 else
 605                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 606         } else {
 607                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 608         }
 609         if (ret) {
 610                 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
 611                 goto iounmap_ctrl;
 612         }
 613
 614         ctrlpriv->era = caam_get_era();
 615
 616         ret = of_platform_populate(nprop, caam_match, NULL, dev);
 617         if (ret) {
 618                 dev_err(dev, "JR platform devices creation error\n");
 619                 goto iounmap_ctrl;
 620         }
 621
 622 #ifdef CONFIG_DEBUG_FS
 623         /*
 624          * FIXME: needs better naming distinction, as some amalgamation of
 625          * "caam" and nprop->full_name. The OF name isn't distinctive,
 626          * but does separate instances
 627          */
 628         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 629
 630         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 631         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 632 #endif
 633
 634         ring = 0;
 635         for_each_available_child_of_node(nprop, np)
 636                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 637                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 638                         ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 639                                              ((__force uint8_t *)ctrl +
 640                                              (ring + JR_BLOCK_NUMBER) *
 641                                               BLOCK_OFFSET
 642                                              );
 643                         ctrlpriv->total_jobrs++;
 644                         ring++;
 645                 }
 646
 647         /* Check to see if (DPAA 1.x) QI present. If so, enable */
 648         ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 649         if (ctrlpriv->qi_present && !caam_dpaa2) {
 650                 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
 651                                ((__force uint8_t *)ctrl +
 652                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 653                                );
 654                 /* This is all that's required to physically enable QI */
 655                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 656
 657                 /* If QMAN driver is present, init CAAM-QI backend */
 658 #ifdef CONFIG_CAAM_QI
 659                 ret = caam_qi_init(pdev);
 660                 if (ret)
 661                         dev_err(dev, "caam qi i/f init failed: %d\n", ret);
 662 #endif
 663         }
 664
 665         /* If no QI and no rings specified, quit and go home */
 666         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 667                 dev_err(dev, "no queues configured, terminating\n");
 668                 ret = -ENOMEM;
 669                 goto caam_remove;
 670         }
 671
 672         cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 673
 674         /*
 675          * If SEC has RNG version >= 4 and RNG state handle has not been
 676          * already instantiated, do RNG instantiation
 677          * In case of DPAA 2.x, RNG is managed by MC firmware.
 678          */
 679         if (!caam_dpaa2 &&
 680             (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 681                 ctrlpriv->rng4_sh_init =
 682                         rd_reg32(&ctrl->r4tst[0].rdsta);
 683                 /*
 684                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 685                  * generated, signal this to the function that is instantiating
 686                  * the state handles. An error would occur if RNG4 attempts
 687                  * to regenerate these keys before the next POR.
 688                  */
 689                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 690                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 691                 do {
 692                         int inst_handles =
 693                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 694                                                                 RDSTA_IFMASK;
 695                         /*
 696                          * If either SH were instantiated by somebody else
 697                          * (e.g. u-boot) then it is assumed that the entropy
 698                          * parameters are properly set and thus the function
 699                          * setting these (kick_trng(...)) is skipped.
 700                          * Also, if a handle was instantiated, do not change
 701                          * the TRNG parameters.
 702                          */
 703                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 704                                 dev_info(dev,
 705                                          "Entropy delay = %u\n",
 706                                          ent_delay);
 707                                 kick_trng(pdev, ent_delay);
 708                                 ent_delay += 400;
 709                         }
 710                         /*
 711                          * if instantiate_rng(...) fails, the loop will rerun
 712                          * and the kick_trng(...) function will modfiy the
 713                          * upper and lower limits of the entropy sampling
 714                          * interval, leading to a sucessful initialization of
 715                          * the RNG.
 716                          */
 717                         ret = instantiate_rng(dev, inst_handles,
 718                                               gen_sk);
 719                         if (ret == -EAGAIN)
 720                                 /*
 721                                  * if here, the loop will rerun,
 722                                  * so don't hog the CPU
 723                                  */
 724                                 cpu_relax();
 725                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 726                 if (ret) {
 727                         dev_err(dev, "failed to instantiate RNG");
 728                         goto caam_remove;
 729                 }
 730                 /*
 731                  * Set handles init'ed by this module as the complement of the
 732                  * already initialized ones
 733                  */
 734                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 735
 736                 /* Enable RDB bit so that RNG works faster */
 737                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 738         }
 739
 740         /* NOTE: RTIC detection ought to go here, around Si time */
 741
 742         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 743                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 744
 745         /* Report "alive" for developer to see */
 746         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 747                  ctrlpriv->era);
 748         dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",
 749                  ctrlpriv->total_jobrs, ctrlpriv->qi_present,
 750                  caam_dpaa2 ? "yes" : "no");
 751
 752 #ifdef CONFIG_DEBUG_FS
 753         debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
 754                             ctrlpriv->ctl, &perfmon->req_dequeued,
 755                             &caam_fops_u64_ro);
 756         debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 757                             ctrlpriv->ctl, &perfmon->ob_enc_req,
 758                             &caam_fops_u64_ro);
 759         debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 760                             ctrlpriv->ctl, &perfmon->ib_dec_req,
 761                             &caam_fops_u64_ro);
 762         debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 763                             ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 764                             &caam_fops_u64_ro);
 765         debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
 766                             ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 767                             &caam_fops_u64_ro);
 768         debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 769                             ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 770                             &caam_fops_u64_ro);
 771         debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
 772                             ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 773                             &caam_fops_u64_ro);
 774
 775         /* Controller level - global status values */
 776         debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
 777                             ctrlpriv->ctl, &perfmon->faultaddr,
 778                             &caam_fops_u32_ro);
 779         debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
 780                             ctrlpriv->ctl, &perfmon->faultdetail,
 781                             &caam_fops_u32_ro);
 782         debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
 783                             ctrlpriv->ctl, &perfmon->status,
 784                             &caam_fops_u32_ro);
 785
 786         /* Internal covering keys (useful in non-secure mode only) */
 787         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 788         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 789         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
 790                                                 S_IRUSR |
 791                                                 S_IRGRP | S_IROTH,
 792                                                 ctrlpriv->ctl,
 793                                                 &ctrlpriv->ctl_kek_wrap);
 794
 795         ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
 796         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 797         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
 798                                                  S_IRUSR |
 799                                                  S_IRGRP | S_IROTH,
 800                                                  ctrlpriv->ctl,
 801                                                  &ctrlpriv->ctl_tkek_wrap);
 802
 803         ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
 804         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 805         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
 806                                                  S_IRUSR |
 807                                                  S_IRGRP | S_IROTH,
 808                                                  ctrlpriv->ctl,
 809                                                  &ctrlpriv->ctl_tdsk_wrap);
 810 #endif
 811         return 0;
 812
 813 caam_remove:
 814 #ifdef CONFIG_DEBUG_FS
 815         debugfs_remove_recursive(ctrlpriv->dfs_root);
 816 #endif
 817         caam_remove(pdev);
 818         return ret;
 819
 820 iounmap_ctrl:
 821         iounmap(ctrl);
 822 disable_caam_emi_slow:
 823         if (ctrlpriv->caam_emi_slow)
 824                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 825 disable_caam_aclk:
 826         clk_disable_unprepare(ctrlpriv->caam_aclk);
 827 disable_caam_mem:
 828         clk_disable_unprepare(ctrlpriv->caam_mem);
 829 disable_caam_ipg:
 830         clk_disable_unprepare(ctrlpriv->caam_ipg);
 831         return ret;
 832 }
 833
 834 static struct platform_driver caam_driver = {
 835         .driver = {
 836                 .name = "caam",
 837                 .of_match_table = caam_match,
 838         },
 839         .probe       = caam_probe,
 840         .remove      = caam_remove,
 841 };
 842
 843 module_platform_driver(caam_driver);
 844
 845 MODULE_LICENSE("GPL");
 846 MODULE_DESCRIPTION("FSL CAAM request backend");
 847 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");