1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/scatterlist.h>
18 #include <linux/highmem.h>
19 #include <linux/crypto.h>
20 #include <linux/hw_random.h>
21 #include <linux/ktime.h>
23 #include <crypto/algapi.h>
24 #include <crypto/internal/des.h>
26 static char hifn_pll_ref[sizeof("extNNN")] = "ext";
27 module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
28 MODULE_PARM_DESC(hifn_pll_ref,
29 "PLL reference clock (pci[freq] or ext[freq], default ext)");
31 static atomic_t hifn_dev_number;
33 #define ACRYPTO_OP_DECRYPT 0
34 #define ACRYPTO_OP_ENCRYPT 1
35 #define ACRYPTO_OP_HMAC 2
36 #define ACRYPTO_OP_RNG 3
38 #define ACRYPTO_MODE_ECB 0
39 #define ACRYPTO_MODE_CBC 1
40 #define ACRYPTO_MODE_CFB 2
41 #define ACRYPTO_MODE_OFB 3
43 #define ACRYPTO_TYPE_AES_128 0
44 #define ACRYPTO_TYPE_AES_192 1
45 #define ACRYPTO_TYPE_AES_256 2
46 #define ACRYPTO_TYPE_3DES 3
47 #define ACRYPTO_TYPE_DES 4
49 #define PCI_VENDOR_ID_HIFN 0x13A3
50 #define PCI_DEVICE_ID_HIFN_7955 0x0020
51 #define PCI_DEVICE_ID_HIFN_7956 0x001d
53 /* I/O region sizes */
55 #define HIFN_BAR0_SIZE 0x1000
56 #define HIFN_BAR1_SIZE 0x2000
57 #define HIFN_BAR2_SIZE 0x8000
61 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
62 #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
63 #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
64 #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
65 #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
66 #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
67 #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
68 #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
69 #define HIFN_CHIP_ID 0x98 /* Chip ID */
72 * Processing Unit Registers (offset from BASEREG0)
74 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
75 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
76 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
77 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
78 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
79 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
80 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
81 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
82 #define HIFN_0_SPACESIZE 0x20 /* Register space size */
84 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
85 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
86 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
87 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
88 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
89 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
91 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
92 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
93 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
94 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
95 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
96 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
97 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
98 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
99 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
100 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
101 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
103 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
104 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
105 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
106 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
107 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
108 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
109 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
110 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
111 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
112 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
113 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
114 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
115 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
116 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
117 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
118 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
119 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
120 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
121 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
122 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
123 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
124 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
125 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
126 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
128 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
129 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
130 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
131 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
132 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
133 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
134 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
135 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
136 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
137 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
138 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
140 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
141 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
142 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
143 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
144 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
145 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
146 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
147 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
148 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
149 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
150 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
151 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
152 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
153 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
154 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
155 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
156 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
157 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
159 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
160 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
161 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
163 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
164 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
167 * DMA Interface Registers (offset from BASEREG1)
169 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
170 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
171 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
172 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
173 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
174 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
175 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
176 #define HIFN_1_PLL 0x4c /* 795x: PLL config */
177 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
178 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
179 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
180 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
181 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
182 #define HIFN_1_REVID 0x98 /* Revision ID */
183 #define HIFN_1_UNLOCK_SECRET1 0xf4
184 #define HIFN_1_UNLOCK_SECRET2 0xfc
185 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
186 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
187 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
188 #define HIFN_1_PUB_OP 0x308 /* Public Operand */
189 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
190 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
191 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
192 #define HIFN_1_RNG_DATA 0x318 /* RNG data */
193 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
194 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
196 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
197 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
198 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
199 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
200 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
201 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
202 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
203 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
204 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
205 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
206 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
207 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
208 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
209 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
210 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
211 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
212 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
213 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
214 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
215 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
216 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
217 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
218 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
219 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
220 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
221 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
222 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
223 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
224 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
225 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
226 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
227 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
228 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
229 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
230 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
231 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
232 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
233 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
234 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
236 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
237 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
238 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
239 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
240 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
241 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
242 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
243 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
244 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
245 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
246 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
247 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
248 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
249 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
250 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
251 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
252 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
253 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
254 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
255 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
256 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
257 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
258 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
260 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
261 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
262 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
263 #define HIFN_DMACNFG_UNLOCK 0x00000800
264 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
265 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
266 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
267 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
268 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
270 /* PLL configuration register */
271 #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */
272 #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */
273 #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */
274 #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */
275 #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */
276 #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */
277 #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */
278 #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */
279 #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */
280 #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */
281 #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */
282 #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */
283 #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */
284 #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */
285 #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */
286 #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */
287 #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */
289 #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */
291 /* Public key reset register (HIFN_1_PUB_RESET) */
292 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
294 /* Public base address register (HIFN_1_PUB_BASE) */
295 #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
297 /* Public operand length register (HIFN_1_PUB_OPLEN) */
298 #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
299 #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
300 #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
301 #define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */
302 #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
303 #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
305 /* Public operation register (HIFN_1_PUB_OP) */
306 #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
307 #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
308 #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
309 #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
310 #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
311 #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
312 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
313 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
314 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
315 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
316 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
317 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
318 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
319 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
320 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
321 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
322 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
323 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
324 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
325 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
327 /* Public status register (HIFN_1_PUB_STATUS) */
328 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
329 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
331 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
332 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
334 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
335 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
337 #define HIFN_NAMESIZE 32
338 #define HIFN_MAX_RESULT_ORDER 5
340 #define HIFN_D_CMD_RSIZE (24 * 1)
341 #define HIFN_D_SRC_RSIZE (80 * 1)
342 #define HIFN_D_DST_RSIZE (80 * 1)
343 #define HIFN_D_RES_RSIZE (24 * 1)
345 #define HIFN_D_DST_DALIGN 4
347 #define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)
349 #define AES_MIN_KEY_SIZE 16
350 #define AES_MAX_KEY_SIZE 32
352 #define HIFN_DES_KEY_LENGTH 8
353 #define HIFN_3DES_KEY_LENGTH 24
354 #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
355 #define HIFN_IV_LENGTH 8
356 #define HIFN_AES_IV_LENGTH 16
357 #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
359 #define HIFN_MAC_KEY_LENGTH 64
360 #define HIFN_MD5_LENGTH 16
361 #define HIFN_SHA1_LENGTH 20
362 #define HIFN_MAC_TRUNC_LENGTH 12
364 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
365 #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
366 #define HIFN_USED_RESULT 12
374 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1];
375 struct hifn_desc srcr[HIFN_D_SRC_RSIZE + 1];
376 struct hifn_desc dstr[HIFN_D_DST_RSIZE + 1];
377 struct hifn_desc resr[HIFN_D_RES_RSIZE + 1];
379 u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
380 u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
383 * Our current positions for insertion and removal from the descriptor
386 volatile int cmdi, srci, dsti, resi;
387 volatile int cmdu, srcu, dstu, resu;
388 int cmdk, srck, dstk, resk;
391 #define HIFN_FLAG_CMD_BUSY (1 << 0)
392 #define HIFN_FLAG_SRC_BUSY (1 << 1)
393 #define HIFN_FLAG_DST_BUSY (1 << 2)
394 #define HIFN_FLAG_RES_BUSY (1 << 3)
395 #define HIFN_FLAG_OLD_KEY (1 << 4)
397 #define HIFN_DEFAULT_ACTIVE_NUM 5
400 char name[HIFN_NAMESIZE];
404 struct pci_dev *pdev;
405 void __iomem *bar[3];
412 void *sa[HIFN_D_RES_RSIZE];
418 struct delayed_work work;
420 unsigned long success;
421 unsigned long prev_success;
425 struct tasklet_struct tasklet;
427 struct crypto_queue queue;
428 struct list_head alg_list;
430 unsigned int pk_clk_freq;
432 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
433 unsigned int rng_wait_time;
439 #define HIFN_D_LENGTH 0x0000ffff
440 #define HIFN_D_NOINVALID 0x01000000
441 #define HIFN_D_MASKDONEIRQ 0x02000000
442 #define HIFN_D_DESTOVER 0x04000000
443 #define HIFN_D_OVER 0x08000000
444 #define HIFN_D_LAST 0x20000000
445 #define HIFN_D_JUMP 0x40000000
446 #define HIFN_D_VALID 0x80000000
448 struct hifn_base_command {
449 volatile __le16 masks;
450 volatile __le16 session_num;
451 volatile __le16 total_source_count;
452 volatile __le16 total_dest_count;
455 #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
456 #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
457 #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
458 #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
459 #define HIFN_BASE_CMD_DECODE 0x2000
460 #define HIFN_BASE_CMD_SRCLEN_M 0xc000
461 #define HIFN_BASE_CMD_SRCLEN_S 14
462 #define HIFN_BASE_CMD_DSTLEN_M 0x3000
463 #define HIFN_BASE_CMD_DSTLEN_S 12
464 #define HIFN_BASE_CMD_LENMASK_HI 0x30000
465 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
468 * Structure to help build up the command data structure.
470 struct hifn_crypt_command {
471 volatile __le16 masks;
472 volatile __le16 header_skip;
473 volatile __le16 source_count;
474 volatile __le16 reserved;
477 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
478 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
479 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
480 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
481 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
482 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
483 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
484 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
485 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
486 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
487 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
488 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
489 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
490 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
491 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
492 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
493 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
494 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
495 #define HIFN_CRYPT_CMD_SRCLEN_S 14
498 * Structure to help build up the command data structure.
500 struct hifn_mac_command {
501 volatile __le16 masks;
502 volatile __le16 header_skip;
503 volatile __le16 source_count;
504 volatile __le16 reserved;
507 #define HIFN_MAC_CMD_ALG_MASK 0x0001
508 #define HIFN_MAC_CMD_ALG_SHA1 0x0000
509 #define HIFN_MAC_CMD_ALG_MD5 0x0001
510 #define HIFN_MAC_CMD_MODE_MASK 0x000c
511 #define HIFN_MAC_CMD_MODE_HMAC 0x0000
512 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
513 #define HIFN_MAC_CMD_MODE_HASH 0x0008
514 #define HIFN_MAC_CMD_MODE_FULL 0x0004
515 #define HIFN_MAC_CMD_TRUNC 0x0010
516 #define HIFN_MAC_CMD_RESULT 0x0020
517 #define HIFN_MAC_CMD_APPEND 0x0040
518 #define HIFN_MAC_CMD_SRCLEN_M 0xc000
519 #define HIFN_MAC_CMD_SRCLEN_S 14
522 * MAC POS IPsec initiates authentication after encryption on encodes
523 * and before decryption on decodes.
525 #define HIFN_MAC_CMD_POS_IPSEC 0x0200
526 #define HIFN_MAC_CMD_NEW_KEY 0x0800
528 struct hifn_comp_command {
529 volatile __le16 masks;
530 volatile __le16 header_skip;
531 volatile __le16 source_count;
532 volatile __le16 reserved;
535 #define HIFN_COMP_CMD_SRCLEN_M 0xc000
536 #define HIFN_COMP_CMD_SRCLEN_S 14
537 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
538 #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
539 #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
540 #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
541 #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
542 #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
543 #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
544 #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
546 struct hifn_base_result {
547 volatile __le16 flags;
548 volatile __le16 session;
549 volatile __le16 src_cnt; /* 15:0 of source count */
550 volatile __le16 dst_cnt; /* 15:0 of dest count */
553 #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
554 #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
555 #define HIFN_BASE_RES_SRCLEN_S 14
556 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
557 #define HIFN_BASE_RES_DSTLEN_S 12
559 struct hifn_comp_result {
560 volatile __le16 flags;
564 #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
565 #define HIFN_COMP_RES_LCB_S 8
566 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
567 #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
568 #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
570 struct hifn_mac_result {
571 volatile __le16 flags;
572 volatile __le16 reserved;
573 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
576 #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
577 #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
579 struct hifn_crypt_result {
580 volatile __le16 flags;
581 volatile __le16 reserved;
584 #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
586 #ifndef HIFN_POLL_FREQUENCY
587 #define HIFN_POLL_FREQUENCY 0x1
590 #ifndef HIFN_POLL_SCALAR
591 #define HIFN_POLL_SCALAR 0x0
594 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
595 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
597 struct hifn_crypto_alg {
598 struct list_head entry;
599 struct crypto_alg alg;
600 struct hifn_device *dev;
603 #define ASYNC_SCATTERLIST_CACHE 16
605 #define ASYNC_FLAGS_MISALIGNED (1 << 0)
607 struct hifn_cipher_walk {
608 struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
613 struct hifn_context {
614 u8 key[HIFN_MAX_CRYPT_KEY_LENGTH];
615 struct hifn_device *dev;
616 unsigned int keysize;
619 struct hifn_request_context {
622 u8 op, type, mode, unused;
623 struct hifn_cipher_walk walk;
626 #define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg)
628 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
630 return readl(dev->bar[0] + reg);
633 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
635 return readl(dev->bar[1] + reg);
638 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
640 writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
643 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
645 writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
648 static void hifn_wait_puc(struct hifn_device *dev)
653 for (i = 10000; i > 0; --i) {
654 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
655 if (!(ret & HIFN_PUCTRL_RESET))
662 dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n");
665 static void hifn_reset_puc(struct hifn_device *dev)
667 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
671 static void hifn_stop_device(struct hifn_device *dev)
673 hifn_write_1(dev, HIFN_1_DMA_CSR,
674 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
675 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
676 hifn_write_0(dev, HIFN_0_PUIER, 0);
677 hifn_write_1(dev, HIFN_1_DMA_IER, 0);
680 static void hifn_reset_dma(struct hifn_device *dev, int full)
682 hifn_stop_device(dev);
685 * Setting poll frequency and others to 0.
687 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
688 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
695 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
698 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
699 HIFN_DMACNFG_MSTRESET);
703 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
704 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
709 static u32 hifn_next_signature(u32 a, u_int cnt)
714 for (i = 0; i < cnt; i++) {
723 a = (v & 1) ^ (a << 1);
729 static struct pci2id {
736 PCI_DEVICE_ID_HIFN_7955,
737 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
738 0x00, 0x00, 0x00, 0x00, 0x00 }
742 PCI_DEVICE_ID_HIFN_7956,
743 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
744 0x00, 0x00, 0x00, 0x00, 0x00 }
748 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
749 static int hifn_rng_data_present(struct hwrng *rng, int wait)
751 struct hifn_device *dev = (struct hifn_device *)rng->priv;
754 nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
755 nsec -= dev->rng_wait_time;
764 static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
766 struct hifn_device *dev = (struct hifn_device *)rng->priv;
768 *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
769 dev->rngtime = ktime_get();
773 static int hifn_register_rng(struct hifn_device *dev)
776 * We must wait at least 256 Pk_clk cycles between two reads of the rng.
778 dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC,
779 dev->pk_clk_freq) * 256;
781 dev->rng.name = dev->name;
782 dev->rng.data_present = hifn_rng_data_present,
783 dev->rng.data_read = hifn_rng_data_read,
784 dev->rng.priv = (unsigned long)dev;
786 return hwrng_register(&dev->rng);
789 static void hifn_unregister_rng(struct hifn_device *dev)
791 hwrng_unregister(&dev->rng);
794 #define hifn_register_rng(dev) 0
795 #define hifn_unregister_rng(dev)
798 static int hifn_init_pubrng(struct hifn_device *dev)
802 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
805 for (i = 100; i > 0; --i) {
808 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
813 dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n");
815 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
816 dev->dmareg |= HIFN_DMAIER_PUBDONE;
817 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
819 dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n");
822 /* Enable RNG engine. */
824 hifn_write_1(dev, HIFN_1_RNG_CONFIG,
825 hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
826 dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n");
828 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
829 /* First value must be discarded */
830 hifn_read_1(dev, HIFN_1_RNG_DATA);
831 dev->rngtime = ktime_get();
836 static int hifn_enable_crypto(struct hifn_device *dev)
842 for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
843 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
844 pci2id[i].pci_prod == dev->pdev->device) {
845 offtbl = pci2id[i].card_id;
851 dev_err(&dev->pdev->dev, "Unknown card!\n");
855 dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
857 hifn_write_1(dev, HIFN_1_DMA_CNFG,
858 HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
859 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
861 addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
863 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
866 for (i = 0; i < 12; ++i) {
867 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
868 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
872 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
874 dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev));
879 static void hifn_init_dma(struct hifn_device *dev)
881 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
882 u32 dptr = dev->desc_dma;
885 for (i = 0; i < HIFN_D_CMD_RSIZE; ++i)
886 dma->cmdr[i].p = __cpu_to_le32(dptr +
887 offsetof(struct hifn_dma, command_bufs[i][0]));
888 for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
889 dma->resr[i].p = __cpu_to_le32(dptr +
890 offsetof(struct hifn_dma, result_bufs[i][0]));
892 /* Setup LAST descriptors. */
893 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
894 offsetof(struct hifn_dma, cmdr[0]));
895 dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
896 offsetof(struct hifn_dma, srcr[0]));
897 dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
898 offsetof(struct hifn_dma, dstr[0]));
899 dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
900 offsetof(struct hifn_dma, resr[0]));
902 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
903 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
904 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
908 * Initialize the PLL. We need to know the frequency of the reference clock
909 * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
910 * allows us to operate without the risk of overclocking the chip. If it
911 * actually uses 33MHz, the chip will operate at half the speed, this can be
912 * overridden by specifying the frequency as module parameter (pci33).
914 * Unfortunately the PCI clock is not very suitable since the HIFN needs a
915 * stable clock and the PCI clock frequency may vary, so the default is the
916 * external clock. There is no way to find out its frequency, we default to
917 * 66MHz since according to Mike Ham of HiFn, almost every board in existence
918 * has an external crystal populated at 66MHz.
920 static void hifn_init_pll(struct hifn_device *dev)
922 unsigned int freq, m;
925 pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
927 if (strncmp(hifn_pll_ref, "ext", 3) == 0)
928 pllcfg |= HIFN_PLL_REF_CLK_PLL;
930 pllcfg |= HIFN_PLL_REF_CLK_HBI;
932 if (hifn_pll_ref[3] != '\0')
933 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
936 dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n",
940 m = HIFN_PLL_FCK_MAX / freq;
942 pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
944 pllcfg |= HIFN_PLL_IS_1_8;
946 pllcfg |= HIFN_PLL_IS_9_12;
948 /* Select clock source and enable clock bypass */
949 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
950 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
952 /* Let the chip lock to the input clock */
955 /* Disable clock bypass */
956 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
957 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
959 /* Switch the engines to the PLL */
960 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
961 HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
964 * The Fpk_clk runs at half the total speed. Its frequency is needed to
965 * calculate the minimum time between two reads of the rng. Since 33MHz
966 * is actually 33.333... we overestimate the frequency here, resulting
967 * in slightly larger intervals.
969 dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
972 static void hifn_init_registers(struct hifn_device *dev)
974 u32 dptr = dev->desc_dma;
976 /* Initialization magic... */
977 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
978 hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
979 hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
981 /* write all 4 ring address registers */
982 hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
983 offsetof(struct hifn_dma, cmdr[0]));
984 hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
985 offsetof(struct hifn_dma, srcr[0]));
986 hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
987 offsetof(struct hifn_dma, dstr[0]));
988 hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
989 offsetof(struct hifn_dma, resr[0]));
993 hifn_write_1(dev, HIFN_1_DMA_CSR,
994 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
995 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
996 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
997 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
998 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
999 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1000 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1001 HIFN_DMACSR_S_WAIT |
1002 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1003 HIFN_DMACSR_C_WAIT |
1004 HIFN_DMACSR_ENGINE |
1005 HIFN_DMACSR_PUBDONE);
1007 hifn_write_1(dev, HIFN_1_DMA_CSR,
1008 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1009 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
1010 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1011 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1012 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1013 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1014 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1015 HIFN_DMACSR_S_WAIT |
1016 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1017 HIFN_DMACSR_C_WAIT |
1018 HIFN_DMACSR_ENGINE |
1019 HIFN_DMACSR_PUBDONE);
1021 hifn_read_1(dev, HIFN_1_DMA_CSR);
1023 dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1024 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1025 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1027 dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
1029 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1030 hifn_read_1(dev, HIFN_1_DMA_IER);
1032 hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
1033 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1034 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1037 hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
1041 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1042 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1043 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1044 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1045 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1048 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
1049 unsigned dlen, unsigned slen, u16 mask, u8 snum)
1051 struct hifn_base_command *base_cmd;
1054 base_cmd = (struct hifn_base_command *)buf_pos;
1055 base_cmd->masks = __cpu_to_le16(mask);
1056 base_cmd->total_source_count =
1057 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
1058 base_cmd->total_dest_count =
1059 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1063 base_cmd->session_num = __cpu_to_le16(snum |
1064 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1065 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1067 return sizeof(struct hifn_base_command);
1070 static int hifn_setup_crypto_command(struct hifn_device *dev,
1071 u8 *buf, unsigned dlen, unsigned slen,
1072 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
1074 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1075 struct hifn_crypt_command *cry_cmd;
1079 cry_cmd = (struct hifn_crypt_command *)buf_pos;
1081 cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
1083 cry_cmd->masks = __cpu_to_le16(mode |
1084 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
1085 HIFN_CRYPT_CMD_SRCLEN_M));
1086 cry_cmd->header_skip = 0;
1087 cry_cmd->reserved = 0;
1089 buf_pos += sizeof(struct hifn_crypt_command);
1092 if (dma->cmdu > 1) {
1093 dev->dmareg |= HIFN_DMAIER_C_WAIT;
1094 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1098 memcpy(buf_pos, key, keylen);
1102 memcpy(buf_pos, iv, ivsize);
1106 cmd_len = buf_pos - buf;
1111 static int hifn_setup_cmd_desc(struct hifn_device *dev,
1112 struct hifn_context *ctx, struct hifn_request_context *rctx,
1113 void *priv, unsigned int nbytes)
1115 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1116 int cmd_len, sa_idx;
1121 buf_pos = buf = dma->command_bufs[dma->cmdi];
1125 case ACRYPTO_OP_DECRYPT:
1126 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1128 case ACRYPTO_OP_ENCRYPT:
1129 mask = HIFN_BASE_CMD_CRYPT;
1131 case ACRYPTO_OP_HMAC:
1132 mask = HIFN_BASE_CMD_MAC;
1138 buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1139 nbytes, mask, dev->snum);
1141 if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
1145 md |= HIFN_CRYPT_CMD_NEW_KEY;
1146 if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
1147 md |= HIFN_CRYPT_CMD_NEW_IV;
1149 switch (rctx->mode) {
1150 case ACRYPTO_MODE_ECB:
1151 md |= HIFN_CRYPT_CMD_MODE_ECB;
1153 case ACRYPTO_MODE_CBC:
1154 md |= HIFN_CRYPT_CMD_MODE_CBC;
1156 case ACRYPTO_MODE_CFB:
1157 md |= HIFN_CRYPT_CMD_MODE_CFB;
1159 case ACRYPTO_MODE_OFB:
1160 md |= HIFN_CRYPT_CMD_MODE_OFB;
1166 switch (rctx->type) {
1167 case ACRYPTO_TYPE_AES_128:
1168 if (ctx->keysize != 16)
1170 md |= HIFN_CRYPT_CMD_KSZ_128 |
1171 HIFN_CRYPT_CMD_ALG_AES;
1173 case ACRYPTO_TYPE_AES_192:
1174 if (ctx->keysize != 24)
1176 md |= HIFN_CRYPT_CMD_KSZ_192 |
1177 HIFN_CRYPT_CMD_ALG_AES;
1179 case ACRYPTO_TYPE_AES_256:
1180 if (ctx->keysize != 32)
1182 md |= HIFN_CRYPT_CMD_KSZ_256 |
1183 HIFN_CRYPT_CMD_ALG_AES;
1185 case ACRYPTO_TYPE_3DES:
1186 if (ctx->keysize != 24)
1188 md |= HIFN_CRYPT_CMD_ALG_3DES;
1190 case ACRYPTO_TYPE_DES:
1191 if (ctx->keysize != 8)
1193 md |= HIFN_CRYPT_CMD_ALG_DES;
1199 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1200 nbytes, nbytes, ctx->key, ctx->keysize,
1201 rctx->iv, rctx->ivsize, md);
1204 dev->sa[sa_idx] = priv;
1207 cmd_len = buf_pos - buf;
1208 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1209 HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1211 if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1212 dma->cmdr[dma->cmdi].l = __cpu_to_le32(
1213 HIFN_D_VALID | HIFN_D_LAST |
1214 HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1217 dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID);
1220 if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1221 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1222 dev->flags |= HIFN_FLAG_CMD_BUSY;
1230 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1231 unsigned int offset, unsigned int size, int last)
1233 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1237 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1241 dma->srcr[idx].p = __cpu_to_le32(addr);
1242 dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1243 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1245 if (++idx == HIFN_D_SRC_RSIZE) {
1246 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1247 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1248 (last ? HIFN_D_LAST : 0));
1255 if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1256 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1257 dev->flags |= HIFN_FLAG_SRC_BUSY;
1263 static void hifn_setup_res_desc(struct hifn_device *dev)
1265 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1267 dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1268 HIFN_D_VALID | HIFN_D_LAST);
1270 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1274 if (++dma->resi == HIFN_D_RES_RSIZE) {
1275 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1276 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1282 if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1283 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1284 dev->flags |= HIFN_FLAG_RES_BUSY;
1288 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1289 unsigned offset, unsigned size, int last)
1291 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1295 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1298 dma->dstr[idx].p = __cpu_to_le32(addr);
1299 dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1300 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1302 if (++idx == HIFN_D_DST_RSIZE) {
1303 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1304 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1305 (last ? HIFN_D_LAST : 0));
1311 if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1312 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1313 dev->flags |= HIFN_FLAG_DST_BUSY;
1317 static int hifn_setup_dma(struct hifn_device *dev,
1318 struct hifn_context *ctx, struct hifn_request_context *rctx,
1319 struct scatterlist *src, struct scatterlist *dst,
1320 unsigned int nbytes, void *priv)
1322 struct scatterlist *t;
1323 struct page *spage, *dpage;
1324 unsigned int soff, doff;
1325 unsigned int n, len;
1329 spage = sg_page(src);
1331 len = min(src->length, n);
1333 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
1339 t = &rctx->walk.cache[0];
1342 if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1343 BUG_ON(!sg_page(t));
1348 BUG_ON(!sg_page(dst));
1349 dpage = sg_page(dst);
1355 hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
1362 hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
1363 hifn_setup_res_desc(dev);
1367 static int hifn_cipher_walk_init(struct hifn_cipher_walk *w,
1368 int num, gfp_t gfp_flags)
1372 num = min(ASYNC_SCATTERLIST_CACHE, num);
1373 sg_init_table(w->cache, num);
1376 for (i = 0; i < num; ++i) {
1377 struct page *page = alloc_page(gfp_flags);
1378 struct scatterlist *s;
1385 sg_set_page(s, page, PAGE_SIZE, 0);
1392 static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w)
1396 for (i = 0; i < w->num; ++i) {
1397 struct scatterlist *s = &w->cache[i];
1399 __free_page(sg_page(s));
1407 static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst,
1408 unsigned int size, unsigned int *nbytesp)
1410 unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1413 if (drest < size || size > nbytes)
1417 copy = min3(drest, size, dst->length);
1423 pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1424 __func__, copy, size, drest, nbytes);
1436 static int hifn_cipher_walk(struct ablkcipher_request *req,
1437 struct hifn_cipher_walk *w)
1439 struct scatterlist *dst, *t;
1440 unsigned int nbytes = req->nbytes, offset, copy, diff;
1446 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1449 dst = &req->dst[idx];
1451 pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
1452 __func__, dst->length, dst->offset, offset, nbytes);
1454 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1455 !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
1457 unsigned slen = min(dst->length - offset, nbytes);
1458 unsigned dlen = PAGE_SIZE;
1462 err = ablkcipher_add(&dlen, dst, slen, &nbytes);
1468 copy = slen & ~(HIFN_D_DST_DALIGN - 1);
1469 diff = slen & (HIFN_D_DST_DALIGN - 1);
1471 if (dlen < nbytes) {
1473 * Destination page does not have enough space
1474 * to put there additional blocksized chunk,
1475 * so we mark that page as containing only
1476 * blocksize aligned chunks:
1477 * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
1478 * and increase number of bytes to be processed
1485 * Temporary of course...
1486 * Kick author if you will catch this one.
1488 pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n",
1489 __func__, dlen, nbytes, slen, offset);
1490 pr_err("%s: please contact author to fix this "
1491 "issue, generally you should not catch "
1492 "this path under any condition but who "
1493 "knows how did you use crypto code.\n"
1494 "Thank you.\n", __func__);
1497 copy += diff + nbytes;
1499 dst = &req->dst[idx];
1501 err = ablkcipher_add(&dlen, dst, nbytes, &nbytes);
1511 nbytes -= min(dst->length, nbytes);
1521 static int hifn_setup_session(struct ablkcipher_request *req)
1523 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1524 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
1525 struct hifn_device *dev = ctx->dev;
1526 unsigned long dlen, flags;
1527 unsigned int nbytes = req->nbytes, idx = 0;
1528 int err = -EINVAL, sg_num;
1529 struct scatterlist *dst;
1531 if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
1534 rctx->walk.flags = 0;
1537 dst = &req->dst[idx];
1538 dlen = min(dst->length, nbytes);
1540 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1541 !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
1542 rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1548 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1549 err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
1554 sg_num = hifn_cipher_walk(req, &rctx->walk);
1560 spin_lock_irqsave(&dev->lock, flags);
1561 if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1566 err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req);
1572 dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1573 spin_unlock_irqrestore(&dev->lock, flags);
1578 spin_unlock_irqrestore(&dev->lock, flags);
1581 dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1582 "type: %u, err: %d.\n",
1583 rctx->iv, rctx->ivsize,
1584 ctx->key, ctx->keysize,
1585 rctx->mode, rctx->op, rctx->type, err);
1591 static int hifn_start_device(struct hifn_device *dev)
1595 dev->started = dev->active = 0;
1596 hifn_reset_dma(dev, 1);
1598 err = hifn_enable_crypto(dev);
1602 hifn_reset_puc(dev);
1606 hifn_init_registers(dev);
1608 hifn_init_pubrng(dev);
1613 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1614 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1616 unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1620 if (srest < size || size > nbytes)
1624 copy = min3(srest, dst->length, size);
1626 daddr = kmap_atomic(sg_page(dst));
1627 memcpy(daddr + dst->offset + offset, saddr, copy);
1628 kunmap_atomic(daddr);
1636 pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1637 __func__, copy, size, srest, nbytes);
1649 static inline void hifn_complete_sa(struct hifn_device *dev, int i)
1651 unsigned long flags;
1653 spin_lock_irqsave(&dev->lock, flags);
1656 if (dev->started < 0)
1657 dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__,
1659 spin_unlock_irqrestore(&dev->lock, flags);
1660 BUG_ON(dev->started < 0);
1663 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1665 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
1667 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1668 unsigned int nbytes = req->nbytes;
1670 struct scatterlist *dst, *t;
1674 t = &rctx->walk.cache[idx];
1675 dst = &req->dst[idx];
1677 pr_debug("\n%s: sg_page(t): %p, t->length: %u, "
1678 "sg_page(dst): %p, dst->length: %u, "
1680 __func__, sg_page(t), t->length,
1681 sg_page(dst), dst->length, nbytes);
1684 nbytes -= min(dst->length, nbytes);
1689 saddr = kmap_atomic(sg_page(t));
1691 err = ablkcipher_get(saddr, &t->length, t->offset,
1692 dst, nbytes, &nbytes);
1694 kunmap_atomic(saddr);
1699 kunmap_atomic(saddr);
1702 hifn_cipher_walk_exit(&rctx->walk);
1705 req->base.complete(&req->base, error);
1708 static void hifn_clear_rings(struct hifn_device *dev, int error)
1710 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1713 dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1714 "k: %d.%d.%d.%d.\n",
1715 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1716 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1717 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1719 i = dma->resk; u = dma->resu;
1721 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1727 hifn_process_ready(dev->sa[i], error);
1728 hifn_complete_sa(dev, i);
1731 if (++i == HIFN_D_RES_RSIZE)
1735 dma->resk = i; dma->resu = u;
1737 i = dma->srck; u = dma->srcu;
1739 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1741 if (++i == HIFN_D_SRC_RSIZE)
1745 dma->srck = i; dma->srcu = u;
1747 i = dma->cmdk; u = dma->cmdu;
1749 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1751 if (++i == HIFN_D_CMD_RSIZE)
1755 dma->cmdk = i; dma->cmdu = u;
1757 i = dma->dstk; u = dma->dstu;
1759 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1761 if (++i == HIFN_D_DST_RSIZE)
1765 dma->dstk = i; dma->dstu = u;
1767 dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1768 "k: %d.%d.%d.%d.\n",
1769 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1770 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1771 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1774 static void hifn_work(struct work_struct *work)
1776 struct delayed_work *dw = to_delayed_work(work);
1777 struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1778 unsigned long flags;
1782 spin_lock_irqsave(&dev->lock, flags);
1783 if (dev->active == 0) {
1784 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1786 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1787 dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1788 r |= HIFN_DMACSR_C_CTRL_DIS;
1790 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1791 dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1792 r |= HIFN_DMACSR_S_CTRL_DIS;
1794 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1795 dev->flags &= ~HIFN_FLAG_DST_BUSY;
1796 r |= HIFN_DMACSR_D_CTRL_DIS;
1798 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1799 dev->flags &= ~HIFN_FLAG_RES_BUSY;
1800 r |= HIFN_DMACSR_R_CTRL_DIS;
1803 hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1807 if ((dev->prev_success == dev->success) && dev->started)
1809 dev->prev_success = dev->success;
1810 spin_unlock_irqrestore(&dev->lock, flags);
1813 if (++dev->reset >= 5) {
1815 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1817 dev_info(&dev->pdev->dev,
1818 "r: %08x, active: %d, started: %d, "
1819 "success: %lu: qlen: %u/%u, reset: %d.\n",
1820 r, dev->active, dev->started,
1821 dev->success, dev->queue.qlen, dev->queue.max_qlen,
1824 dev_info(&dev->pdev->dev, "%s: res: ", __func__);
1825 for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
1826 pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]);
1828 hifn_process_ready(dev->sa[i], -ENODEV);
1829 hifn_complete_sa(dev, i);
1834 hifn_reset_dma(dev, 1);
1835 hifn_stop_device(dev);
1836 hifn_start_device(dev);
1840 tasklet_schedule(&dev->tasklet);
1843 schedule_delayed_work(&dev->work, HZ);
1846 static irqreturn_t hifn_interrupt(int irq, void *data)
1848 struct hifn_device *dev = (struct hifn_device *)data;
1849 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1850 u32 dmacsr, restart;
1852 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1854 dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1855 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1856 dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1857 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1858 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
1860 if ((dmacsr & dev->dmareg) == 0)
1863 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1865 if (dmacsr & HIFN_DMACSR_ENGINE)
1866 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1867 if (dmacsr & HIFN_DMACSR_PUBDONE)
1868 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1869 hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1871 restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1873 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1875 dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1876 !!(dmacsr & HIFN_DMACSR_R_OVER),
1877 !!(dmacsr & HIFN_DMACSR_D_OVER),
1878 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1879 if (!!(puisr & HIFN_PUISR_DSTOVER))
1880 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1881 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1882 HIFN_DMACSR_D_OVER));
1885 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1886 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1888 dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n",
1889 !!(dmacsr & HIFN_DMACSR_C_ABORT),
1890 !!(dmacsr & HIFN_DMACSR_S_ABORT),
1891 !!(dmacsr & HIFN_DMACSR_D_ABORT),
1892 !!(dmacsr & HIFN_DMACSR_R_ABORT));
1893 hifn_reset_dma(dev, 1);
1895 hifn_init_registers(dev);
1898 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1899 dev_dbg(&dev->pdev->dev, "wait on command.\n");
1900 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1901 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1904 tasklet_schedule(&dev->tasklet);
1909 static void hifn_flush(struct hifn_device *dev)
1911 unsigned long flags;
1912 struct crypto_async_request *async_req;
1913 struct ablkcipher_request *req;
1914 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1917 for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
1918 struct hifn_desc *d = &dma->resr[i];
1921 hifn_process_ready(dev->sa[i],
1922 (d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0);
1923 hifn_complete_sa(dev, i);
1927 spin_lock_irqsave(&dev->lock, flags);
1928 while ((async_req = crypto_dequeue_request(&dev->queue))) {
1929 req = ablkcipher_request_cast(async_req);
1930 spin_unlock_irqrestore(&dev->lock, flags);
1932 hifn_process_ready(req, -ENODEV);
1934 spin_lock_irqsave(&dev->lock, flags);
1936 spin_unlock_irqrestore(&dev->lock, flags);
1939 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1942 struct hifn_context *ctx = crypto_ablkcipher_ctx(cipher);
1943 struct hifn_device *dev = ctx->dev;
1946 err = verify_ablkcipher_des_key(cipher, key);
1950 dev->flags &= ~HIFN_FLAG_OLD_KEY;
1952 memcpy(ctx->key, key, len);
1958 static int hifn_des3_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1961 struct hifn_context *ctx = crypto_ablkcipher_ctx(cipher);
1962 struct hifn_device *dev = ctx->dev;
1965 err = verify_ablkcipher_des3_key(cipher, key);
1969 dev->flags &= ~HIFN_FLAG_OLD_KEY;
1971 memcpy(ctx->key, key, len);
1977 static int hifn_handle_req(struct ablkcipher_request *req)
1979 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1980 struct hifn_device *dev = ctx->dev;
1983 if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
1984 err = hifn_setup_session(req);
1986 if (err == -EAGAIN) {
1987 unsigned long flags;
1989 spin_lock_irqsave(&dev->lock, flags);
1990 err = ablkcipher_enqueue_request(&dev->queue, req);
1991 spin_unlock_irqrestore(&dev->lock, flags);
1997 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
2000 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2001 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
2004 ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
2006 if (req->info && mode != ACRYPTO_MODE_ECB) {
2007 if (type == ACRYPTO_TYPE_AES_128)
2008 ivsize = HIFN_AES_IV_LENGTH;
2009 else if (type == ACRYPTO_TYPE_DES)
2010 ivsize = HIFN_DES_KEY_LENGTH;
2011 else if (type == ACRYPTO_TYPE_3DES)
2012 ivsize = HIFN_3DES_KEY_LENGTH;
2015 if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
2016 if (ctx->keysize == 24)
2017 type = ACRYPTO_TYPE_AES_192;
2018 else if (ctx->keysize == 32)
2019 type = ACRYPTO_TYPE_AES_256;
2025 rctx->iv = req->info;
2026 rctx->ivsize = ivsize;
2029 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2030 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2031 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2034 return hifn_handle_req(req);
2037 static int hifn_process_queue(struct hifn_device *dev)
2039 struct crypto_async_request *async_req, *backlog;
2040 struct ablkcipher_request *req;
2041 unsigned long flags;
2044 while (dev->started < HIFN_QUEUE_LENGTH) {
2045 spin_lock_irqsave(&dev->lock, flags);
2046 backlog = crypto_get_backlog(&dev->queue);
2047 async_req = crypto_dequeue_request(&dev->queue);
2048 spin_unlock_irqrestore(&dev->lock, flags);
2054 backlog->complete(backlog, -EINPROGRESS);
2056 req = ablkcipher_request_cast(async_req);
2058 err = hifn_handle_req(req);
2066 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2070 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2071 struct hifn_device *dev = ctx->dev;
2073 err = hifn_setup_crypto_req(req, op, type, mode);
2077 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2078 hifn_process_queue(dev);
2080 return -EINPROGRESS;
2084 * AES ecryption functions.
2086 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2088 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2089 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2091 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2093 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2094 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2096 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2098 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2099 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2101 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2103 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2104 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2108 * AES decryption functions.
2110 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2112 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2113 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2115 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2117 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2118 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2120 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2122 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2123 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2125 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2127 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2128 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2132 * DES ecryption functions.
2134 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2136 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2137 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2139 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2141 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2142 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2144 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2146 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2147 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2149 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2151 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2152 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2156 * DES decryption functions.
2158 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2160 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2161 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2163 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2165 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2166 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2168 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2170 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2171 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2173 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2175 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2176 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2180 * 3DES ecryption functions.
2182 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2184 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2185 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2187 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2189 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2190 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2192 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2194 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2195 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2197 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2199 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2200 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2203 /* 3DES decryption functions. */
2204 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2206 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2207 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2209 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2211 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2212 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2214 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2216 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2217 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2219 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2221 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2222 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2225 struct hifn_alg_template {
2226 char name[CRYPTO_MAX_ALG_NAME];
2227 char drv_name[CRYPTO_MAX_ALG_NAME];
2229 struct ablkcipher_alg ablkcipher;
2232 static struct hifn_alg_template hifn_alg_templates[] = {
2234 * 3DES ECB, CBC, CFB and OFB modes.
2237 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
2239 .min_keysize = HIFN_3DES_KEY_LENGTH,
2240 .max_keysize = HIFN_3DES_KEY_LENGTH,
2241 .setkey = hifn_des3_setkey,
2242 .encrypt = hifn_encrypt_3des_cfb,
2243 .decrypt = hifn_decrypt_3des_cfb,
2247 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
2249 .min_keysize = HIFN_3DES_KEY_LENGTH,
2250 .max_keysize = HIFN_3DES_KEY_LENGTH,
2251 .setkey = hifn_des3_setkey,
2252 .encrypt = hifn_encrypt_3des_ofb,
2253 .decrypt = hifn_decrypt_3des_ofb,
2257 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
2259 .ivsize = HIFN_IV_LENGTH,
2260 .min_keysize = HIFN_3DES_KEY_LENGTH,
2261 .max_keysize = HIFN_3DES_KEY_LENGTH,
2262 .setkey = hifn_des3_setkey,
2263 .encrypt = hifn_encrypt_3des_cbc,
2264 .decrypt = hifn_decrypt_3des_cbc,
2268 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
2270 .min_keysize = HIFN_3DES_KEY_LENGTH,
2271 .max_keysize = HIFN_3DES_KEY_LENGTH,
2272 .setkey = hifn_des3_setkey,
2273 .encrypt = hifn_encrypt_3des_ecb,
2274 .decrypt = hifn_decrypt_3des_ecb,
2279 * DES ECB, CBC, CFB and OFB modes.
2282 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
2284 .min_keysize = HIFN_DES_KEY_LENGTH,
2285 .max_keysize = HIFN_DES_KEY_LENGTH,
2286 .setkey = hifn_setkey,
2287 .encrypt = hifn_encrypt_des_cfb,
2288 .decrypt = hifn_decrypt_des_cfb,
2292 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
2294 .min_keysize = HIFN_DES_KEY_LENGTH,
2295 .max_keysize = HIFN_DES_KEY_LENGTH,
2296 .setkey = hifn_setkey,
2297 .encrypt = hifn_encrypt_des_ofb,
2298 .decrypt = hifn_decrypt_des_ofb,
2302 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
2304 .ivsize = HIFN_IV_LENGTH,
2305 .min_keysize = HIFN_DES_KEY_LENGTH,
2306 .max_keysize = HIFN_DES_KEY_LENGTH,
2307 .setkey = hifn_setkey,
2308 .encrypt = hifn_encrypt_des_cbc,
2309 .decrypt = hifn_decrypt_des_cbc,
2313 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
2315 .min_keysize = HIFN_DES_KEY_LENGTH,
2316 .max_keysize = HIFN_DES_KEY_LENGTH,
2317 .setkey = hifn_setkey,
2318 .encrypt = hifn_encrypt_des_ecb,
2319 .decrypt = hifn_decrypt_des_ecb,
2324 * AES ECB, CBC, CFB and OFB modes.
2327 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
2329 .min_keysize = AES_MIN_KEY_SIZE,
2330 .max_keysize = AES_MAX_KEY_SIZE,
2331 .setkey = hifn_setkey,
2332 .encrypt = hifn_encrypt_aes_ecb,
2333 .decrypt = hifn_decrypt_aes_ecb,
2337 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
2339 .ivsize = HIFN_AES_IV_LENGTH,
2340 .min_keysize = AES_MIN_KEY_SIZE,
2341 .max_keysize = AES_MAX_KEY_SIZE,
2342 .setkey = hifn_setkey,
2343 .encrypt = hifn_encrypt_aes_cbc,
2344 .decrypt = hifn_decrypt_aes_cbc,
2348 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
2350 .min_keysize = AES_MIN_KEY_SIZE,
2351 .max_keysize = AES_MAX_KEY_SIZE,
2352 .setkey = hifn_setkey,
2353 .encrypt = hifn_encrypt_aes_cfb,
2354 .decrypt = hifn_decrypt_aes_cfb,
2358 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
2360 .min_keysize = AES_MIN_KEY_SIZE,
2361 .max_keysize = AES_MAX_KEY_SIZE,
2362 .setkey = hifn_setkey,
2363 .encrypt = hifn_encrypt_aes_ofb,
2364 .decrypt = hifn_decrypt_aes_ofb,
2369 static int hifn_cra_init(struct crypto_tfm *tfm)
2371 struct crypto_alg *alg = tfm->__crt_alg;
2372 struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2373 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2376 tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context);
2380 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2382 struct hifn_crypto_alg *alg;
2385 alg = kzalloc(sizeof(*alg), GFP_KERNEL);
2389 snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2390 snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
2391 t->drv_name, dev->name);
2393 alg->alg.cra_priority = 300;
2394 alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2395 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
2396 alg->alg.cra_blocksize = t->bsize;
2397 alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2398 alg->alg.cra_alignmask = 0;
2399 alg->alg.cra_type = &crypto_ablkcipher_type;
2400 alg->alg.cra_module = THIS_MODULE;
2401 alg->alg.cra_u.ablkcipher = t->ablkcipher;
2402 alg->alg.cra_init = hifn_cra_init;
2406 list_add_tail(&alg->entry, &dev->alg_list);
2408 err = crypto_register_alg(&alg->alg);
2410 list_del(&alg->entry);
2417 static void hifn_unregister_alg(struct hifn_device *dev)
2419 struct hifn_crypto_alg *a, *n;
2421 list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2422 list_del(&a->entry);
2423 crypto_unregister_alg(&a->alg);
2428 static int hifn_register_alg(struct hifn_device *dev)
2432 for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) {
2433 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2441 hifn_unregister_alg(dev);
2445 static void hifn_tasklet_callback(unsigned long data)
2447 struct hifn_device *dev = (struct hifn_device *)data;
2450 * This is ok to call this without lock being held,
2451 * althogh it modifies some parameters used in parallel,
2452 * (like dev->success), but they are used in process
2453 * context or update is atomic (like setting dev->sa[i] to NULL).
2455 hifn_clear_rings(dev, 0);
2457 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2458 hifn_process_queue(dev);
2461 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2464 struct hifn_device *dev;
2467 err = pci_enable_device(pdev);
2470 pci_set_master(pdev);
2472 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2474 goto err_out_disable_pci_device;
2476 snprintf(name, sizeof(name), "hifn%d",
2477 atomic_inc_return(&hifn_dev_number) - 1);
2479 err = pci_request_regions(pdev, name);
2481 goto err_out_disable_pci_device;
2483 if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2484 pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2485 pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2486 dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n");
2488 goto err_out_free_regions;
2491 dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2495 goto err_out_free_regions;
2498 INIT_LIST_HEAD(&dev->alg_list);
2500 snprintf(dev->name, sizeof(dev->name), "%s", name);
2501 spin_lock_init(&dev->lock);
2503 for (i = 0; i < 3; ++i) {
2504 unsigned long addr, size;
2506 addr = pci_resource_start(pdev, i);
2507 size = pci_resource_len(pdev, i);
2509 dev->bar[i] = ioremap_nocache(addr, size);
2512 goto err_out_unmap_bars;
2516 dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma),
2518 if (!dev->desc_virt) {
2519 dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n");
2521 goto err_out_unmap_bars;
2525 dev->irq = pdev->irq;
2527 for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
2530 pci_set_drvdata(pdev, dev);
2532 tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2534 crypto_init_queue(&dev->queue, 1);
2536 err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2538 dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n",
2541 goto err_out_free_desc;
2544 err = hifn_start_device(dev);
2546 goto err_out_free_irq;
2548 err = hifn_register_rng(dev);
2550 goto err_out_stop_device;
2552 err = hifn_register_alg(dev);
2554 goto err_out_unregister_rng;
2556 INIT_DELAYED_WORK(&dev->work, hifn_work);
2557 schedule_delayed_work(&dev->work, HZ);
2559 dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been "
2560 "successfully registered as %s.\n",
2561 pci_name(pdev), dev->name);
2565 err_out_unregister_rng:
2566 hifn_unregister_rng(dev);
2567 err_out_stop_device:
2568 hifn_reset_dma(dev, 1);
2569 hifn_stop_device(dev);
2571 free_irq(dev->irq, dev);
2572 tasklet_kill(&dev->tasklet);
2574 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2575 dev->desc_virt, dev->desc_dma);
2578 for (i = 0; i < 3; ++i)
2580 iounmap(dev->bar[i]);
2583 err_out_free_regions:
2584 pci_release_regions(pdev);
2586 err_out_disable_pci_device:
2587 pci_disable_device(pdev);
2592 static void hifn_remove(struct pci_dev *pdev)
2595 struct hifn_device *dev;
2597 dev = pci_get_drvdata(pdev);
2600 cancel_delayed_work_sync(&dev->work);
2602 hifn_unregister_rng(dev);
2603 hifn_unregister_alg(dev);
2604 hifn_reset_dma(dev, 1);
2605 hifn_stop_device(dev);
2607 free_irq(dev->irq, dev);
2608 tasklet_kill(&dev->tasklet);
2612 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2613 dev->desc_virt, dev->desc_dma);
2614 for (i = 0; i < 3; ++i)
2616 iounmap(dev->bar[i]);
2621 pci_release_regions(pdev);
2622 pci_disable_device(pdev);
2625 static struct pci_device_id hifn_pci_tbl[] = {
2626 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2627 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2630 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2632 static struct pci_driver hifn_pci_driver = {
2634 .id_table = hifn_pci_tbl,
2635 .probe = hifn_probe,
2636 .remove = hifn_remove,
2639 static int __init hifn_init(void)
2644 /* HIFN supports only 32-bit addresses */
2645 BUILD_BUG_ON(sizeof(dma_addr_t) != 4);
2647 if (strncmp(hifn_pll_ref, "ext", 3) &&
2648 strncmp(hifn_pll_ref, "pci", 3)) {
2649 pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext");
2654 * For the 7955/7956 the reference clock frequency must be in the
2655 * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
2656 * but this chip is currently not supported.
2658 if (hifn_pll_ref[3] != '\0') {
2659 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
2660 if (freq < 20 || freq > 100) {
2661 pr_err("hifn795x: invalid hifn_pll_ref frequency, must"
2662 "be in the range of 20-100");
2667 err = pci_register_driver(&hifn_pci_driver);
2669 pr_err("Failed to register PCI driver for %s device.\n",
2670 hifn_pci_driver.name);
2674 pr_info("Driver for HIFN 795x crypto accelerator chip "
2675 "has been successfully registered.\n");
2680 static void __exit hifn_fini(void)
2682 pci_unregister_driver(&hifn_pci_driver);
2684 pr_info("Driver for HIFN 795x crypto accelerator chip "
2685 "has been successfully unregistered.\n");
2688 module_init(hifn_init);
2689 module_exit(hifn_fini);
2691 MODULE_LICENSE("GPL");
2692 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2693 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");