1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 * Author: Arnaud Ebalard <arno@natisbad.org>
8 * This work is based on an initial version written by
9 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
12 #include <crypto/hmac.h>
13 #include <crypto/md5.h>
14 #include <crypto/sha.h>
18 struct mv_cesa_ahash_dma_iter {
19 struct mv_cesa_dma_iter base;
20 struct mv_cesa_sg_dma_iter src;
24 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
25 struct ahash_request *req)
27 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
28 unsigned int len = req->nbytes + creq->cache_ptr;
31 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
33 mv_cesa_req_dma_iter_init(&iter->base, len);
34 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
35 iter->src.op_offset = creq->cache_ptr;
39 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
41 iter->src.op_offset = 0;
43 return mv_cesa_req_dma_iter_next_op(&iter->base);
47 mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags)
49 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
58 mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req)
63 dma_pool_free(cesa_dev->dma->cache_pool, req->cache,
67 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
73 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
81 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
86 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
91 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
93 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
95 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
98 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
100 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
102 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
103 mv_cesa_ahash_dma_free_cache(&creq->req.dma);
104 mv_cesa_dma_cleanup(&creq->base);
107 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
109 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
111 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
112 mv_cesa_ahash_dma_cleanup(req);
115 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
117 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
119 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
120 mv_cesa_ahash_dma_last_cleanup(req);
123 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
125 unsigned int index, padlen;
127 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
128 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
133 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
138 /* Pad out to 56 mod 64 */
139 padlen = mv_cesa_ahash_pad_len(creq);
140 memset(buf + 1, 0, padlen - 1);
143 __le64 bits = cpu_to_le64(creq->len << 3);
144 memcpy(buf + padlen, &bits, sizeof(bits));
146 __be64 bits = cpu_to_be64(creq->len << 3);
147 memcpy(buf + padlen, &bits, sizeof(bits));
153 static void mv_cesa_ahash_std_step(struct ahash_request *req)
155 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
156 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
157 struct mv_cesa_engine *engine = creq->base.engine;
158 struct mv_cesa_op_ctx *op;
159 unsigned int new_cache_ptr = 0;
162 unsigned int digsize;
165 mv_cesa_adjust_op(engine, &creq->op_tmpl);
166 memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
169 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
170 for (i = 0; i < digsize / 4; i++)
171 writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
175 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
176 creq->cache, creq->cache_ptr);
178 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
179 CESA_SA_SRAM_PAYLOAD_SIZE);
181 if (!creq->last_req) {
182 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
183 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
186 if (len - creq->cache_ptr)
187 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
189 CESA_SA_DATA_SRAM_OFFSET +
191 len - creq->cache_ptr,
196 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
198 if (creq->last_req && sreq->offset == req->nbytes &&
199 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
200 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
201 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
202 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
203 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
206 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
207 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
209 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
210 mv_cesa_set_mac_op_total_len(op, creq->len);
212 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
214 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
215 len &= CESA_HASH_BLOCK_SIZE_MSK;
216 new_cache_ptr = 64 - trailerlen;
217 memcpy_fromio(creq->cache,
219 CESA_SA_DATA_SRAM_OFFSET + len,
222 len += mv_cesa_ahash_pad_req(creq,
224 CESA_SA_DATA_SRAM_OFFSET);
227 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
228 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
230 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
234 mv_cesa_set_mac_op_frag_len(op, len);
235 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
237 /* FIXME: only update enc_len field */
238 memcpy_toio(engine->sram, op, sizeof(*op));
240 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
241 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
242 CESA_SA_DESC_CFG_FRAG_MSK);
244 creq->cache_ptr = new_cache_ptr;
246 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
247 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
248 BUG_ON(readl(engine->regs + CESA_SA_CMD) &
249 CESA_SA_CMD_EN_CESA_SA_ACCL0);
250 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
253 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
255 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
256 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
258 if (sreq->offset < (req->nbytes - creq->cache_ptr))
264 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
266 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
267 struct mv_cesa_req *basereq = &creq->base;
269 mv_cesa_dma_prepare(basereq, basereq->engine);
272 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
274 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
275 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
280 static void mv_cesa_ahash_dma_step(struct ahash_request *req)
282 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
283 struct mv_cesa_req *base = &creq->base;
285 /* We must explicitly set the digest state. */
286 if (base->chain.first->flags & CESA_TDMA_SET_STATE) {
287 struct mv_cesa_engine *engine = base->engine;
290 /* Set the hash state in the IVDIG regs. */
291 for (i = 0; i < ARRAY_SIZE(creq->state); i++)
292 writel_relaxed(creq->state[i], engine->regs +
296 mv_cesa_dma_step(base);
299 static void mv_cesa_ahash_step(struct crypto_async_request *req)
301 struct ahash_request *ahashreq = ahash_request_cast(req);
302 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
304 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
305 mv_cesa_ahash_dma_step(ahashreq);
307 mv_cesa_ahash_std_step(ahashreq);
310 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
312 struct ahash_request *ahashreq = ahash_request_cast(req);
313 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
315 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
316 return mv_cesa_dma_process(&creq->base, status);
318 return mv_cesa_ahash_std_process(ahashreq, status);
321 static void mv_cesa_ahash_complete(struct crypto_async_request *req)
323 struct ahash_request *ahashreq = ahash_request_cast(req);
324 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
325 struct mv_cesa_engine *engine = creq->base.engine;
326 unsigned int digsize;
329 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
331 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ &&
332 (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_RESULT) {
336 * Result is already in the correct endianess when the SA is
339 data = creq->base.chain.last->op->ctx.hash.hash;
340 for (i = 0; i < digsize / 4; i++)
341 creq->state[i] = cpu_to_le32(data[i]);
343 memcpy(ahashreq->result, data, digsize);
345 for (i = 0; i < digsize / 4; i++)
346 creq->state[i] = readl_relaxed(engine->regs +
348 if (creq->last_req) {
350 * Hardware's MD5 digest is in little endian format, but
351 * SHA in big endian format
354 __le32 *result = (void *)ahashreq->result;
356 for (i = 0; i < digsize / 4; i++)
357 result[i] = cpu_to_le32(creq->state[i]);
359 __be32 *result = (void *)ahashreq->result;
361 for (i = 0; i < digsize / 4; i++)
362 result[i] = cpu_to_be32(creq->state[i]);
367 atomic_sub(ahashreq->nbytes, &engine->load);
370 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
371 struct mv_cesa_engine *engine)
373 struct ahash_request *ahashreq = ahash_request_cast(req);
374 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
376 creq->base.engine = engine;
378 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
379 mv_cesa_ahash_dma_prepare(ahashreq);
381 mv_cesa_ahash_std_prepare(ahashreq);
384 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
386 struct ahash_request *ahashreq = ahash_request_cast(req);
387 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
390 mv_cesa_ahash_last_cleanup(ahashreq);
392 mv_cesa_ahash_cleanup(ahashreq);
395 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
398 ahashreq->nbytes - creq->cache_ptr);
401 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
402 .step = mv_cesa_ahash_step,
403 .process = mv_cesa_ahash_process,
404 .cleanup = mv_cesa_ahash_req_cleanup,
405 .complete = mv_cesa_ahash_complete,
408 static void mv_cesa_ahash_init(struct ahash_request *req,
409 struct mv_cesa_op_ctx *tmpl, bool algo_le)
411 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
413 memset(creq, 0, sizeof(*creq));
414 mv_cesa_update_op_cfg(tmpl,
415 CESA_SA_DESC_CFG_OP_MAC_ONLY |
416 CESA_SA_DESC_CFG_FIRST_FRAG,
417 CESA_SA_DESC_CFG_OP_MSK |
418 CESA_SA_DESC_CFG_FRAG_MSK);
419 mv_cesa_set_mac_op_total_len(tmpl, 0);
420 mv_cesa_set_mac_op_frag_len(tmpl, 0);
421 creq->op_tmpl = *tmpl;
423 creq->algo_le = algo_le;
426 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
428 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
430 ctx->base.ops = &mv_cesa_ahash_req_ops;
432 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
433 sizeof(struct mv_cesa_ahash_req));
437 static bool mv_cesa_ahash_cache_req(struct ahash_request *req)
439 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
442 if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) {
448 sg_pcopy_to_buffer(req->src, creq->src_nents,
449 creq->cache + creq->cache_ptr,
452 creq->cache_ptr += req->nbytes;
458 static struct mv_cesa_op_ctx *
459 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
460 struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
463 struct mv_cesa_op_ctx *op;
466 op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
470 /* Set the operation block fragment length. */
471 mv_cesa_set_mac_op_frag_len(op, frag_len);
473 /* Append dummy desc to launch operation */
474 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
478 if (mv_cesa_mac_op_is_first_frag(tmpl))
479 mv_cesa_update_op_cfg(tmpl,
480 CESA_SA_DESC_CFG_MID_FRAG,
481 CESA_SA_DESC_CFG_FRAG_MSK);
487 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
488 struct mv_cesa_ahash_req *creq,
491 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
494 if (!creq->cache_ptr)
497 ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags);
501 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr);
503 return mv_cesa_dma_add_data_transfer(chain,
504 CESA_SA_DATA_SRAM_OFFSET,
505 ahashdreq->cache_dma,
507 CESA_TDMA_DST_IN_SRAM,
511 static struct mv_cesa_op_ctx *
512 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
513 struct mv_cesa_ahash_dma_iter *dma_iter,
514 struct mv_cesa_ahash_req *creq,
515 unsigned int frag_len, gfp_t flags)
517 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
518 unsigned int len, trailerlen, padoff = 0;
519 struct mv_cesa_op_ctx *op;
523 * If the transfer is smaller than our maximum length, and we have
524 * some data outstanding, we can ask the engine to finish the hash.
526 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
527 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
532 mv_cesa_set_mac_op_total_len(op, creq->len);
533 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
534 CESA_SA_DESC_CFG_NOT_FRAG :
535 CESA_SA_DESC_CFG_LAST_FRAG,
536 CESA_SA_DESC_CFG_FRAG_MSK);
538 ret = mv_cesa_dma_add_result_op(chain,
539 CESA_SA_CFG_SRAM_OFFSET,
540 CESA_SA_DATA_SRAM_OFFSET,
541 CESA_TDMA_SRC_IN_SRAM, flags);
543 return ERR_PTR(-ENOMEM);
548 * The request is longer than the engine can handle, or we have
549 * no data outstanding. Manually generate the padding, adding it
550 * as a "mid" fragment.
552 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
556 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
558 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
560 ret = mv_cesa_dma_add_data_transfer(chain,
561 CESA_SA_DATA_SRAM_OFFSET +
563 ahashdreq->padding_dma,
564 len, CESA_TDMA_DST_IN_SRAM,
569 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
574 if (len == trailerlen)
580 ret = mv_cesa_dma_add_data_transfer(chain,
581 CESA_SA_DATA_SRAM_OFFSET,
582 ahashdreq->padding_dma +
585 CESA_TDMA_DST_IN_SRAM,
590 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
594 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
596 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
597 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
598 GFP_KERNEL : GFP_ATOMIC;
599 struct mv_cesa_req *basereq = &creq->base;
600 struct mv_cesa_ahash_dma_iter iter;
601 struct mv_cesa_op_ctx *op = NULL;
602 unsigned int frag_len;
603 bool set_state = false;
607 basereq->chain.first = NULL;
608 basereq->chain.last = NULL;
610 if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
613 if (creq->src_nents) {
614 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
622 mv_cesa_tdma_desc_iter_init(&basereq->chain);
623 mv_cesa_ahash_req_iter_init(&iter, req);
626 * Add the cache (left-over data from a previous block) first.
627 * This will never overflow the SRAM size.
629 ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags);
635 * Add all the new data, inserting an operation block and
636 * launch command between each full SRAM block-worth of
637 * data. We intentionally do not add the final op block.
640 ret = mv_cesa_dma_add_op_transfers(&basereq->chain,
646 frag_len = iter.base.op_len;
648 if (!mv_cesa_ahash_req_iter_next_op(&iter))
651 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
659 /* Account for the data that was in the cache. */
660 frag_len = iter.base.op_len;
664 * At this point, frag_len indicates whether we have any data
665 * outstanding which needs an operation. Queue up the final
666 * operation, which depends whether this is the final request.
669 op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq,
672 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
681 * If results are copied via DMA, this means that this
682 * request can be directly processed by the engine,
683 * without partial updates. So we can chain it at the
684 * DMA level with other requests.
686 type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK;
688 if (op && type != CESA_TDMA_RESULT) {
689 /* Add dummy desc to wait for crypto operation end */
690 ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);
696 creq->cache_ptr = req->nbytes + creq->cache_ptr -
701 basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ;
703 if (type != CESA_TDMA_RESULT)
704 basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN;
708 * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to
709 * let the step logic know that the IVDIG registers should be
710 * explicitly set before launching a TDMA chain.
712 basereq->chain.first->flags |= CESA_TDMA_SET_STATE;
718 mv_cesa_dma_cleanup(basereq);
719 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
722 mv_cesa_ahash_last_cleanup(req);
727 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
729 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
731 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
732 if (creq->src_nents < 0) {
733 dev_err(cesa_dev->dev, "Invalid number of src SG");
734 return creq->src_nents;
737 *cached = mv_cesa_ahash_cache_req(req);
742 if (cesa_dev->caps->has_tdma)
743 return mv_cesa_ahash_dma_req_init(req);
748 static int mv_cesa_ahash_queue_req(struct ahash_request *req)
750 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
751 struct mv_cesa_engine *engine;
755 ret = mv_cesa_ahash_req_init(req, &cached);
762 engine = mv_cesa_select_engine(req->nbytes);
763 mv_cesa_ahash_prepare(&req->base, engine);
765 ret = mv_cesa_queue_req(&req->base, &creq->base);
767 if (mv_cesa_req_needs_cleanup(&req->base, ret))
768 mv_cesa_ahash_cleanup(req);
773 static int mv_cesa_ahash_update(struct ahash_request *req)
775 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
777 creq->len += req->nbytes;
779 return mv_cesa_ahash_queue_req(req);
782 static int mv_cesa_ahash_final(struct ahash_request *req)
784 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
785 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
787 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
788 creq->last_req = true;
791 return mv_cesa_ahash_queue_req(req);
794 static int mv_cesa_ahash_finup(struct ahash_request *req)
796 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
797 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
799 creq->len += req->nbytes;
800 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
801 creq->last_req = true;
803 return mv_cesa_ahash_queue_req(req);
806 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
807 u64 *len, void *cache)
809 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
810 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
811 unsigned int digsize = crypto_ahash_digestsize(ahash);
812 unsigned int blocksize;
814 blocksize = crypto_ahash_blocksize(ahash);
817 memcpy(hash, creq->state, digsize);
818 memset(cache, 0, blocksize);
819 memcpy(cache, creq->cache, creq->cache_ptr);
824 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
825 u64 len, const void *cache)
827 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
828 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
829 unsigned int digsize = crypto_ahash_digestsize(ahash);
830 unsigned int blocksize;
831 unsigned int cache_ptr;
834 ret = crypto_ahash_init(req);
838 blocksize = crypto_ahash_blocksize(ahash);
839 if (len >= blocksize)
840 mv_cesa_update_op_cfg(&creq->op_tmpl,
841 CESA_SA_DESC_CFG_MID_FRAG,
842 CESA_SA_DESC_CFG_FRAG_MSK);
845 memcpy(creq->state, hash, digsize);
848 cache_ptr = do_div(len, blocksize);
852 memcpy(creq->cache, cache, cache_ptr);
853 creq->cache_ptr = cache_ptr;
858 static int mv_cesa_md5_init(struct ahash_request *req)
860 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
861 struct mv_cesa_op_ctx tmpl = { };
863 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
865 mv_cesa_ahash_init(req, &tmpl, true);
867 creq->state[0] = MD5_H0;
868 creq->state[1] = MD5_H1;
869 creq->state[2] = MD5_H2;
870 creq->state[3] = MD5_H3;
875 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
877 struct md5_state *out_state = out;
879 return mv_cesa_ahash_export(req, out_state->hash,
880 &out_state->byte_count, out_state->block);
883 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
885 const struct md5_state *in_state = in;
887 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
891 static int mv_cesa_md5_digest(struct ahash_request *req)
895 ret = mv_cesa_md5_init(req);
899 return mv_cesa_ahash_finup(req);
902 struct ahash_alg mv_md5_alg = {
903 .init = mv_cesa_md5_init,
904 .update = mv_cesa_ahash_update,
905 .final = mv_cesa_ahash_final,
906 .finup = mv_cesa_ahash_finup,
907 .digest = mv_cesa_md5_digest,
908 .export = mv_cesa_md5_export,
909 .import = mv_cesa_md5_import,
911 .digestsize = MD5_DIGEST_SIZE,
912 .statesize = sizeof(struct md5_state),
915 .cra_driver_name = "mv-md5",
917 .cra_flags = CRYPTO_ALG_ASYNC |
918 CRYPTO_ALG_KERN_DRIVER_ONLY,
919 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
920 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
921 .cra_init = mv_cesa_ahash_cra_init,
922 .cra_module = THIS_MODULE,
927 static int mv_cesa_sha1_init(struct ahash_request *req)
929 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
930 struct mv_cesa_op_ctx tmpl = { };
932 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
934 mv_cesa_ahash_init(req, &tmpl, false);
936 creq->state[0] = SHA1_H0;
937 creq->state[1] = SHA1_H1;
938 creq->state[2] = SHA1_H2;
939 creq->state[3] = SHA1_H3;
940 creq->state[4] = SHA1_H4;
945 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
947 struct sha1_state *out_state = out;
949 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
953 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
955 const struct sha1_state *in_state = in;
957 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
961 static int mv_cesa_sha1_digest(struct ahash_request *req)
965 ret = mv_cesa_sha1_init(req);
969 return mv_cesa_ahash_finup(req);
972 struct ahash_alg mv_sha1_alg = {
973 .init = mv_cesa_sha1_init,
974 .update = mv_cesa_ahash_update,
975 .final = mv_cesa_ahash_final,
976 .finup = mv_cesa_ahash_finup,
977 .digest = mv_cesa_sha1_digest,
978 .export = mv_cesa_sha1_export,
979 .import = mv_cesa_sha1_import,
981 .digestsize = SHA1_DIGEST_SIZE,
982 .statesize = sizeof(struct sha1_state),
985 .cra_driver_name = "mv-sha1",
987 .cra_flags = CRYPTO_ALG_ASYNC |
988 CRYPTO_ALG_KERN_DRIVER_ONLY,
989 .cra_blocksize = SHA1_BLOCK_SIZE,
990 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
991 .cra_init = mv_cesa_ahash_cra_init,
992 .cra_module = THIS_MODULE,
997 static int mv_cesa_sha256_init(struct ahash_request *req)
999 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
1000 struct mv_cesa_op_ctx tmpl = { };
1002 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
1004 mv_cesa_ahash_init(req, &tmpl, false);
1006 creq->state[0] = SHA256_H0;
1007 creq->state[1] = SHA256_H1;
1008 creq->state[2] = SHA256_H2;
1009 creq->state[3] = SHA256_H3;
1010 creq->state[4] = SHA256_H4;
1011 creq->state[5] = SHA256_H5;
1012 creq->state[6] = SHA256_H6;
1013 creq->state[7] = SHA256_H7;
1018 static int mv_cesa_sha256_digest(struct ahash_request *req)
1022 ret = mv_cesa_sha256_init(req);
1026 return mv_cesa_ahash_finup(req);
1029 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1031 struct sha256_state *out_state = out;
1033 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1037 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1039 const struct sha256_state *in_state = in;
1041 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1045 struct ahash_alg mv_sha256_alg = {
1046 .init = mv_cesa_sha256_init,
1047 .update = mv_cesa_ahash_update,
1048 .final = mv_cesa_ahash_final,
1049 .finup = mv_cesa_ahash_finup,
1050 .digest = mv_cesa_sha256_digest,
1051 .export = mv_cesa_sha256_export,
1052 .import = mv_cesa_sha256_import,
1054 .digestsize = SHA256_DIGEST_SIZE,
1055 .statesize = sizeof(struct sha256_state),
1057 .cra_name = "sha256",
1058 .cra_driver_name = "mv-sha256",
1059 .cra_priority = 300,
1060 .cra_flags = CRYPTO_ALG_ASYNC |
1061 CRYPTO_ALG_KERN_DRIVER_ONLY,
1062 .cra_blocksize = SHA256_BLOCK_SIZE,
1063 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1064 .cra_init = mv_cesa_ahash_cra_init,
1065 .cra_module = THIS_MODULE,
1070 struct mv_cesa_ahash_result {
1071 struct completion completion;
1075 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1078 struct mv_cesa_ahash_result *result = req->data;
1080 if (error == -EINPROGRESS)
1083 result->error = error;
1084 complete(&result->completion);
1087 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1088 void *state, unsigned int blocksize)
1090 struct mv_cesa_ahash_result result;
1091 struct scatterlist sg;
1094 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1095 mv_cesa_hmac_ahash_complete, &result);
1096 sg_init_one(&sg, pad, blocksize);
1097 ahash_request_set_crypt(req, &sg, pad, blocksize);
1098 init_completion(&result.completion);
1100 ret = crypto_ahash_init(req);
1104 ret = crypto_ahash_update(req);
1105 if (ret && ret != -EINPROGRESS)
1108 wait_for_completion_interruptible(&result.completion);
1110 return result.error;
1112 ret = crypto_ahash_export(req, state);
1119 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1120 const u8 *key, unsigned int keylen,
1122 unsigned int blocksize)
1124 struct mv_cesa_ahash_result result;
1125 struct scatterlist sg;
1129 if (keylen <= blocksize) {
1130 memcpy(ipad, key, keylen);
1132 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1137 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1138 mv_cesa_hmac_ahash_complete,
1140 sg_init_one(&sg, keydup, keylen);
1141 ahash_request_set_crypt(req, &sg, ipad, keylen);
1142 init_completion(&result.completion);
1144 ret = crypto_ahash_digest(req);
1145 if (ret == -EINPROGRESS) {
1146 wait_for_completion_interruptible(&result.completion);
1150 /* Set the memory region to 0 to avoid any leak. */
1156 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1159 memset(ipad + keylen, 0, blocksize - keylen);
1160 memcpy(opad, ipad, blocksize);
1162 for (i = 0; i < blocksize; i++) {
1163 ipad[i] ^= HMAC_IPAD_VALUE;
1164 opad[i] ^= HMAC_OPAD_VALUE;
1170 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1171 const u8 *key, unsigned int keylen,
1172 void *istate, void *ostate)
1174 struct ahash_request *req;
1175 struct crypto_ahash *tfm;
1176 unsigned int blocksize;
1181 tfm = crypto_alloc_ahash(hash_alg_name, 0, 0);
1183 return PTR_ERR(tfm);
1185 req = ahash_request_alloc(tfm, GFP_KERNEL);
1191 crypto_ahash_clear_flags(tfm, ~0);
1193 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1195 ipad = kcalloc(2, blocksize, GFP_KERNEL);
1201 opad = ipad + blocksize;
1203 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1207 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1211 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1216 ahash_request_free(req);
1218 crypto_free_ahash(tfm);
1223 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1225 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1227 ctx->base.ops = &mv_cesa_ahash_req_ops;
1229 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1230 sizeof(struct mv_cesa_ahash_req));
1234 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1236 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1237 struct mv_cesa_op_ctx tmpl = { };
1239 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1240 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1242 mv_cesa_ahash_init(req, &tmpl, true);
1247 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1248 unsigned int keylen)
1250 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1251 struct md5_state istate, ostate;
1254 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1258 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1259 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1261 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1262 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1267 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1271 ret = mv_cesa_ahmac_md5_init(req);
1275 return mv_cesa_ahash_finup(req);
1278 struct ahash_alg mv_ahmac_md5_alg = {
1279 .init = mv_cesa_ahmac_md5_init,
1280 .update = mv_cesa_ahash_update,
1281 .final = mv_cesa_ahash_final,
1282 .finup = mv_cesa_ahash_finup,
1283 .digest = mv_cesa_ahmac_md5_digest,
1284 .setkey = mv_cesa_ahmac_md5_setkey,
1285 .export = mv_cesa_md5_export,
1286 .import = mv_cesa_md5_import,
1288 .digestsize = MD5_DIGEST_SIZE,
1289 .statesize = sizeof(struct md5_state),
1291 .cra_name = "hmac(md5)",
1292 .cra_driver_name = "mv-hmac-md5",
1293 .cra_priority = 300,
1294 .cra_flags = CRYPTO_ALG_ASYNC |
1295 CRYPTO_ALG_KERN_DRIVER_ONLY,
1296 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1297 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1298 .cra_init = mv_cesa_ahmac_cra_init,
1299 .cra_module = THIS_MODULE,
1304 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1306 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1307 struct mv_cesa_op_ctx tmpl = { };
1309 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1310 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1312 mv_cesa_ahash_init(req, &tmpl, false);
1317 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1318 unsigned int keylen)
1320 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1321 struct sha1_state istate, ostate;
1324 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1328 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1329 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1331 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1332 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1337 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1341 ret = mv_cesa_ahmac_sha1_init(req);
1345 return mv_cesa_ahash_finup(req);
1348 struct ahash_alg mv_ahmac_sha1_alg = {
1349 .init = mv_cesa_ahmac_sha1_init,
1350 .update = mv_cesa_ahash_update,
1351 .final = mv_cesa_ahash_final,
1352 .finup = mv_cesa_ahash_finup,
1353 .digest = mv_cesa_ahmac_sha1_digest,
1354 .setkey = mv_cesa_ahmac_sha1_setkey,
1355 .export = mv_cesa_sha1_export,
1356 .import = mv_cesa_sha1_import,
1358 .digestsize = SHA1_DIGEST_SIZE,
1359 .statesize = sizeof(struct sha1_state),
1361 .cra_name = "hmac(sha1)",
1362 .cra_driver_name = "mv-hmac-sha1",
1363 .cra_priority = 300,
1364 .cra_flags = CRYPTO_ALG_ASYNC |
1365 CRYPTO_ALG_KERN_DRIVER_ONLY,
1366 .cra_blocksize = SHA1_BLOCK_SIZE,
1367 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1368 .cra_init = mv_cesa_ahmac_cra_init,
1369 .cra_module = THIS_MODULE,
1374 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1375 unsigned int keylen)
1377 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1378 struct sha256_state istate, ostate;
1381 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1385 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1386 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1388 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1389 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1394 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1396 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1397 struct mv_cesa_op_ctx tmpl = { };
1399 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1400 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1402 mv_cesa_ahash_init(req, &tmpl, false);
1407 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1411 ret = mv_cesa_ahmac_sha256_init(req);
1415 return mv_cesa_ahash_finup(req);
1418 struct ahash_alg mv_ahmac_sha256_alg = {
1419 .init = mv_cesa_ahmac_sha256_init,
1420 .update = mv_cesa_ahash_update,
1421 .final = mv_cesa_ahash_final,
1422 .finup = mv_cesa_ahash_finup,
1423 .digest = mv_cesa_ahmac_sha256_digest,
1424 .setkey = mv_cesa_ahmac_sha256_setkey,
1425 .export = mv_cesa_sha256_export,
1426 .import = mv_cesa_sha256_import,
1428 .digestsize = SHA256_DIGEST_SIZE,
1429 .statesize = sizeof(struct sha256_state),
1431 .cra_name = "hmac(sha256)",
1432 .cra_driver_name = "mv-hmac-sha256",
1433 .cra_priority = 300,
1434 .cra_flags = CRYPTO_ALG_ASYNC |
1435 CRYPTO_ALG_KERN_DRIVER_ONLY,
1436 .cra_blocksize = SHA256_BLOCK_SIZE,
1437 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1438 .cra_init = mv_cesa_ahmac_cra_init,
1439 .cra_module = THIS_MODULE,