1 // SPDX-License-Identifier: GPL-2.0-only
5 * Support for OMAP AES HW acceleration.
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
12 #define pr_fmt(fmt) "%20s: " fmt, __func__
13 #define prn(num) pr_debug(#num "=%d\n", num)
14 #define prx(num) pr_debug(#num "=%x\n", num)
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/kernel.h>
21 #include <linux/platform_device.h>
22 #include <linux/scatterlist.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_device.h>
28 #include <linux/of_address.h>
30 #include <linux/crypto.h>
31 #include <linux/interrupt.h>
32 #include <crypto/scatterwalk.h>
33 #include <crypto/aes.h>
34 #include <crypto/gcm.h>
35 #include <crypto/engine.h>
36 #include <crypto/internal/skcipher.h>
37 #include <crypto/internal/aead.h>
39 #include "omap-crypto.h"
42 /* keep registered devices data here */
43 static LIST_HEAD(dev_list);
44 static DEFINE_SPINLOCK(list_lock);
46 static int aes_fallback_sz = 200;
49 #define omap_aes_read(dd, offset) \
52 _read_ret = __raw_readl(dd->io_base + offset); \
53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
58 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
60 return __raw_readl(dd->io_base + offset);
65 #define omap_aes_write(dd, offset, value) \
67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
69 __raw_writel(value, dd->io_base + offset); \
72 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
75 __raw_writel(value, dd->io_base + offset);
79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
84 val = omap_aes_read(dd, offset);
87 omap_aes_write(dd, offset, val);
90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
91 u32 *value, int count)
93 for (; count--; value++, offset += 4)
94 omap_aes_write(dd, offset, *value);
97 static int omap_aes_hw_init(struct omap_aes_dev *dd)
101 if (!(dd->flags & FLAGS_INIT)) {
102 dd->flags |= FLAGS_INIT;
106 err = pm_runtime_get_sync(dd->dev);
108 dev_err(dd->dev, "failed to get sync: %d\n", err);
115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
122 int omap_aes_write_ctrl(struct omap_aes_dev *dd)
124 struct omap_aes_reqctx *rctx;
129 err = omap_aes_hw_init(dd);
133 key32 = dd->ctx->keylen / sizeof(u32);
135 /* RESET the key as previous HASH keys should not get affected*/
136 if (dd->flags & FLAGS_GCM)
137 for (i = 0; i < 0x40; i = i + 4)
138 omap_aes_write(dd, i, 0x0);
140 for (i = 0; i < key32; i++) {
141 omap_aes_write(dd, AES_REG_KEY(dd, i),
142 __le32_to_cpu(dd->ctx->key[i]));
145 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
146 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
148 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
149 rctx = aead_request_ctx(dd->aead_req);
150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
154 if (dd->flags & FLAGS_CBC)
155 val |= AES_REG_CTRL_CBC;
157 if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
158 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
160 if (dd->flags & FLAGS_GCM)
161 val |= AES_REG_CTRL_GCM;
163 if (dd->flags & FLAGS_ENCRYPT)
164 val |= AES_REG_CTRL_DIRECTION;
166 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
175 val = dd->pdata->dma_start;
177 if (dd->dma_lch_out != NULL)
178 val |= dd->pdata->dma_enable_out;
179 if (dd->dma_lch_in != NULL)
180 val |= dd->pdata->dma_enable_in;
182 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
183 dd->pdata->dma_start;
185 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
191 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
192 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
193 if (dd->flags & FLAGS_GCM)
194 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
196 omap_aes_dma_trigger_omap2(dd, length);
199 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
203 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
204 dd->pdata->dma_start;
206 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
211 struct omap_aes_dev *dd;
213 spin_lock_bh(&list_lock);
214 dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
215 list_move_tail(&dd->list, &dev_list);
217 spin_unlock_bh(&list_lock);
222 static void omap_aes_dma_out_callback(void *data)
224 struct omap_aes_dev *dd = data;
226 /* dma_lch_out - completed */
227 tasklet_schedule(&dd->done_task);
230 static int omap_aes_dma_init(struct omap_aes_dev *dd)
234 dd->dma_lch_out = NULL;
235 dd->dma_lch_in = NULL;
237 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
238 if (IS_ERR(dd->dma_lch_in)) {
239 dev_err(dd->dev, "Unable to request in DMA channel\n");
240 return PTR_ERR(dd->dma_lch_in);
243 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
244 if (IS_ERR(dd->dma_lch_out)) {
245 dev_err(dd->dev, "Unable to request out DMA channel\n");
246 err = PTR_ERR(dd->dma_lch_out);
253 dma_release_channel(dd->dma_lch_in);
258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
263 dma_release_channel(dd->dma_lch_out);
264 dma_release_channel(dd->dma_lch_in);
267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
268 struct scatterlist *in_sg,
269 struct scatterlist *out_sg,
270 int in_sg_len, int out_sg_len)
272 struct dma_async_tx_descriptor *tx_in, *tx_out;
273 struct dma_slave_config cfg;
277 scatterwalk_start(&dd->in_walk, dd->in_sg);
278 scatterwalk_start(&dd->out_walk, dd->out_sg);
280 /* Enable DATAIN interrupt and let it take
282 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
286 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
288 memset(&cfg, 0, sizeof(cfg));
290 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
291 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
292 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
293 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
294 cfg.src_maxburst = DST_MAXBURST;
295 cfg.dst_maxburst = DST_MAXBURST;
298 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
300 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
305 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
307 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
309 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
313 /* No callback necessary */
314 tx_in->callback_param = dd;
317 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
319 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
324 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
326 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
328 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
332 if (dd->flags & FLAGS_GCM)
333 tx_out->callback = omap_aes_gcm_dma_out_callback;
335 tx_out->callback = omap_aes_dma_out_callback;
336 tx_out->callback_param = dd;
338 dmaengine_submit(tx_in);
339 dmaengine_submit(tx_out);
341 dma_async_issue_pending(dd->dma_lch_in);
342 dma_async_issue_pending(dd->dma_lch_out);
345 dd->pdata->trigger(dd, dd->total);
350 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
354 pr_debug("total: %d\n", dd->total);
357 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
360 dev_err(dd->dev, "dma_map_sg() error\n");
364 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
367 dev_err(dd->dev, "dma_map_sg() error\n");
372 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
374 if (err && !dd->pio_only) {
375 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
376 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
383 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
385 struct ablkcipher_request *req = dd->req;
387 pr_debug("err: %d\n", err);
389 crypto_finalize_ablkcipher_request(dd->engine, req, err);
391 pm_runtime_mark_last_busy(dd->dev);
392 pm_runtime_put_autosuspend(dd->dev);
395 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
397 pr_debug("total: %d\n", dd->total);
399 omap_aes_dma_stop(dd);
405 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
406 struct ablkcipher_request *req)
409 return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
414 static int omap_aes_prepare_req(struct crypto_engine *engine,
417 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
418 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
419 crypto_ablkcipher_reqtfm(req));
420 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
421 struct omap_aes_dev *dd = rctx->dd;
428 /* assign new request to device */
430 dd->total = req->nbytes;
431 dd->total_save = req->nbytes;
432 dd->in_sg = req->src;
433 dd->out_sg = req->dst;
434 dd->orig_out = req->dst;
436 flags = OMAP_CRYPTO_COPY_DATA;
437 if (req->src == req->dst)
438 flags |= OMAP_CRYPTO_FORCE_COPY;
440 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
442 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
446 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
448 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
452 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
453 if (dd->in_sg_len < 0)
454 return dd->in_sg_len;
456 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
457 if (dd->out_sg_len < 0)
458 return dd->out_sg_len;
460 rctx->mode &= FLAGS_MODE_MASK;
461 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
466 return omap_aes_write_ctrl(dd);
469 static int omap_aes_crypt_req(struct crypto_engine *engine,
472 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
473 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
474 struct omap_aes_dev *dd = rctx->dd;
479 return omap_aes_crypt_dma_start(dd);
482 static void omap_aes_done_task(unsigned long data)
484 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
486 pr_debug("enter done_task\n");
489 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
491 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
492 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
494 omap_aes_crypt_dma_stop(dd);
497 omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save,
498 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
500 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
501 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
503 omap_aes_finish_req(dd, 0);
508 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
510 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
511 crypto_ablkcipher_reqtfm(req));
512 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
513 struct omap_aes_dev *dd;
516 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
517 !!(mode & FLAGS_ENCRYPT),
518 !!(mode & FLAGS_CBC));
520 if (req->nbytes < aes_fallback_sz) {
521 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
523 skcipher_request_set_sync_tfm(subreq, ctx->fallback);
524 skcipher_request_set_callback(subreq, req->base.flags, NULL,
526 skcipher_request_set_crypt(subreq, req->src, req->dst,
527 req->nbytes, req->info);
529 if (mode & FLAGS_ENCRYPT)
530 ret = crypto_skcipher_encrypt(subreq);
532 ret = crypto_skcipher_decrypt(subreq);
534 skcipher_request_zero(subreq);
537 dd = omap_aes_find_dev(rctx);
543 return omap_aes_handle_queue(dd, req);
546 /* ********************** ALG API ************************************ */
548 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
551 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
554 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
555 keylen != AES_KEYSIZE_256)
558 pr_debug("enter, keylen: %d\n", keylen);
560 memcpy(ctx->key, key, keylen);
561 ctx->keylen = keylen;
563 crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
564 crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
565 CRYPTO_TFM_REQ_MASK);
567 ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
574 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
576 return omap_aes_crypt(req, FLAGS_ENCRYPT);
579 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
581 return omap_aes_crypt(req, 0);
584 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
586 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
589 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
591 return omap_aes_crypt(req, FLAGS_CBC);
594 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
596 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
599 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
601 return omap_aes_crypt(req, FLAGS_CTR);
604 static int omap_aes_prepare_req(struct crypto_engine *engine,
606 static int omap_aes_crypt_req(struct crypto_engine *engine,
609 static int omap_aes_cra_init(struct crypto_tfm *tfm)
611 const char *name = crypto_tfm_alg_name(tfm);
612 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
613 struct crypto_sync_skcipher *blk;
615 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
621 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
623 ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
624 ctx->enginectx.op.unprepare_request = NULL;
625 ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
630 static int omap_aes_gcm_cra_init(struct crypto_aead *tfm)
632 struct omap_aes_dev *dd = NULL;
633 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
636 /* Find AES device, currently picks the first device */
637 spin_lock_bh(&list_lock);
638 list_for_each_entry(dd, &dev_list, list) {
641 spin_unlock_bh(&list_lock);
643 err = pm_runtime_get_sync(dd->dev);
645 dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
650 tfm->reqsize = sizeof(struct omap_aes_reqctx);
651 ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0);
652 if (IS_ERR(ctx->ctr)) {
653 pr_warn("could not load aes driver for encrypting IV\n");
654 return PTR_ERR(ctx->ctr);
660 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
662 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
665 crypto_free_sync_skcipher(ctx->fallback);
667 ctx->fallback = NULL;
670 static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm)
672 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
674 omap_aes_cra_exit(crypto_aead_tfm(tfm));
677 crypto_free_skcipher(ctx->ctr);
680 /* ********************** ALGS ************************************ */
682 static struct crypto_alg algs_ecb_cbc[] = {
684 .cra_name = "ecb(aes)",
685 .cra_driver_name = "ecb-aes-omap",
687 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
688 CRYPTO_ALG_KERN_DRIVER_ONLY |
689 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
690 .cra_blocksize = AES_BLOCK_SIZE,
691 .cra_ctxsize = sizeof(struct omap_aes_ctx),
693 .cra_type = &crypto_ablkcipher_type,
694 .cra_module = THIS_MODULE,
695 .cra_init = omap_aes_cra_init,
696 .cra_exit = omap_aes_cra_exit,
697 .cra_u.ablkcipher = {
698 .min_keysize = AES_MIN_KEY_SIZE,
699 .max_keysize = AES_MAX_KEY_SIZE,
700 .setkey = omap_aes_setkey,
701 .encrypt = omap_aes_ecb_encrypt,
702 .decrypt = omap_aes_ecb_decrypt,
706 .cra_name = "cbc(aes)",
707 .cra_driver_name = "cbc-aes-omap",
709 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
710 CRYPTO_ALG_KERN_DRIVER_ONLY |
711 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
712 .cra_blocksize = AES_BLOCK_SIZE,
713 .cra_ctxsize = sizeof(struct omap_aes_ctx),
715 .cra_type = &crypto_ablkcipher_type,
716 .cra_module = THIS_MODULE,
717 .cra_init = omap_aes_cra_init,
718 .cra_exit = omap_aes_cra_exit,
719 .cra_u.ablkcipher = {
720 .min_keysize = AES_MIN_KEY_SIZE,
721 .max_keysize = AES_MAX_KEY_SIZE,
722 .ivsize = AES_BLOCK_SIZE,
723 .setkey = omap_aes_setkey,
724 .encrypt = omap_aes_cbc_encrypt,
725 .decrypt = omap_aes_cbc_decrypt,
730 static struct crypto_alg algs_ctr[] = {
732 .cra_name = "ctr(aes)",
733 .cra_driver_name = "ctr-aes-omap",
735 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
736 CRYPTO_ALG_KERN_DRIVER_ONLY |
737 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
738 .cra_blocksize = AES_BLOCK_SIZE,
739 .cra_ctxsize = sizeof(struct omap_aes_ctx),
741 .cra_type = &crypto_ablkcipher_type,
742 .cra_module = THIS_MODULE,
743 .cra_init = omap_aes_cra_init,
744 .cra_exit = omap_aes_cra_exit,
745 .cra_u.ablkcipher = {
746 .min_keysize = AES_MIN_KEY_SIZE,
747 .max_keysize = AES_MAX_KEY_SIZE,
748 .ivsize = AES_BLOCK_SIZE,
749 .setkey = omap_aes_setkey,
750 .encrypt = omap_aes_ctr_encrypt,
751 .decrypt = omap_aes_ctr_decrypt,
756 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
758 .algs_list = algs_ecb_cbc,
759 .size = ARRAY_SIZE(algs_ecb_cbc),
763 static struct aead_alg algs_aead_gcm[] = {
766 .cra_name = "gcm(aes)",
767 .cra_driver_name = "gcm-aes-omap",
769 .cra_flags = CRYPTO_ALG_ASYNC |
770 CRYPTO_ALG_KERN_DRIVER_ONLY,
772 .cra_ctxsize = sizeof(struct omap_aes_ctx),
773 .cra_alignmask = 0xf,
774 .cra_module = THIS_MODULE,
776 .init = omap_aes_gcm_cra_init,
777 .exit = omap_aes_gcm_cra_exit,
778 .ivsize = GCM_AES_IV_SIZE,
779 .maxauthsize = AES_BLOCK_SIZE,
780 .setkey = omap_aes_gcm_setkey,
781 .encrypt = omap_aes_gcm_encrypt,
782 .decrypt = omap_aes_gcm_decrypt,
786 .cra_name = "rfc4106(gcm(aes))",
787 .cra_driver_name = "rfc4106-gcm-aes-omap",
789 .cra_flags = CRYPTO_ALG_ASYNC |
790 CRYPTO_ALG_KERN_DRIVER_ONLY,
792 .cra_ctxsize = sizeof(struct omap_aes_ctx),
793 .cra_alignmask = 0xf,
794 .cra_module = THIS_MODULE,
796 .init = omap_aes_gcm_cra_init,
797 .exit = omap_aes_gcm_cra_exit,
798 .maxauthsize = AES_BLOCK_SIZE,
799 .ivsize = GCM_RFC4106_IV_SIZE,
800 .setkey = omap_aes_4106gcm_setkey,
801 .encrypt = omap_aes_4106gcm_encrypt,
802 .decrypt = omap_aes_4106gcm_decrypt,
806 static struct omap_aes_aead_algs omap_aes_aead_info = {
807 .algs_list = algs_aead_gcm,
808 .size = ARRAY_SIZE(algs_aead_gcm),
811 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
812 .algs_info = omap_aes_algs_info_ecb_cbc,
813 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
814 .trigger = omap_aes_dma_trigger_omap2,
821 .dma_enable_in = BIT(2),
822 .dma_enable_out = BIT(3),
831 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
833 .algs_list = algs_ecb_cbc,
834 .size = ARRAY_SIZE(algs_ecb_cbc),
837 .algs_list = algs_ctr,
838 .size = ARRAY_SIZE(algs_ctr),
842 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
843 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
844 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
845 .trigger = omap_aes_dma_trigger_omap2,
852 .dma_enable_in = BIT(2),
853 .dma_enable_out = BIT(3),
861 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
862 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
863 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
864 .aead_algs_info = &omap_aes_aead_info,
865 .trigger = omap_aes_dma_trigger_omap4,
872 .irq_status_ofs = 0x8c,
873 .irq_enable_ofs = 0x90,
874 .dma_enable_in = BIT(5),
875 .dma_enable_out = BIT(6),
876 .major_mask = 0x0700,
878 .minor_mask = 0x003f,
882 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
884 struct omap_aes_dev *dd = dev_id;
888 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
889 if (status & AES_REG_IRQ_DATA_IN) {
890 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
894 BUG_ON(_calc_walked(in) > dd->in_sg->length);
896 src = sg_virt(dd->in_sg) + _calc_walked(in);
898 for (i = 0; i < AES_BLOCK_WORDS; i++) {
899 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
901 scatterwalk_advance(&dd->in_walk, 4);
902 if (dd->in_sg->length == _calc_walked(in)) {
903 dd->in_sg = sg_next(dd->in_sg);
905 scatterwalk_start(&dd->in_walk,
907 src = sg_virt(dd->in_sg) +
915 /* Clear IRQ status */
916 status &= ~AES_REG_IRQ_DATA_IN;
917 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
919 /* Enable DATA_OUT interrupt */
920 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
922 } else if (status & AES_REG_IRQ_DATA_OUT) {
923 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
927 BUG_ON(_calc_walked(out) > dd->out_sg->length);
929 dst = sg_virt(dd->out_sg) + _calc_walked(out);
931 for (i = 0; i < AES_BLOCK_WORDS; i++) {
932 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
933 scatterwalk_advance(&dd->out_walk, 4);
934 if (dd->out_sg->length == _calc_walked(out)) {
935 dd->out_sg = sg_next(dd->out_sg);
937 scatterwalk_start(&dd->out_walk,
939 dst = sg_virt(dd->out_sg) +
947 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
949 /* Clear IRQ status */
950 status &= ~AES_REG_IRQ_DATA_OUT;
951 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
954 /* All bytes read! */
955 tasklet_schedule(&dd->done_task);
957 /* Enable DATA_IN interrupt for next block */
958 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
964 static const struct of_device_id omap_aes_of_match[] = {
966 .compatible = "ti,omap2-aes",
967 .data = &omap_aes_pdata_omap2,
970 .compatible = "ti,omap3-aes",
971 .data = &omap_aes_pdata_omap3,
974 .compatible = "ti,omap4-aes",
975 .data = &omap_aes_pdata_omap4,
979 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
981 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
982 struct device *dev, struct resource *res)
984 struct device_node *node = dev->of_node;
987 dd->pdata = of_device_get_match_data(dev);
989 dev_err(dev, "no compatible OF match\n");
994 err = of_address_to_resource(node, 0, res);
996 dev_err(dev, "can't translate OF node address\n");
1005 static const struct of_device_id omap_aes_of_match[] = {
1009 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1010 struct device *dev, struct resource *res)
1016 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1017 struct platform_device *pdev, struct resource *res)
1019 struct device *dev = &pdev->dev;
1023 /* Get the base address */
1024 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026 dev_err(dev, "no MEM resource info\n");
1030 memcpy(res, r, sizeof(*res));
1032 /* Only OMAP2/3 can be non-DT */
1033 dd->pdata = &omap_aes_pdata_omap2;
1039 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1042 return sprintf(buf, "%d\n", aes_fallback_sz);
1045 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1046 const char *buf, size_t size)
1051 status = kstrtol(buf, 0, &value);
1055 /* HW accelerator only works with buffers > 9 */
1057 dev_err(dev, "minimum fallback size 9\n");
1061 aes_fallback_sz = value;
1066 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1069 struct omap_aes_dev *dd = dev_get_drvdata(dev);
1071 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1074 static ssize_t queue_len_store(struct device *dev,
1075 struct device_attribute *attr, const char *buf,
1078 struct omap_aes_dev *dd;
1081 unsigned long flags;
1083 status = kstrtol(buf, 0, &value);
1091 * Changing the queue size in fly is safe, if size becomes smaller
1092 * than current size, it will just not accept new entries until
1093 * it has shrank enough.
1095 spin_lock_bh(&list_lock);
1096 list_for_each_entry(dd, &dev_list, list) {
1097 spin_lock_irqsave(&dd->lock, flags);
1098 dd->engine->queue.max_qlen = value;
1099 dd->aead_queue.base.max_qlen = value;
1100 spin_unlock_irqrestore(&dd->lock, flags);
1102 spin_unlock_bh(&list_lock);
1107 static DEVICE_ATTR_RW(queue_len);
1108 static DEVICE_ATTR_RW(fallback);
1110 static struct attribute *omap_aes_attrs[] = {
1111 &dev_attr_queue_len.attr,
1112 &dev_attr_fallback.attr,
1116 static struct attribute_group omap_aes_attr_group = {
1117 .attrs = omap_aes_attrs,
1120 static int omap_aes_probe(struct platform_device *pdev)
1122 struct device *dev = &pdev->dev;
1123 struct omap_aes_dev *dd;
1124 struct crypto_alg *algp;
1125 struct aead_alg *aalg;
1126 struct resource res;
1127 int err = -ENOMEM, i, j, irq = -1;
1130 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1132 dev_err(dev, "unable to alloc data struct.\n");
1136 platform_set_drvdata(pdev, dd);
1138 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1140 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1141 omap_aes_get_res_pdev(dd, pdev, &res);
1145 dd->io_base = devm_ioremap_resource(dev, &res);
1146 if (IS_ERR(dd->io_base)) {
1147 err = PTR_ERR(dd->io_base);
1150 dd->phys_base = res.start;
1152 pm_runtime_use_autosuspend(dev);
1153 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1155 pm_runtime_enable(dev);
1156 err = pm_runtime_get_sync(dev);
1158 dev_err(dev, "%s: failed to get_sync(%d)\n",
1163 omap_aes_dma_stop(dd);
1165 reg = omap_aes_read(dd, AES_REG_REV(dd));
1167 pm_runtime_put_sync(dev);
1169 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1170 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1171 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1173 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1175 err = omap_aes_dma_init(dd);
1176 if (err == -EPROBE_DEFER) {
1178 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1181 irq = platform_get_irq(pdev, 0);
1187 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1190 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1195 spin_lock_init(&dd->lock);
1197 INIT_LIST_HEAD(&dd->list);
1198 spin_lock(&list_lock);
1199 list_add_tail(&dd->list, &dev_list);
1200 spin_unlock(&list_lock);
1202 /* Initialize crypto engine */
1203 dd->engine = crypto_engine_alloc_init(dev, 1);
1209 err = crypto_engine_start(dd->engine);
1213 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1214 if (!dd->pdata->algs_info[i].registered) {
1215 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1216 algp = &dd->pdata->algs_info[i].algs_list[j];
1218 pr_debug("reg alg: %s\n", algp->cra_name);
1220 err = crypto_register_alg(algp);
1224 dd->pdata->algs_info[i].registered++;
1229 if (dd->pdata->aead_algs_info &&
1230 !dd->pdata->aead_algs_info->registered) {
1231 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1232 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1235 pr_debug("reg alg: %s\n", algp->cra_name);
1237 err = crypto_register_aead(aalg);
1241 dd->pdata->aead_algs_info->registered++;
1245 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1247 dev_err(dev, "could not create sysfs device attrs\n");
1253 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1254 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1255 crypto_unregister_aead(aalg);
1258 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1259 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1260 crypto_unregister_alg(
1261 &dd->pdata->algs_info[i].algs_list[j]);
1265 crypto_engine_exit(dd->engine);
1267 omap_aes_dma_cleanup(dd);
1269 tasklet_kill(&dd->done_task);
1270 pm_runtime_disable(dev);
1274 dev_err(dev, "initialization failed.\n");
1278 static int omap_aes_remove(struct platform_device *pdev)
1280 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1281 struct aead_alg *aalg;
1287 spin_lock(&list_lock);
1288 list_del(&dd->list);
1289 spin_unlock(&list_lock);
1291 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1292 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1293 crypto_unregister_alg(
1294 &dd->pdata->algs_info[i].algs_list[j]);
1296 for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) {
1297 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1298 crypto_unregister_aead(aalg);
1301 crypto_engine_exit(dd->engine);
1303 tasklet_kill(&dd->done_task);
1304 omap_aes_dma_cleanup(dd);
1305 pm_runtime_disable(dd->dev);
1311 #ifdef CONFIG_PM_SLEEP
1312 static int omap_aes_suspend(struct device *dev)
1314 pm_runtime_put_sync(dev);
1318 static int omap_aes_resume(struct device *dev)
1320 pm_runtime_get_sync(dev);
1325 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1327 static struct platform_driver omap_aes_driver = {
1328 .probe = omap_aes_probe,
1329 .remove = omap_aes_remove,
1332 .pm = &omap_aes_pm_ops,
1333 .of_match_table = omap_aes_of_match,
1337 module_platform_driver(omap_aes_driver);
1339 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1340 MODULE_LICENSE("GPL v2");
1341 MODULE_AUTHOR("Dmitry Kasatkin");