1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for OMAP DES and Triple DES HW acceleration.
5 * Copyright (c) 2013 Texas Instruments Incorporated
6 * Author: Joel Fernandes <joelf@ti.com>
9 #define pr_fmt(fmt) "%s: " fmt, __func__
12 #define prn(num) printk(#num "=%d\n", num)
13 #define prx(num) printk(#num "=%x\n", num)
15 #define prn(num) do { } while (0)
16 #define prx(num) do { } while (0)
19 #include <linux/err.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/pm_runtime.h>
30 #include <linux/of_device.h>
31 #include <linux/of_address.h>
33 #include <linux/crypto.h>
34 #include <linux/interrupt.h>
35 #include <crypto/scatterwalk.h>
36 #include <crypto/internal/des.h>
37 #include <crypto/internal/skcipher.h>
38 #include <crypto/algapi.h>
39 #include <crypto/engine.h>
41 #include "omap-crypto.h"
43 #define DST_MAXBURST 2
45 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
47 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
49 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
52 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
54 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55 #define DES_REG_CTRL_CBC BIT(4)
56 #define DES_REG_CTRL_TDES BIT(3)
57 #define DES_REG_CTRL_DIRECTION BIT(2)
58 #define DES_REG_CTRL_INPUT_READY BIT(1)
59 #define DES_REG_CTRL_OUTPUT_READY BIT(0)
61 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
63 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
65 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
67 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
69 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71 #define DES_REG_IRQ_DATA_IN BIT(1)
72 #define DES_REG_IRQ_DATA_OUT BIT(2)
74 #define FLAGS_MODE_MASK 0x000f
75 #define FLAGS_ENCRYPT BIT(0)
76 #define FLAGS_CBC BIT(1)
77 #define FLAGS_INIT BIT(4)
78 #define FLAGS_BUSY BIT(6)
80 #define DEFAULT_AUTOSUSPEND_DELAY 1000
82 #define FLAGS_IN_DATA_ST_SHIFT 8
83 #define FLAGS_OUT_DATA_ST_SHIFT 10
86 struct crypto_engine_ctx enginectx;
87 struct omap_des_dev *dd;
90 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
94 struct omap_des_reqctx {
98 #define OMAP_DES_QUEUE_LENGTH 1
99 #define OMAP_DES_CACHE_SIZE 0
101 struct omap_des_algs_info {
102 struct skcipher_alg *algs_list;
104 unsigned int registered;
107 struct omap_des_pdata {
108 struct omap_des_algs_info *algs_info;
109 unsigned int algs_info_size;
111 void (*trigger)(struct omap_des_dev *dd, int length);
132 struct omap_des_dev {
133 struct list_head list;
134 unsigned long phys_base;
135 void __iomem *io_base;
136 struct omap_des_ctx *ctx;
141 struct tasklet_struct done_task;
143 struct skcipher_request *req;
144 struct crypto_engine *engine;
146 * total is used by PIO mode for book keeping so introduce
147 * variable total_save as need it to calc page_order
152 struct scatterlist *in_sg;
153 struct scatterlist *out_sg;
155 /* Buffers for copying for unaligned cases */
156 struct scatterlist in_sgl;
157 struct scatterlist out_sgl;
158 struct scatterlist *orig_out;
160 struct scatter_walk in_walk;
161 struct scatter_walk out_walk;
162 struct dma_chan *dma_lch_in;
163 struct dma_chan *dma_lch_out;
167 const struct omap_des_pdata *pdata;
170 /* keep registered devices data here */
171 static LIST_HEAD(dev_list);
172 static DEFINE_SPINLOCK(list_lock);
175 #define omap_des_read(dd, offset) \
178 _read_ret = __raw_readl(dd->io_base + offset); \
179 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
180 offset, _read_ret); \
184 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
186 return __raw_readl(dd->io_base + offset);
191 #define omap_des_write(dd, offset, value) \
193 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
195 __raw_writel(value, dd->io_base + offset); \
198 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
201 __raw_writel(value, dd->io_base + offset);
205 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
210 val = omap_des_read(dd, offset);
213 omap_des_write(dd, offset, val);
216 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
217 u32 *value, int count)
219 for (; count--; value++, offset += 4)
220 omap_des_write(dd, offset, *value);
223 static int omap_des_hw_init(struct omap_des_dev *dd)
228 * clocks are enabled when request starts and disabled when finished.
229 * It may be long delays between requests.
230 * Device might go to off mode to save power.
232 err = pm_runtime_get_sync(dd->dev);
234 pm_runtime_put_noidle(dd->dev);
235 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
239 if (!(dd->flags & FLAGS_INIT)) {
240 dd->flags |= FLAGS_INIT;
247 static int omap_des_write_ctrl(struct omap_des_dev *dd)
251 u32 val = 0, mask = 0;
253 err = omap_des_hw_init(dd);
257 key32 = dd->ctx->keylen / sizeof(u32);
259 /* it seems a key should always be set even if it has not changed */
260 for (i = 0; i < key32; i++) {
261 omap_des_write(dd, DES_REG_KEY(dd, i),
262 __le32_to_cpu(dd->ctx->key[i]));
265 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
266 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
268 if (dd->flags & FLAGS_CBC)
269 val |= DES_REG_CTRL_CBC;
270 if (dd->flags & FLAGS_ENCRYPT)
271 val |= DES_REG_CTRL_DIRECTION;
273 val |= DES_REG_CTRL_TDES;
275 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
277 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
282 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
286 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
288 val = dd->pdata->dma_start;
290 if (dd->dma_lch_out != NULL)
291 val |= dd->pdata->dma_enable_out;
292 if (dd->dma_lch_in != NULL)
293 val |= dd->pdata->dma_enable_in;
295 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
296 dd->pdata->dma_start;
298 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
301 static void omap_des_dma_stop(struct omap_des_dev *dd)
305 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
306 dd->pdata->dma_start;
308 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
311 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
313 struct omap_des_dev *dd = NULL, *tmp;
315 spin_lock_bh(&list_lock);
317 list_for_each_entry(tmp, &dev_list, list) {
318 /* FIXME: take fist available des core */
324 /* already found before */
327 spin_unlock_bh(&list_lock);
332 static void omap_des_dma_out_callback(void *data)
334 struct omap_des_dev *dd = data;
336 /* dma_lch_out - completed */
337 tasklet_schedule(&dd->done_task);
340 static int omap_des_dma_init(struct omap_des_dev *dd)
344 dd->dma_lch_out = NULL;
345 dd->dma_lch_in = NULL;
347 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
348 if (IS_ERR(dd->dma_lch_in)) {
349 dev_err(dd->dev, "Unable to request in DMA channel\n");
350 return PTR_ERR(dd->dma_lch_in);
353 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
354 if (IS_ERR(dd->dma_lch_out)) {
355 dev_err(dd->dev, "Unable to request out DMA channel\n");
356 err = PTR_ERR(dd->dma_lch_out);
363 dma_release_channel(dd->dma_lch_in);
368 static void omap_des_dma_cleanup(struct omap_des_dev *dd)
373 dma_release_channel(dd->dma_lch_out);
374 dma_release_channel(dd->dma_lch_in);
377 static int omap_des_crypt_dma(struct crypto_tfm *tfm,
378 struct scatterlist *in_sg, struct scatterlist *out_sg,
379 int in_sg_len, int out_sg_len)
381 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
382 struct omap_des_dev *dd = ctx->dd;
383 struct dma_async_tx_descriptor *tx_in, *tx_out;
384 struct dma_slave_config cfg;
388 scatterwalk_start(&dd->in_walk, dd->in_sg);
389 scatterwalk_start(&dd->out_walk, dd->out_sg);
391 /* Enable DATAIN interrupt and let it take
393 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
397 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
399 memset(&cfg, 0, sizeof(cfg));
401 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
402 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
403 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
404 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
405 cfg.src_maxburst = DST_MAXBURST;
406 cfg.dst_maxburst = DST_MAXBURST;
409 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
411 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
416 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
420 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
424 /* No callback necessary */
425 tx_in->callback_param = dd;
428 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
430 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
435 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
437 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
439 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
443 tx_out->callback = omap_des_dma_out_callback;
444 tx_out->callback_param = dd;
446 dmaengine_submit(tx_in);
447 dmaengine_submit(tx_out);
449 dma_async_issue_pending(dd->dma_lch_in);
450 dma_async_issue_pending(dd->dma_lch_out);
453 dd->pdata->trigger(dd, dd->total);
458 static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
460 struct crypto_tfm *tfm = crypto_skcipher_tfm(
461 crypto_skcipher_reqtfm(dd->req));
464 pr_debug("total: %d\n", dd->total);
467 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
470 dev_err(dd->dev, "dma_map_sg() error\n");
474 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
477 dev_err(dd->dev, "dma_map_sg() error\n");
482 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
484 if (err && !dd->pio_only) {
485 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
486 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
493 static void omap_des_finish_req(struct omap_des_dev *dd, int err)
495 struct skcipher_request *req = dd->req;
497 pr_debug("err: %d\n", err);
499 crypto_finalize_skcipher_request(dd->engine, req, err);
501 pm_runtime_mark_last_busy(dd->dev);
502 pm_runtime_put_autosuspend(dd->dev);
505 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
507 pr_debug("total: %d\n", dd->total);
509 omap_des_dma_stop(dd);
511 dmaengine_terminate_all(dd->dma_lch_in);
512 dmaengine_terminate_all(dd->dma_lch_out);
517 static int omap_des_handle_queue(struct omap_des_dev *dd,
518 struct skcipher_request *req)
521 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
526 static int omap_des_prepare_req(struct crypto_engine *engine,
529 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
530 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
531 crypto_skcipher_reqtfm(req));
532 struct omap_des_dev *dd = omap_des_find_dev(ctx);
533 struct omap_des_reqctx *rctx;
540 /* assign new request to device */
542 dd->total = req->cryptlen;
543 dd->total_save = req->cryptlen;
544 dd->in_sg = req->src;
545 dd->out_sg = req->dst;
546 dd->orig_out = req->dst;
548 flags = OMAP_CRYPTO_COPY_DATA;
549 if (req->src == req->dst)
550 flags |= OMAP_CRYPTO_FORCE_COPY;
552 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
554 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
558 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
560 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
564 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
565 if (dd->in_sg_len < 0)
566 return dd->in_sg_len;
568 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
569 if (dd->out_sg_len < 0)
570 return dd->out_sg_len;
572 rctx = skcipher_request_ctx(req);
573 ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
574 rctx->mode &= FLAGS_MODE_MASK;
575 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
580 return omap_des_write_ctrl(dd);
583 static int omap_des_crypt_req(struct crypto_engine *engine,
586 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
587 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
588 crypto_skcipher_reqtfm(req));
589 struct omap_des_dev *dd = omap_des_find_dev(ctx);
594 return omap_des_crypt_dma_start(dd);
597 static void omap_des_done_task(unsigned long data)
599 struct omap_des_dev *dd = (struct omap_des_dev *)data;
601 pr_debug("enter done_task\n");
604 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
606 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
607 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
609 omap_des_crypt_dma_stop(dd);
612 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
613 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
615 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
616 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
618 omap_des_finish_req(dd, 0);
623 static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
625 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
626 crypto_skcipher_reqtfm(req));
627 struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
628 struct omap_des_dev *dd;
630 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
631 !!(mode & FLAGS_ENCRYPT),
632 !!(mode & FLAGS_CBC));
634 if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE)) {
635 pr_err("request size is not exact amount of DES blocks\n");
639 dd = omap_des_find_dev(ctx);
645 return omap_des_handle_queue(dd, req);
648 /* ********************** ALG API ************************************ */
650 static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
653 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
656 pr_debug("enter, keylen: %d\n", keylen);
658 err = verify_skcipher_des_key(cipher, key);
662 memcpy(ctx->key, key, keylen);
663 ctx->keylen = keylen;
668 static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
671 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
674 pr_debug("enter, keylen: %d\n", keylen);
676 err = verify_skcipher_des3_key(cipher, key);
680 memcpy(ctx->key, key, keylen);
681 ctx->keylen = keylen;
686 static int omap_des_ecb_encrypt(struct skcipher_request *req)
688 return omap_des_crypt(req, FLAGS_ENCRYPT);
691 static int omap_des_ecb_decrypt(struct skcipher_request *req)
693 return omap_des_crypt(req, 0);
696 static int omap_des_cbc_encrypt(struct skcipher_request *req)
698 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
701 static int omap_des_cbc_decrypt(struct skcipher_request *req)
703 return omap_des_crypt(req, FLAGS_CBC);
706 static int omap_des_prepare_req(struct crypto_engine *engine,
708 static int omap_des_crypt_req(struct crypto_engine *engine,
711 static int omap_des_init_tfm(struct crypto_skcipher *tfm)
713 struct omap_des_ctx *ctx = crypto_skcipher_ctx(tfm);
717 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
719 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
720 ctx->enginectx.op.unprepare_request = NULL;
721 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
726 /* ********************** ALGS ************************************ */
728 static struct skcipher_alg algs_ecb_cbc[] = {
730 .base.cra_name = "ecb(des)",
731 .base.cra_driver_name = "ecb-des-omap",
732 .base.cra_priority = 100,
733 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
735 .base.cra_blocksize = DES_BLOCK_SIZE,
736 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
737 .base.cra_module = THIS_MODULE,
739 .min_keysize = DES_KEY_SIZE,
740 .max_keysize = DES_KEY_SIZE,
741 .setkey = omap_des_setkey,
742 .encrypt = omap_des_ecb_encrypt,
743 .decrypt = omap_des_ecb_decrypt,
744 .init = omap_des_init_tfm,
747 .base.cra_name = "cbc(des)",
748 .base.cra_driver_name = "cbc-des-omap",
749 .base.cra_priority = 100,
750 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
752 .base.cra_blocksize = DES_BLOCK_SIZE,
753 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
754 .base.cra_module = THIS_MODULE,
756 .min_keysize = DES_KEY_SIZE,
757 .max_keysize = DES_KEY_SIZE,
758 .ivsize = DES_BLOCK_SIZE,
759 .setkey = omap_des_setkey,
760 .encrypt = omap_des_cbc_encrypt,
761 .decrypt = omap_des_cbc_decrypt,
762 .init = omap_des_init_tfm,
765 .base.cra_name = "ecb(des3_ede)",
766 .base.cra_driver_name = "ecb-des3-omap",
767 .base.cra_priority = 100,
768 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
770 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
771 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
772 .base.cra_module = THIS_MODULE,
774 .min_keysize = DES3_EDE_KEY_SIZE,
775 .max_keysize = DES3_EDE_KEY_SIZE,
776 .setkey = omap_des3_setkey,
777 .encrypt = omap_des_ecb_encrypt,
778 .decrypt = omap_des_ecb_decrypt,
779 .init = omap_des_init_tfm,
782 .base.cra_name = "cbc(des3_ede)",
783 .base.cra_driver_name = "cbc-des3-omap",
784 .base.cra_priority = 100,
785 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
787 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
788 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
789 .base.cra_module = THIS_MODULE,
791 .min_keysize = DES3_EDE_KEY_SIZE,
792 .max_keysize = DES3_EDE_KEY_SIZE,
793 .ivsize = DES3_EDE_BLOCK_SIZE,
794 .setkey = omap_des3_setkey,
795 .encrypt = omap_des_cbc_encrypt,
796 .decrypt = omap_des_cbc_decrypt,
797 .init = omap_des_init_tfm,
801 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
803 .algs_list = algs_ecb_cbc,
804 .size = ARRAY_SIZE(algs_ecb_cbc),
809 static const struct omap_des_pdata omap_des_pdata_omap4 = {
810 .algs_info = omap_des_algs_info_ecb_cbc,
811 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
812 .trigger = omap_des_dma_trigger_omap4,
819 .irq_status_ofs = 0x3c,
820 .irq_enable_ofs = 0x40,
821 .dma_enable_in = BIT(5),
822 .dma_enable_out = BIT(6),
823 .major_mask = 0x0700,
825 .minor_mask = 0x003f,
829 static irqreturn_t omap_des_irq(int irq, void *dev_id)
831 struct omap_des_dev *dd = dev_id;
835 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
836 if (status & DES_REG_IRQ_DATA_IN) {
837 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
841 BUG_ON(_calc_walked(in) > dd->in_sg->length);
843 src = sg_virt(dd->in_sg) + _calc_walked(in);
845 for (i = 0; i < DES_BLOCK_WORDS; i++) {
846 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
848 scatterwalk_advance(&dd->in_walk, 4);
849 if (dd->in_sg->length == _calc_walked(in)) {
850 dd->in_sg = sg_next(dd->in_sg);
852 scatterwalk_start(&dd->in_walk,
854 src = sg_virt(dd->in_sg) +
862 /* Clear IRQ status */
863 status &= ~DES_REG_IRQ_DATA_IN;
864 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
866 /* Enable DATA_OUT interrupt */
867 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
869 } else if (status & DES_REG_IRQ_DATA_OUT) {
870 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
874 BUG_ON(_calc_walked(out) > dd->out_sg->length);
876 dst = sg_virt(dd->out_sg) + _calc_walked(out);
878 for (i = 0; i < DES_BLOCK_WORDS; i++) {
879 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
880 scatterwalk_advance(&dd->out_walk, 4);
881 if (dd->out_sg->length == _calc_walked(out)) {
882 dd->out_sg = sg_next(dd->out_sg);
884 scatterwalk_start(&dd->out_walk,
886 dst = sg_virt(dd->out_sg) +
894 BUG_ON(dd->total < DES_BLOCK_SIZE);
896 dd->total -= DES_BLOCK_SIZE;
898 /* Clear IRQ status */
899 status &= ~DES_REG_IRQ_DATA_OUT;
900 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
903 /* All bytes read! */
904 tasklet_schedule(&dd->done_task);
906 /* Enable DATA_IN interrupt for next block */
907 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
913 static const struct of_device_id omap_des_of_match[] = {
915 .compatible = "ti,omap4-des",
916 .data = &omap_des_pdata_omap4,
920 MODULE_DEVICE_TABLE(of, omap_des_of_match);
922 static int omap_des_get_of(struct omap_des_dev *dd,
923 struct platform_device *pdev)
926 dd->pdata = of_device_get_match_data(&pdev->dev);
928 dev_err(&pdev->dev, "no compatible OF match\n");
935 static int omap_des_get_of(struct omap_des_dev *dd,
942 static int omap_des_get_pdev(struct omap_des_dev *dd,
943 struct platform_device *pdev)
945 /* non-DT devices get pdata from pdev */
946 dd->pdata = pdev->dev.platform_data;
951 static int omap_des_probe(struct platform_device *pdev)
953 struct device *dev = &pdev->dev;
954 struct omap_des_dev *dd;
955 struct skcipher_alg *algp;
956 struct resource *res;
957 int err = -ENOMEM, i, j, irq = -1;
960 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
962 dev_err(dev, "unable to alloc data struct.\n");
966 platform_set_drvdata(pdev, dd);
968 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
970 dev_err(dev, "no MEM resource info\n");
974 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
975 omap_des_get_pdev(dd, pdev);
979 dd->io_base = devm_ioremap_resource(dev, res);
980 if (IS_ERR(dd->io_base)) {
981 err = PTR_ERR(dd->io_base);
984 dd->phys_base = res->start;
986 pm_runtime_use_autosuspend(dev);
987 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
989 pm_runtime_enable(dev);
990 err = pm_runtime_get_sync(dev);
992 pm_runtime_put_noidle(dev);
993 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
997 omap_des_dma_stop(dd);
999 reg = omap_des_read(dd, DES_REG_REV(dd));
1001 pm_runtime_put_sync(dev);
1003 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1004 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1005 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1007 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1009 err = omap_des_dma_init(dd);
1010 if (err == -EPROBE_DEFER) {
1012 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1015 irq = platform_get_irq(pdev, 0);
1021 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1024 dev_err(dev, "Unable to grab omap-des IRQ\n");
1030 INIT_LIST_HEAD(&dd->list);
1031 spin_lock(&list_lock);
1032 list_add_tail(&dd->list, &dev_list);
1033 spin_unlock(&list_lock);
1035 /* Initialize des crypto engine */
1036 dd->engine = crypto_engine_alloc_init(dev, 1);
1042 err = crypto_engine_start(dd->engine);
1046 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1047 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1048 algp = &dd->pdata->algs_info[i].algs_list[j];
1050 pr_debug("reg alg: %s\n", algp->base.cra_name);
1052 err = crypto_register_skcipher(algp);
1056 dd->pdata->algs_info[i].registered++;
1063 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1064 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1065 crypto_unregister_skcipher(
1066 &dd->pdata->algs_info[i].algs_list[j]);
1070 crypto_engine_exit(dd->engine);
1072 omap_des_dma_cleanup(dd);
1074 tasklet_kill(&dd->done_task);
1076 pm_runtime_disable(dev);
1080 dev_err(dev, "initialization failed.\n");
1084 static int omap_des_remove(struct platform_device *pdev)
1086 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1092 spin_lock(&list_lock);
1093 list_del(&dd->list);
1094 spin_unlock(&list_lock);
1096 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1097 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1098 crypto_unregister_skcipher(
1099 &dd->pdata->algs_info[i].algs_list[j]);
1101 tasklet_kill(&dd->done_task);
1102 omap_des_dma_cleanup(dd);
1103 pm_runtime_disable(dd->dev);
1109 #ifdef CONFIG_PM_SLEEP
1110 static int omap_des_suspend(struct device *dev)
1112 pm_runtime_put_sync(dev);
1116 static int omap_des_resume(struct device *dev)
1120 err = pm_runtime_get_sync(dev);
1122 pm_runtime_put_noidle(dev);
1123 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1130 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1132 static struct platform_driver omap_des_driver = {
1133 .probe = omap_des_probe,
1134 .remove = omap_des_remove,
1137 .pm = &omap_des_pm_ops,
1138 .of_match_table = of_match_ptr(omap_des_of_match),
1142 module_platform_driver(omap_des_driver);
1144 MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1145 MODULE_LICENSE("GPL v2");
1146 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");