drivers/devfreq/rk3399_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/arm-smccc.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/devfreq.h>
  19 #include <linux/devfreq-event.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_opp.h>
  26 #include <linux/regmap.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/rwsem.h>
  29 #include <linux/suspend.h>
  30
  31 #include <soc/rockchip/rk3399_grf.h>
  32 #include <soc/rockchip/rockchip_sip.h>
  33
  34 struct dram_timing {
  35         unsigned int ddr3_speed_bin;
  36         unsigned int pd_idle;
  37         unsigned int sr_idle;
  38         unsigned int sr_mc_gate_idle;
  39         unsigned int srpd_lite_idle;
  40         unsigned int standby_idle;
  41         unsigned int auto_pd_dis_freq;
  42         unsigned int dram_dll_dis_freq;
  43         unsigned int phy_dll_dis_freq;
  44         unsigned int ddr3_odt_dis_freq;
  45         unsigned int ddr3_drv;
  46         unsigned int ddr3_odt;
  47         unsigned int phy_ddr3_ca_drv;
  48         unsigned int phy_ddr3_dq_drv;
  49         unsigned int phy_ddr3_odt;
  50         unsigned int lpddr3_odt_dis_freq;
  51         unsigned int lpddr3_drv;
  52         unsigned int lpddr3_odt;
  53         unsigned int phy_lpddr3_ca_drv;
  54         unsigned int phy_lpddr3_dq_drv;
  55         unsigned int phy_lpddr3_odt;
  56         unsigned int lpddr4_odt_dis_freq;
  57         unsigned int lpddr4_drv;
  58         unsigned int lpddr4_dq_odt;
  59         unsigned int lpddr4_ca_odt;
  60         unsigned int phy_lpddr4_ca_drv;
  61         unsigned int phy_lpddr4_ck_cs_drv;
  62         unsigned int phy_lpddr4_dq_drv;
  63         unsigned int phy_lpddr4_odt;
  64 };
  65
  66 struct rk3399_dmcfreq {
  67         struct device *dev;
  68         struct devfreq *devfreq;
  69         struct devfreq_simple_ondemand_data ondemand_data;
  70         struct clk *dmc_clk;
  71         struct devfreq_event_dev *edev;
  72         struct mutex lock;
  73         struct dram_timing timing;
  74         struct regulator *vdd_center;
  75         struct regmap *regmap_pmu;
  76         unsigned long rate, target_rate;
  77         unsigned long volt, target_volt;
  78         unsigned int odt_dis_freq;
  79         int odt_pd_arg0, odt_pd_arg1;
  80 };
  81
  82 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
  83                                  u32 flags)
  84 {
  85         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  86         struct dev_pm_opp *opp;
  87         unsigned long old_clk_rate = dmcfreq->rate;
  88         unsigned long target_volt, target_rate;
  89         struct arm_smccc_res res;
  90         bool odt_enable = false;
  91         int err;
  92
  93         opp = devfreq_recommended_opp(dev, freq, flags);
  94         if (IS_ERR(opp))
  95                 return PTR_ERR(opp);
  96
  97         target_rate = dev_pm_opp_get_freq(opp);
  98         target_volt = dev_pm_opp_get_voltage(opp);
  99         dev_pm_opp_put(opp);
 100
 101         if (dmcfreq->rate == target_rate)
 102                 return 0;
 103
 104         mutex_lock(&dmcfreq->lock);
 105
 106         if (target_rate >= dmcfreq->odt_dis_freq)
 107                 odt_enable = true;
 108
 109         /*
 110          * This makes a SMC call to the TF-A to set the DDR PD (power-down)
 111          * timings and to enable or disable the ODT (on-die termination)
 112          * resistors.
 113          */
 114         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
 115                       dmcfreq->odt_pd_arg1,
 116                       ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
 117                       odt_enable, 0, 0, 0, &res);
 118
 119         /*
 120          * If frequency scaling from low to high, adjust voltage first.
 121          * If frequency scaling from high to low, adjust frequency first.
 122          */
 123         if (old_clk_rate < target_rate) {
 124                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 125                                             target_volt);
 126                 if (err) {
 127                         dev_err(dev, "Cannot set voltage %lu uV\n",
 128                                 target_volt);
 129                         goto out;
 130                 }
 131         }
 132
 133         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 134         if (err) {
 135                 dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
 136                         err);
 137                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 138                                       dmcfreq->volt);
 139                 goto out;
 140         }
 141
 142         /*
 143          * Check the dpll rate,
 144          * There only two result we will get,
 145          * 1. Ddr frequency scaling fail, we still get the old rate.
 146          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 147          */
 148         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 149
 150         /* If get the incorrect rate, set voltage to old value. */
 151         if (dmcfreq->rate != target_rate) {
 152                 dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
 153                         target_rate, dmcfreq->rate);
 154                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 155                                       dmcfreq->volt);
 156                 goto out;
 157         } else if (old_clk_rate > target_rate)
 158                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 159                                             target_volt);
 160         if (err)
 161                 dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
 162
 163         dmcfreq->rate = target_rate;
 164         dmcfreq->volt = target_volt;
 165
 166 out:
 167         mutex_unlock(&dmcfreq->lock);
 168         return err;
 169 }
 170
 171 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
 172                                          struct devfreq_dev_status *stat)
 173 {
 174         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 175         struct devfreq_event_data edata;
 176         int ret = 0;
 177
 178         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 179         if (ret < 0)
 180                 return ret;
 181
 182         stat->current_frequency = dmcfreq->rate;
 183         stat->busy_time = edata.load_count;
 184         stat->total_time = edata.total_count;
 185
 186         return ret;
 187 }
 188
 189 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
 190 {
 191         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 192
 193         *freq = dmcfreq->rate;
 194
 195         return 0;
 196 }
 197
 198 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
 199         .polling_ms     = 200,
 200         .target         = rk3399_dmcfreq_target,
 201         .get_dev_status = rk3399_dmcfreq_get_dev_status,
 202         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
 203 };
 204
 205 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
 206 {
 207         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 208         int ret = 0;
 209
 210         ret = devfreq_event_disable_edev(dmcfreq->edev);
 211         if (ret < 0) {
 212                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 213                 return ret;
 214         }
 215
 216         ret = devfreq_suspend_device(dmcfreq->devfreq);
 217         if (ret < 0) {
 218                 dev_err(dev, "failed to suspend the devfreq devices\n");
 219                 return ret;
 220         }
 221
 222         return 0;
 223 }
 224
 225 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
 226 {
 227         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 228         int ret = 0;
 229
 230         ret = devfreq_event_enable_edev(dmcfreq->edev);
 231         if (ret < 0) {
 232                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 233                 return ret;
 234         }
 235
 236         ret = devfreq_resume_device(dmcfreq->devfreq);
 237         if (ret < 0) {
 238                 dev_err(dev, "failed to resume the devfreq devices\n");
 239                 return ret;
 240         }
 241         return ret;
 242 }
 243
 244 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
 245                          rk3399_dmcfreq_resume);
 246
 247 static int of_get_ddr_timings(struct dram_timing *timing,
 248                               struct device_node *np)
 249 {
 250         int ret = 0;
 251
 252         ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
 253                                    &timing->ddr3_speed_bin);
 254         ret |= of_property_read_u32(np, "rockchip,pd_idle",
 255                                     &timing->pd_idle);
 256         ret |= of_property_read_u32(np, "rockchip,sr_idle",
 257                                     &timing->sr_idle);
 258         ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
 259                                     &timing->sr_mc_gate_idle);
 260         ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
 261                                     &timing->srpd_lite_idle);
 262         ret |= of_property_read_u32(np, "rockchip,standby_idle",
 263                                     &timing->standby_idle);
 264         ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
 265                                     &timing->auto_pd_dis_freq);
 266         ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
 267                                     &timing->dram_dll_dis_freq);
 268         ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
 269                                     &timing->phy_dll_dis_freq);
 270         ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
 271                                     &timing->ddr3_odt_dis_freq);
 272         ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
 273                                     &timing->ddr3_drv);
 274         ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
 275                                     &timing->ddr3_odt);
 276         ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
 277                                     &timing->phy_ddr3_ca_drv);
 278         ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
 279                                     &timing->phy_ddr3_dq_drv);
 280         ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
 281                                     &timing->phy_ddr3_odt);
 282         ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
 283                                     &timing->lpddr3_odt_dis_freq);
 284         ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
 285                                     &timing->lpddr3_drv);
 286         ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
 287                                     &timing->lpddr3_odt);
 288         ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
 289                                     &timing->phy_lpddr3_ca_drv);
 290         ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
 291                                     &timing->phy_lpddr3_dq_drv);
 292         ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
 293                                     &timing->phy_lpddr3_odt);
 294         ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
 295                                     &timing->lpddr4_odt_dis_freq);
 296         ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
 297                                     &timing->lpddr4_drv);
 298         ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
 299                                     &timing->lpddr4_dq_odt);
 300         ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
 301                                     &timing->lpddr4_ca_odt);
 302         ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
 303                                     &timing->phy_lpddr4_ca_drv);
 304         ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
 305                                     &timing->phy_lpddr4_ck_cs_drv);
 306         ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
 307                                     &timing->phy_lpddr4_dq_drv);
 308         ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
 309                                     &timing->phy_lpddr4_odt);
 310
 311         return ret;
 312 }
 313
 314 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
 315 {
 316         struct arm_smccc_res res;
 317         struct device *dev = &pdev->dev;
 318         struct device_node *np = pdev->dev.of_node, *node;
 319         struct rk3399_dmcfreq *data;
 320         int ret, index, size;
 321         uint32_t *timing;
 322         struct dev_pm_opp *opp;
 323         u32 ddr_type;
 324         u32 val;
 325
 326         data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
 327         if (!data)
 328                 return -ENOMEM;
 329
 330         mutex_init(&data->lock);
 331
 332         data->vdd_center = devm_regulator_get(dev, "center");
 333         if (IS_ERR(data->vdd_center)) {
 334                 if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
 335                         return -EPROBE_DEFER;
 336
 337                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 338                 return PTR_ERR(data->vdd_center);
 339         }
 340
 341         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 342         if (IS_ERR(data->dmc_clk)) {
 343                 if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
 344                         return -EPROBE_DEFER;
 345
 346                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 347                 return PTR_ERR(data->dmc_clk);
 348         }
 349
 350         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 351         if (IS_ERR(data->edev))
 352                 return -EPROBE_DEFER;
 353
 354         ret = devfreq_event_enable_edev(data->edev);
 355         if (ret < 0) {
 356                 dev_err(dev, "failed to enable devfreq-event devices\n");
 357                 return ret;
 358         }
 359
 360         /*
 361          * Get dram timing and pass it to arm trust firmware,
 362          * the dram drvier in arm trust firmware will get these
 363          * timing and to do dram initial.
 364          */
 365         if (!of_get_ddr_timings(&data->timing, np)) {
 366                 timing = &data->timing.ddr3_speed_bin;
 367                 size = sizeof(struct dram_timing) / 4;
 368                 for (index = 0; index < size; index++) {
 369                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 370                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 371                                       0, 0, 0, 0, &res);
 372                         if (res.a0) {
 373                                 dev_err(dev, "Failed to set dram param: %ld\n",
 374                                         res.a0);
 375                                 return -EINVAL;
 376                         }
 377                 }
 378         }
 379
 380         node = of_parse_phandle(np, "rockchip,pmu", 0);
 381         if (node) {
 382                 data->regmap_pmu = syscon_node_to_regmap(node);
 383                 if (IS_ERR(data->regmap_pmu))
 384                         return PTR_ERR(data->regmap_pmu);
 385         }
 386
 387         regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
 388         ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
 389                     RK3399_PMUGRF_DDRTYPE_MASK;
 390
 391         switch (ddr_type) {
 392         case RK3399_PMUGRF_DDRTYPE_DDR3:
 393                 data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
 394                 break;
 395         case RK3399_PMUGRF_DDRTYPE_LPDDR3:
 396                 data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
 397                 break;
 398         case RK3399_PMUGRF_DDRTYPE_LPDDR4:
 399                 data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
 400                 break;
 401         default:
 402                 return -EINVAL;
 403         };
 404
 405         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 406                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 407                       0, 0, 0, 0, &res);
 408
 409         /*
 410          * In TF-A there is a platform SIP call to set the PD (power-down)
 411          * timings and to enable or disable the ODT (on-die termination).
 412          * This call needs three arguments as follows:
 413          *
 414          * arg0:
 415          *     bit[0-7]   : sr_idle
 416          *     bit[8-15]  : sr_mc_gate_idle
 417          *     bit[16-31] : standby idle
 418          * arg1:
 419          *     bit[0-11]  : pd_idle
 420          *     bit[16-27] : srpd_lite_idle
 421          * arg2:
 422          *     bit[0]     : odt enable
 423          */
 424         data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
 425                             ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
 426                             ((data->timing.standby_idle & 0xffff) << 16);
 427         data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
 428                             ((data->timing.srpd_lite_idle & 0xfff) << 16);
 429
 430         /*
 431          * We add a devfreq driver to our parent since it has a device tree node
 432          * with operating points.
 433          */
 434         if (dev_pm_opp_of_add_table(dev)) {
 435                 dev_err(dev, "Invalid operating-points in device tree.\n");
 436                 return -EINVAL;
 437         }
 438
 439         of_property_read_u32(np, "upthreshold",
 440                              &data->ondemand_data.upthreshold);
 441         of_property_read_u32(np, "downdifferential",
 442                              &data->ondemand_data.downdifferential);
 443
 444         data->rate = clk_get_rate(data->dmc_clk);
 445
 446         opp = devfreq_recommended_opp(dev, &data->rate, 0);
 447         if (IS_ERR(opp)) {
 448                 ret = PTR_ERR(opp);
 449                 goto err_free_opp;
 450         }
 451
 452         data->rate = dev_pm_opp_get_freq(opp);
 453         data->volt = dev_pm_opp_get_voltage(opp);
 454         dev_pm_opp_put(opp);
 455
 456         rk3399_devfreq_dmc_profile.initial_freq = data->rate;
 457
 458         data->devfreq = devm_devfreq_add_device(dev,
 459                                            &rk3399_devfreq_dmc_profile,
 460                                            DEVFREQ_GOV_SIMPLE_ONDEMAND,
 461                                            &data->ondemand_data);
 462         if (IS_ERR(data->devfreq)) {
 463                 ret = PTR_ERR(data->devfreq);
 464                 goto err_free_opp;
 465         }
 466
 467         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 468
 469         data->dev = dev;
 470         platform_set_drvdata(pdev, data);
 471
 472         return 0;
 473
 474 err_free_opp:
 475         dev_pm_opp_of_remove_table(&pdev->dev);
 476         return ret;
 477 }
 478
 479 static int rk3399_dmcfreq_remove(struct platform_device *pdev)
 480 {
 481         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
 482
 483         /*
 484          * Before remove the opp table we need to unregister the opp notifier.
 485          */
 486         devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
 487         dev_pm_opp_of_remove_table(dmcfreq->dev);
 488
 489         return 0;
 490 }
 491
 492 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
 493         { .compatible = "rockchip,rk3399-dmc" },
 494         { },
 495 };
 496 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
 497
 498 static struct platform_driver rk3399_dmcfreq_driver = {
 499         .probe  = rk3399_dmcfreq_probe,
 500         .remove = rk3399_dmcfreq_remove,
 501         .driver = {
 502                 .name   = "rk3399-dmc-freq",
 503                 .pm     = &rk3399_dmcfreq_pm,
 504                 .of_match_table = rk3399dmc_devfreq_of_match,
 505         },
 506 };
 507 module_platform_driver(rk3399_dmcfreq_driver);
 508
 509 MODULE_LICENSE("GPL v2");
 510 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 511 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");