1 #include <linux/delay.h>
2 #include <linux/dmaengine.h>
3 #include <linux/dma-mapping.h>
4 #include <linux/platform_device.h>
5 #include <linux/module.h>
7 #include <linux/slab.h>
8 #include <linux/of_dma.h>
9 #include <linux/of_irq.h>
10 #include <linux/dmapool.h>
11 #include <linux/interrupt.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include "dmaengine.h"
17 #define DESC_TYPE_HOST 0x10
18 #define DESC_TYPE_TEARD 0x13
20 #define TD_DESC_IS_RX (1 << 16)
21 #define TD_DESC_DMA_NUM 10
23 #define DESC_LENGTH_BITS_NUM 21
25 #define DESC_TYPE_USB (5 << 26)
26 #define DESC_PD_COMPLETE (1 << 31)
30 #define DMA_TXGCR(x) (0x800 + (x) * 0x20)
31 #define DMA_RXGCR(x) (0x808 + (x) * 0x20)
34 #define GCR_CHAN_ENABLE (1 << 31)
35 #define GCR_TEARDOWN (1 << 30)
36 #define GCR_STARV_RETRY (1 << 24)
37 #define GCR_DESC_TYPE_HOST (1 << 14)
40 #define DMA_SCHED_CTRL 0
41 #define DMA_SCHED_CTRL_EN (1 << 31)
42 #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800)
44 #define SCHED_ENTRY0_CHAN(x) ((x) << 0)
45 #define SCHED_ENTRY0_IS_RX (1 << 7)
47 #define SCHED_ENTRY1_CHAN(x) ((x) << 8)
48 #define SCHED_ENTRY1_IS_RX (1 << 15)
50 #define SCHED_ENTRY2_CHAN(x) ((x) << 16)
51 #define SCHED_ENTRY2_IS_RX (1 << 23)
53 #define SCHED_ENTRY3_CHAN(x) ((x) << 24)
54 #define SCHED_ENTRY3_IS_RX (1 << 31)
57 /* 4 KiB of memory for descriptors, 2 for each endpoint */
58 #define ALLOC_DECS_NUM 128
60 #define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS)
61 #define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4)
63 #define QMGR_LRAM0_BASE 0x80
64 #define QMGR_LRAM_SIZE 0x84
65 #define QMGR_LRAM1_BASE 0x88
66 #define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10)
67 #define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10)
68 #define QMGR_MEMCTRL_IDX_SH 16
69 #define QMGR_MEMCTRL_DESC_SH 8
71 #define QMGR_NUM_PEND 5
72 #define QMGR_PEND(x) (0x90 + (x) * 4)
74 #define QMGR_PENDING_SLOT_Q(x) (x / 32)
75 #define QMGR_PENDING_BIT_Q(x) (x % 32)
77 #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)
78 #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)
79 #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)
80 #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10)
82 /* Glue layer specific */
83 /* USBSS / USB AM335x */
84 #define USBSS_IRQ_STATUS 0x28
85 #define USBSS_IRQ_ENABLER 0x2c
86 #define USBSS_IRQ_CLEARR 0x30
88 #define USBSS_IRQ_PD_COMP (1 << 2)
90 /* Packet Descriptor */
91 #define PD2_ZERO_LENGTH (1 << 19)
93 struct cppi41_channel {
95 struct dma_async_tx_descriptor txd;
96 struct cppi41_dd *cdd;
97 struct cppi41_desc *desc;
99 void __iomem *gcr_reg;
104 unsigned int q_comp_num;
105 unsigned int port_num;
108 unsigned td_queued:1;
110 unsigned td_desc_seen:1;
112 struct list_head node; /* Node for pending list */
132 struct dma_device ddev;
135 dma_addr_t scratch_phys;
137 struct cppi41_desc *cd;
138 dma_addr_t descs_phys;
140 struct cppi41_channel *chan_busy[ALLOC_DECS_NUM];
142 void __iomem *usbss_mem;
143 void __iomem *ctrl_mem;
144 void __iomem *sched_mem;
145 void __iomem *qmgr_mem;
147 const struct chan_queues *queues_rx;
148 const struct chan_queues *queues_tx;
149 struct chan_queues td_queue;
151 struct list_head pending; /* Pending queued transfers */
152 spinlock_t lock; /* Lock for pending list */
154 /* context for suspend/resume */
155 unsigned int dma_tdfdq;
158 #define FIST_COMPLETION_QUEUE 93
159 static struct chan_queues usb_queues_tx[] = {
161 [ 0] = { .submit = 32, .complete = 93},
162 [ 1] = { .submit = 34, .complete = 94},
163 [ 2] = { .submit = 36, .complete = 95},
164 [ 3] = { .submit = 38, .complete = 96},
165 [ 4] = { .submit = 40, .complete = 97},
166 [ 5] = { .submit = 42, .complete = 98},
167 [ 6] = { .submit = 44, .complete = 99},
168 [ 7] = { .submit = 46, .complete = 100},
169 [ 8] = { .submit = 48, .complete = 101},
170 [ 9] = { .submit = 50, .complete = 102},
171 [10] = { .submit = 52, .complete = 103},
172 [11] = { .submit = 54, .complete = 104},
173 [12] = { .submit = 56, .complete = 105},
174 [13] = { .submit = 58, .complete = 106},
175 [14] = { .submit = 60, .complete = 107},
178 [15] = { .submit = 62, .complete = 125},
179 [16] = { .submit = 64, .complete = 126},
180 [17] = { .submit = 66, .complete = 127},
181 [18] = { .submit = 68, .complete = 128},
182 [19] = { .submit = 70, .complete = 129},
183 [20] = { .submit = 72, .complete = 130},
184 [21] = { .submit = 74, .complete = 131},
185 [22] = { .submit = 76, .complete = 132},
186 [23] = { .submit = 78, .complete = 133},
187 [24] = { .submit = 80, .complete = 134},
188 [25] = { .submit = 82, .complete = 135},
189 [26] = { .submit = 84, .complete = 136},
190 [27] = { .submit = 86, .complete = 137},
191 [28] = { .submit = 88, .complete = 138},
192 [29] = { .submit = 90, .complete = 139},
195 static const struct chan_queues usb_queues_rx[] = {
197 [ 0] = { .submit = 1, .complete = 109},
198 [ 1] = { .submit = 2, .complete = 110},
199 [ 2] = { .submit = 3, .complete = 111},
200 [ 3] = { .submit = 4, .complete = 112},
201 [ 4] = { .submit = 5, .complete = 113},
202 [ 5] = { .submit = 6, .complete = 114},
203 [ 6] = { .submit = 7, .complete = 115},
204 [ 7] = { .submit = 8, .complete = 116},
205 [ 8] = { .submit = 9, .complete = 117},
206 [ 9] = { .submit = 10, .complete = 118},
207 [10] = { .submit = 11, .complete = 119},
208 [11] = { .submit = 12, .complete = 120},
209 [12] = { .submit = 13, .complete = 121},
210 [13] = { .submit = 14, .complete = 122},
211 [14] = { .submit = 15, .complete = 123},
214 [15] = { .submit = 16, .complete = 141},
215 [16] = { .submit = 17, .complete = 142},
216 [17] = { .submit = 18, .complete = 143},
217 [18] = { .submit = 19, .complete = 144},
218 [19] = { .submit = 20, .complete = 145},
219 [20] = { .submit = 21, .complete = 146},
220 [21] = { .submit = 22, .complete = 147},
221 [22] = { .submit = 23, .complete = 148},
222 [23] = { .submit = 24, .complete = 149},
223 [24] = { .submit = 25, .complete = 150},
224 [25] = { .submit = 26, .complete = 151},
225 [26] = { .submit = 27, .complete = 152},
226 [27] = { .submit = 28, .complete = 153},
227 [28] = { .submit = 29, .complete = 154},
228 [29] = { .submit = 30, .complete = 155},
231 struct cppi_glue_infos {
232 irqreturn_t (*isr)(int irq, void *data);
233 const struct chan_queues *queues_rx;
234 const struct chan_queues *queues_tx;
235 struct chan_queues td_queue;
238 static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
240 return container_of(c, struct cppi41_channel, chan);
243 static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
245 struct cppi41_channel *c;
249 descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM;
251 if (!((desc >= cdd->descs_phys) &&
252 (desc < (cdd->descs_phys + descs_size)))) {
256 desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
257 BUG_ON(desc_num >= ALLOC_DECS_NUM);
258 c = cdd->chan_busy[desc_num];
259 cdd->chan_busy[desc_num] = NULL;
261 /* Usecount for chan_busy[], paired with push_desc_queue() */
262 pm_runtime_put(cdd->ddev.dev);
267 static void cppi_writel(u32 val, void *__iomem *mem)
269 __raw_writel(val, mem);
272 static u32 cppi_readl(void *__iomem *mem)
274 return __raw_readl(mem);
277 static u32 pd_trans_len(u32 val)
279 return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
282 static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
286 desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
291 static irqreturn_t cppi41_irq(int irq, void *data)
293 struct cppi41_dd *cdd = data;
294 struct cppi41_channel *c;
298 status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
299 if (!(status & USBSS_IRQ_PD_COMP))
301 cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
303 for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
308 val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
309 if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) {
311 /* set corresponding bit for completetion Q 93 */
312 mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE);
313 /* not set all bits for queues less than Q 93 */
315 /* now invert and keep only Q 93+ set */
326 error = pm_runtime_get(cdd->ddev.dev);
328 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
332 val &= ~(1 << q_num);
334 desc = cppi41_pop_desc(cdd, q_num);
335 c = desc_to_chan(cdd, desc);
337 pr_err("%s() q %d desc %08x\n", __func__,
342 if (c->desc->pd2 & PD2_ZERO_LENGTH)
345 len = pd_trans_len(c->desc->pd0);
347 c->residue = pd_trans_len(c->desc->pd6) - len;
348 dma_cookie_complete(&c->txd);
349 dmaengine_desc_get_callback_invoke(&c->txd, NULL);
351 pm_runtime_mark_last_busy(cdd->ddev.dev);
352 pm_runtime_put_autosuspend(cdd->ddev.dev);
358 static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
362 cookie = dma_cookie_assign(tx);
367 static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan)
369 struct cppi41_channel *c = to_cpp41_chan(chan);
370 struct cppi41_dd *cdd = c->cdd;
373 error = pm_runtime_get_sync(cdd->ddev.dev);
375 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
377 pm_runtime_put_noidle(cdd->ddev.dev);
382 dma_cookie_init(chan);
383 dma_async_tx_descriptor_init(&c->txd, chan);
384 c->txd.tx_submit = cppi41_tx_submit;
387 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
389 pm_runtime_mark_last_busy(cdd->ddev.dev);
390 pm_runtime_put_autosuspend(cdd->ddev.dev);
395 static void cppi41_dma_free_chan_resources(struct dma_chan *chan)
397 struct cppi41_channel *c = to_cpp41_chan(chan);
398 struct cppi41_dd *cdd = c->cdd;
401 error = pm_runtime_get_sync(cdd->ddev.dev);
403 pm_runtime_put_noidle(cdd->ddev.dev);
408 WARN_ON(!list_empty(&cdd->pending));
410 pm_runtime_mark_last_busy(cdd->ddev.dev);
411 pm_runtime_put_autosuspend(cdd->ddev.dev);
414 static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan,
415 dma_cookie_t cookie, struct dma_tx_state *txstate)
417 struct cppi41_channel *c = to_cpp41_chan(chan);
421 ret = dma_cookie_status(chan, cookie, txstate);
422 if (txstate && ret == DMA_COMPLETE)
423 txstate->residue = c->residue;
429 static void push_desc_queue(struct cppi41_channel *c)
431 struct cppi41_dd *cdd = c->cdd;
438 reg = GCR_CHAN_ENABLE;
440 reg |= GCR_STARV_RETRY;
441 reg |= GCR_DESC_TYPE_HOST;
442 reg |= c->q_comp_num;
445 cppi_writel(reg, c->gcr_reg);
448 * We don't use writel() but __raw_writel() so we have to make sure
449 * that the DMA descriptor in coherent memory made to the main memory
450 * before starting the dma engine.
455 * DMA transfers can take at least 200ms to complete with USB mass
456 * storage connected. To prevent autosuspend timeouts, we must use
457 * pm_runtime_get/put() when chan_busy[] is modified. This will get
458 * cleared in desc_to_chan() or cppi41_stop_chan() depending on the
459 * outcome of the transfer.
461 pm_runtime_get(cdd->ddev.dev);
463 desc_phys = lower_32_bits(c->desc_phys);
464 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
465 WARN_ON(cdd->chan_busy[desc_num]);
466 cdd->chan_busy[desc_num] = c;
468 reg = (sizeof(struct cppi41_desc) - 24) / 4;
470 cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
473 static void pending_desc(struct cppi41_channel *c)
475 struct cppi41_dd *cdd = c->cdd;
478 spin_lock_irqsave(&cdd->lock, flags);
479 list_add_tail(&c->node, &cdd->pending);
480 spin_unlock_irqrestore(&cdd->lock, flags);
483 static void cppi41_dma_issue_pending(struct dma_chan *chan)
485 struct cppi41_channel *c = to_cpp41_chan(chan);
486 struct cppi41_dd *cdd = c->cdd;
489 error = pm_runtime_get(cdd->ddev.dev);
490 if ((error != -EINPROGRESS) && error < 0) {
491 pm_runtime_put_noidle(cdd->ddev.dev);
492 dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
498 if (likely(pm_runtime_active(cdd->ddev.dev)))
503 pm_runtime_mark_last_busy(cdd->ddev.dev);
504 pm_runtime_put_autosuspend(cdd->ddev.dev);
507 static u32 get_host_pd0(u32 length)
511 reg = DESC_TYPE_HOST << DESC_TYPE;
517 static u32 get_host_pd1(struct cppi41_channel *c)
526 static u32 get_host_pd2(struct cppi41_channel *c)
531 reg |= c->q_comp_num;
536 static u32 get_host_pd3(u32 length)
540 /* PD3 = packet size */
546 static u32 get_host_pd6(u32 length)
550 /* PD6 buffer size */
551 reg = DESC_PD_COMPLETE;
557 static u32 get_host_pd4_or_7(u32 addr)
566 static u32 get_host_pd5(void)
575 static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg(
576 struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len,
577 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
579 struct cppi41_channel *c = to_cpp41_chan(chan);
580 struct cppi41_desc *d;
581 struct scatterlist *sg;
585 for_each_sg(sgl, sg, sg_len, i) {
589 /* We need to use more than one desc once musb supports sg */
590 addr = lower_32_bits(sg_dma_address(sg));
591 len = sg_dma_len(sg);
593 d->pd0 = get_host_pd0(len);
594 d->pd1 = get_host_pd1(c);
595 d->pd2 = get_host_pd2(c);
596 d->pd3 = get_host_pd3(len);
597 d->pd4 = get_host_pd4_or_7(addr);
598 d->pd5 = get_host_pd5();
599 d->pd6 = get_host_pd6(len);
600 d->pd7 = get_host_pd4_or_7(addr);
608 static void cppi41_compute_td_desc(struct cppi41_desc *d)
610 d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
613 static int cppi41_tear_down_chan(struct cppi41_channel *c)
615 struct cppi41_dd *cdd = c->cdd;
616 struct cppi41_desc *td;
622 td += cdd->first_td_desc;
624 td_desc_phys = cdd->descs_phys;
625 td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
628 cppi41_compute_td_desc(td);
631 reg = (sizeof(struct cppi41_desc) - 24) / 4;
633 cppi_writel(reg, cdd->qmgr_mem +
634 QMGR_QUEUE_D(cdd->td_queue.submit));
636 reg = GCR_CHAN_ENABLE;
638 reg |= GCR_STARV_RETRY;
639 reg |= GCR_DESC_TYPE_HOST;
640 reg |= c->q_comp_num;
643 cppi_writel(reg, c->gcr_reg);
648 if (!c->td_seen || !c->td_desc_seen) {
650 desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
652 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
654 if (desc_phys == c->desc_phys) {
657 } else if (desc_phys == td_desc_phys) {
662 WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
663 WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
664 WARN_ON((pd0 & 0x1f) != c->port_num);
666 } else if (desc_phys) {
672 * If the TX descriptor / channel is in use, the caller needs to poke
673 * his TD bit multiple times. After that he hardware releases the
674 * transfer descriptor followed by TD descriptor. Waiting seems not to
675 * cause any difference.
676 * RX seems to be thrown out right away. However once the TearDown
677 * descriptor gets through we are done. If we have seens the transfer
678 * descriptor before the TD we fetch it from enqueue, it has to be
679 * there waiting for us.
681 if (!c->td_seen && c->td_retry) {
685 WARN_ON(!c->td_retry);
687 if (!c->td_desc_seen) {
688 desc_phys = cppi41_pop_desc(cdd, c->q_num);
690 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
697 cppi_writel(0, c->gcr_reg);
701 static int cppi41_stop_chan(struct dma_chan *chan)
703 struct cppi41_channel *c = to_cpp41_chan(chan);
704 struct cppi41_dd *cdd = c->cdd;
709 desc_phys = lower_32_bits(c->desc_phys);
710 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
711 if (!cdd->chan_busy[desc_num])
714 ret = cppi41_tear_down_chan(c);
718 WARN_ON(!cdd->chan_busy[desc_num]);
719 cdd->chan_busy[desc_num] = NULL;
721 /* Usecount for chan_busy[], paired with push_desc_queue() */
722 pm_runtime_put(cdd->ddev.dev);
727 static void cleanup_chans(struct cppi41_dd *cdd)
729 while (!list_empty(&cdd->ddev.channels)) {
730 struct cppi41_channel *cchan;
732 cchan = list_first_entry(&cdd->ddev.channels,
733 struct cppi41_channel, chan.device_node);
734 list_del(&cchan->chan.device_node);
739 static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
741 struct cppi41_channel *cchan;
746 ret = of_property_read_u32(dev->of_node, "#dma-channels",
751 * The channels can only be used as TX or as RX. So we add twice
752 * that much dma channels because USB can only do RX or TX.
756 for (i = 0; i < n_chans; i++) {
757 cchan = kzalloc(sizeof(*cchan), GFP_KERNEL);
763 cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
766 cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
769 cchan->port_num = i >> 1;
770 cchan->desc = &cdd->cd[i];
771 cchan->desc_phys = cdd->descs_phys;
772 cchan->desc_phys += i * sizeof(struct cppi41_desc);
773 cchan->chan.device = &cdd->ddev;
774 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
776 cdd->first_td_desc = n_chans;
784 static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
786 unsigned int mem_decs;
789 mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc);
791 for (i = 0; i < DESCS_AREAS; i++) {
793 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
794 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
796 dma_free_coherent(dev, mem_decs, cdd->cd,
801 static void disable_sched(struct cppi41_dd *cdd)
803 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
806 static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
810 purge_descs(dev, cdd);
812 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
813 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
814 dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
818 static int init_descs(struct device *dev, struct cppi41_dd *cdd)
820 unsigned int desc_size;
821 unsigned int mem_decs;
826 BUILD_BUG_ON(sizeof(struct cppi41_desc) &
827 (sizeof(struct cppi41_desc) - 1));
828 BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32);
829 BUILD_BUG_ON(ALLOC_DECS_NUM < 32);
831 desc_size = sizeof(struct cppi41_desc);
832 mem_decs = ALLOC_DECS_NUM * desc_size;
835 for (i = 0; i < DESCS_AREAS; i++) {
837 reg = idx << QMGR_MEMCTRL_IDX_SH;
838 reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH;
839 reg |= ilog2(ALLOC_DECS_NUM) - 5;
841 BUILD_BUG_ON(DESCS_AREAS != 1);
842 cdd->cd = dma_alloc_coherent(dev, mem_decs,
843 &cdd->descs_phys, GFP_KERNEL);
847 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
848 cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
850 idx += ALLOC_DECS_NUM;
855 static void init_sched(struct cppi41_dd *cdd)
862 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
863 for (ch = 0; ch < 15 * 2; ch += 2) {
865 reg = SCHED_ENTRY0_CHAN(ch);
866 reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
868 reg |= SCHED_ENTRY2_CHAN(ch + 1);
869 reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX;
870 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
873 reg = 15 * 2 * 2 - 1;
874 reg |= DMA_SCHED_CTRL_EN;
875 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
878 static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
882 BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
883 cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
884 &cdd->scratch_phys, GFP_KERNEL);
885 if (!cdd->qmgr_scratch)
888 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
889 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
890 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
892 ret = init_descs(dev, cdd);
896 cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
900 deinit_cppi41(dev, cdd);
904 static struct platform_driver cpp41_dma_driver;
906 * The param format is:
914 static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
916 struct cppi41_channel *cchan;
917 struct cppi41_dd *cdd;
918 const struct chan_queues *queues;
921 if (chan->device->dev->driver != &cpp41_dma_driver.driver)
924 cchan = to_cpp41_chan(chan);
926 if (cchan->port_num != num[INFO_PORT])
929 if (cchan->is_tx && !num[INFO_IS_TX])
933 queues = cdd->queues_tx;
935 queues = cdd->queues_rx;
937 BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx));
938 if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx)))
941 cchan->q_num = queues[cchan->port_num].submit;
942 cchan->q_comp_num = queues[cchan->port_num].complete;
946 static struct of_dma_filter_info cpp41_dma_info = {
947 .filter_fn = cpp41_dma_filter_fn,
950 static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
951 struct of_dma *ofdma)
953 int count = dma_spec->args_count;
954 struct of_dma_filter_info *info = ofdma->of_dma_data;
956 if (!info || !info->filter_fn)
962 return dma_request_channel(info->dma_cap, info->filter_fn,
966 static const struct cppi_glue_infos usb_infos = {
968 .queues_rx = usb_queues_rx,
969 .queues_tx = usb_queues_tx,
970 .td_queue = { .submit = 31, .complete = 0 },
973 static const struct of_device_id cppi41_dma_ids[] = {
974 { .compatible = "ti,am3359-cppi41", .data = &usb_infos},
977 MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
979 static const struct cppi_glue_infos *get_glue_info(struct device *dev)
981 const struct of_device_id *of_id;
983 of_id = of_match_node(cppi41_dma_ids, dev->of_node);
989 #define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
990 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
991 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
992 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
994 static int cppi41_dma_probe(struct platform_device *pdev)
996 struct cppi41_dd *cdd;
997 struct device *dev = &pdev->dev;
998 const struct cppi_glue_infos *glue_info;
1002 glue_info = get_glue_info(dev);
1006 cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
1010 dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
1011 cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
1012 cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
1013 cdd->ddev.device_tx_status = cppi41_dma_tx_status;
1014 cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
1015 cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
1016 cdd->ddev.device_terminate_all = cppi41_stop_chan;
1017 cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1018 cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS;
1019 cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS;
1020 cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1021 cdd->ddev.dev = dev;
1022 INIT_LIST_HEAD(&cdd->ddev.channels);
1023 cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
1025 cdd->usbss_mem = of_iomap(dev->of_node, 0);
1026 cdd->ctrl_mem = of_iomap(dev->of_node, 1);
1027 cdd->sched_mem = of_iomap(dev->of_node, 2);
1028 cdd->qmgr_mem = of_iomap(dev->of_node, 3);
1029 spin_lock_init(&cdd->lock);
1030 INIT_LIST_HEAD(&cdd->pending);
1032 platform_set_drvdata(pdev, cdd);
1034 if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
1038 pm_runtime_enable(dev);
1039 pm_runtime_set_autosuspend_delay(dev, 100);
1040 pm_runtime_use_autosuspend(dev);
1041 ret = pm_runtime_get_sync(dev);
1045 cdd->queues_rx = glue_info->queues_rx;
1046 cdd->queues_tx = glue_info->queues_tx;
1047 cdd->td_queue = glue_info->td_queue;
1049 ret = init_cppi41(dev, cdd);
1053 ret = cppi41_add_chans(dev, cdd);
1057 irq = irq_of_parse_and_map(dev->of_node, 0);
1063 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1065 ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED,
1066 dev_name(dev), cdd);
1071 ret = dma_async_device_register(&cdd->ddev);
1075 ret = of_dma_controller_register(dev->of_node,
1076 cppi41_dma_xlate, &cpp41_dma_info);
1080 pm_runtime_mark_last_busy(dev);
1081 pm_runtime_put_autosuspend(dev);
1085 dma_async_device_unregister(&cdd->ddev);
1088 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1091 deinit_cppi41(dev, cdd);
1093 pm_runtime_dont_use_autosuspend(dev);
1095 pm_runtime_put_sync(dev);
1096 pm_runtime_disable(dev);
1097 iounmap(cdd->usbss_mem);
1098 iounmap(cdd->ctrl_mem);
1099 iounmap(cdd->sched_mem);
1100 iounmap(cdd->qmgr_mem);
1104 static int cppi41_dma_remove(struct platform_device *pdev)
1106 struct cppi41_dd *cdd = platform_get_drvdata(pdev);
1109 error = pm_runtime_get_sync(&pdev->dev);
1111 dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n",
1113 of_dma_controller_free(pdev->dev.of_node);
1114 dma_async_device_unregister(&cdd->ddev);
1116 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1117 devm_free_irq(&pdev->dev, cdd->irq, cdd);
1119 deinit_cppi41(&pdev->dev, cdd);
1120 iounmap(cdd->usbss_mem);
1121 iounmap(cdd->ctrl_mem);
1122 iounmap(cdd->sched_mem);
1123 iounmap(cdd->qmgr_mem);
1124 pm_runtime_dont_use_autosuspend(&pdev->dev);
1125 pm_runtime_put_sync(&pdev->dev);
1126 pm_runtime_disable(&pdev->dev);
1130 static int __maybe_unused cppi41_suspend(struct device *dev)
1132 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1134 cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
1135 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1141 static int __maybe_unused cppi41_resume(struct device *dev)
1143 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1144 struct cppi41_channel *c;
1147 for (i = 0; i < DESCS_AREAS; i++)
1148 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
1150 list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
1152 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
1156 cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
1157 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
1158 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
1159 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
1161 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1166 static int __maybe_unused cppi41_runtime_suspend(struct device *dev)
1168 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1170 WARN_ON(!list_empty(&cdd->pending));
1175 static int __maybe_unused cppi41_runtime_resume(struct device *dev)
1177 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1178 struct cppi41_channel *c, *_c;
1179 unsigned long flags;
1181 spin_lock_irqsave(&cdd->lock, flags);
1182 list_for_each_entry_safe(c, _c, &cdd->pending, node) {
1186 spin_unlock_irqrestore(&cdd->lock, flags);
1191 static const struct dev_pm_ops cppi41_pm_ops = {
1192 SET_LATE_SYSTEM_SLEEP_PM_OPS(cppi41_suspend, cppi41_resume)
1193 SET_RUNTIME_PM_OPS(cppi41_runtime_suspend,
1194 cppi41_runtime_resume,
1198 static struct platform_driver cpp41_dma_driver = {
1199 .probe = cppi41_dma_probe,
1200 .remove = cppi41_dma_remove,
1202 .name = "cppi41-dma-engine",
1203 .pm = &cppi41_pm_ops,
1204 .of_match_table = of_match_ptr(cppi41_dma_ids),
1208 module_platform_driver(cpp41_dma_driver);
1209 MODULE_LICENSE("GPL");
1210 MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");