drivers/dma/dw/idma32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2013,2018 Intel Corporation
   3
   4 #include <linux/bitops.h>
   5 #include <linux/errno.h>
   6 #include <linux/slab.h>
   7 #include <linux/types.h>
   8
   9 #include "internal.h"
  10
  11 static void idma32_initialize_chan(struct dw_dma_chan *dwc)
  12 {
  13         u32 cfghi = 0;
  14         u32 cfglo = 0;
  15
  16         /* Set default burst alignment */
  17         cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
  18
  19         /* Low 4 bits of the request lines */
  20         cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
  21         cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
  22
  23         /* Request line extension (2 bits) */
  24         cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
  25         cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
  26
  27         channel_writel(dwc, CFG_LO, cfglo);
  28         channel_writel(dwc, CFG_HI, cfghi);
  29 }
  30
  31 static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain)
  32 {
  33         u32 cfglo = channel_readl(dwc, CFG_LO);
  34
  35         if (drain)
  36                 cfglo |= IDMA32C_CFGL_CH_DRAIN;
  37
  38         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
  39 }
  40
  41 static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain)
  42 {
  43         u32 cfglo = channel_readl(dwc, CFG_LO);
  44
  45         if (drain)
  46                 cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
  47
  48         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
  49 }
  50
  51 static u32 idma32_bytes2block(struct dw_dma_chan *dwc,
  52                               size_t bytes, unsigned int width, size_t *len)
  53 {
  54         u32 block;
  55
  56         if (bytes > dwc->block_size) {
  57                 block = dwc->block_size;
  58                 *len = dwc->block_size;
  59         } else {
  60                 block = bytes;
  61                 *len = bytes;
  62         }
  63
  64         return block;
  65 }
  66
  67 static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
  68 {
  69         return IDMA32C_CTLH_BLOCK_TS(block);
  70 }
  71
  72 static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
  73 {
  74         *maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
  75 }
  76
  77 static void idma32_set_device_name(struct dw_dma *dw, int id)
  78 {
  79         snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
  80 }
  81
  82 /*
  83  * Program FIFO size of channels.
  84  *
  85  * By default full FIFO (512 bytes) is assigned to channel 0. Here we
  86  * slice FIFO on equal parts between channels.
  87  */
  88 static void idma32_fifo_partition(struct dw_dma *dw)
  89 {
  90         u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
  91                     IDMA32C_FP_UPDATE;
  92         u64 fifo_partition = 0;
  93
  94         /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
  95         fifo_partition |= value << 0;
  96
  97         /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
  98         fifo_partition |= value << 32;
  99
 100         /* Program FIFO Partition registers - 64 bytes per channel */
 101         idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
 102         idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
 103 }
 104
 105 static void idma32_disable(struct dw_dma *dw)
 106 {
 107         do_dw_dma_off(dw);
 108         idma32_fifo_partition(dw);
 109 }
 110
 111 static void idma32_enable(struct dw_dma *dw)
 112 {
 113         idma32_fifo_partition(dw);
 114         do_dw_dma_on(dw);
 115 }
 116
 117 int idma32_dma_probe(struct dw_dma_chip *chip)
 118 {
 119         struct dw_dma *dw;
 120
 121         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
 122         if (!dw)
 123                 return -ENOMEM;
 124
 125         /* Channel operations */
 126         dw->initialize_chan = idma32_initialize_chan;
 127         dw->suspend_chan = idma32_suspend_chan;
 128         dw->resume_chan = idma32_resume_chan;
 129         dw->encode_maxburst = idma32_encode_maxburst;
 130         dw->bytes2block = idma32_bytes2block;
 131         dw->block2bytes = idma32_block2bytes;
 132
 133         /* Device operations */
 134         dw->set_device_name = idma32_set_device_name;
 135         dw->disable = idma32_disable;
 136         dw->enable = idma32_enable;
 137
 138         chip->dw = dw;
 139         return do_dma_probe(chip);
 140 }
 141 EXPORT_SYMBOL_GPL(idma32_dma_probe);
 142
 143 int idma32_dma_remove(struct dw_dma_chip *chip)
 144 {
 145         return do_dma_remove(chip);
 146 }
 147 EXPORT_SYMBOL_GPL(idma32_dma_remove);