drivers/dma/imx-sdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-sdma.c
   4 //
   5 // This file contains a driver for the Freescale Smart DMA engine
   6 //
   7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8 //
   9 // Based on code from Freescale:
  10 //
  11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  12
  13 #include <linux/init.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mm.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firmware.h>
  28 #include <linux/slab.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_dma.h>
  35
  36 #include <asm/irq.h>
  37 #include <linux/platform_data/dma-imx-sdma.h>
  38 #include <linux/platform_data/dma-imx.h>
  39 #include <linux/regmap.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  42
  43 #include "dmaengine.h"
  44 #include "virt-dma.h"
  45
  46 /* SDMA registers */
  47 #define SDMA_H_C0PTR            0x000
  48 #define SDMA_H_INTR             0x004
  49 #define SDMA_H_STATSTOP         0x008
  50 #define SDMA_H_START            0x00c
  51 #define SDMA_H_EVTOVR           0x010
  52 #define SDMA_H_DSPOVR           0x014
  53 #define SDMA_H_HOSTOVR          0x018
  54 #define SDMA_H_EVTPEND          0x01c
  55 #define SDMA_H_DSPENBL          0x020
  56 #define SDMA_H_RESET            0x024
  57 #define SDMA_H_EVTERR           0x028
  58 #define SDMA_H_INTRMSK          0x02c
  59 #define SDMA_H_PSW              0x030
  60 #define SDMA_H_EVTERRDBG        0x034
  61 #define SDMA_H_CONFIG           0x038
  62 #define SDMA_ONCE_ENB           0x040
  63 #define SDMA_ONCE_DATA          0x044
  64 #define SDMA_ONCE_INSTR         0x048
  65 #define SDMA_ONCE_STAT          0x04c
  66 #define SDMA_ONCE_CMD           0x050
  67 #define SDMA_EVT_MIRROR         0x054
  68 #define SDMA_ILLINSTADDR        0x058
  69 #define SDMA_CHN0ADDR           0x05c
  70 #define SDMA_ONCE_RTB           0x060
  71 #define SDMA_XTRIG_CONF1        0x070
  72 #define SDMA_XTRIG_CONF2        0x074
  73 #define SDMA_CHNENBL0_IMX35     0x200
  74 #define SDMA_CHNENBL0_IMX31     0x080
  75 #define SDMA_CHNPRI_0           0x100
  76
  77 /*
  78  * Buffer descriptor status values.
  79  */
  80 #define BD_DONE  0x01
  81 #define BD_WRAP  0x02
  82 #define BD_CONT  0x04
  83 #define BD_INTR  0x08
  84 #define BD_RROR  0x10
  85 #define BD_LAST  0x20
  86 #define BD_EXTD  0x80
  87
  88 /*
  89  * Data Node descriptor status values.
  90  */
  91 #define DND_END_OF_FRAME  0x80
  92 #define DND_END_OF_XFER   0x40
  93 #define DND_DONE          0x20
  94 #define DND_UNUSED        0x01
  95
  96 /*
  97  * IPCV2 descriptor status values.
  98  */
  99 #define BD_IPCV2_END_OF_FRAME  0x40
 100
 101 #define IPCV2_MAX_NODES        50
 102 /*
 103  * Error bit set in the CCB status field by the SDMA,
 104  * in setbd routine, in case of a transfer error
 105  */
 106 #define DATA_ERROR  0x10000000
 107
 108 /*
 109  * Buffer descriptor commands.
 110  */
 111 #define C0_ADDR             0x01
 112 #define C0_LOAD             0x02
 113 #define C0_DUMP             0x03
 114 #define C0_SETCTX           0x07
 115 #define C0_GETCTX           0x03
 116 #define C0_SETDM            0x01
 117 #define C0_SETPM            0x04
 118 #define C0_GETDM            0x02
 119 #define C0_GETPM            0x08
 120 /*
 121  * Change endianness indicator in the BD command field
 122  */
 123 #define CHANGE_ENDIANNESS   0x80
 124
 125 /*
 126  *  p_2_p watermark_level description
 127  *      Bits            Name                    Description
 128  *      0-7             Lower WML               Lower watermark level
 129  *      8               PS                      1: Pad Swallowing
 130  *                                              0: No Pad Swallowing
 131  *      9               PA                      1: Pad Adding
 132  *                                              0: No Pad Adding
 133  *      10              SPDIF                   If this bit is set both source
 134  *                                              and destination are on SPBA
 135  *      11              Source Bit(SP)          1: Source on SPBA
 136  *                                              0: Source on AIPS
 137  *      12              Destination Bit(DP)     1: Destination on SPBA
 138  *                                              0: Destination on AIPS
 139  *      13-15           ---------               MUST BE 0
 140  *      16-23           Higher WML              HWML
 141  *      24-27           N                       Total number of samples after
 142  *                                              which Pad adding/Swallowing
 143  *                                              must be done. It must be odd.
 144  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 145  *                                              LWML event mask
 146  *                                              0: LWE in EVENTS register
 147  *                                              1: LWE in EVENTS2 register
 148  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 149  *                                              HWML event mask
 150  *                                              0: HWE in EVENTS register
 151  *                                              1: HWE in EVENTS2 register
 152  *      30              ---------               MUST BE 0
 153  *      31              CONT                    1: Amount of samples to be
 154  *                                              transferred is unknown and
 155  *                                              script will keep on
 156  *                                              transferring samples as long as
 157  *                                              both events are detected and
 158  *                                              script must be manually stopped
 159  *                                              by the application
 160  *                                              0: The amount of samples to be
 161  *                                              transferred is equal to the
 162  *                                              count field of mode word
 163  */
 164 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 165 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 166 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 167 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 168 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 169 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 170 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 171 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 172 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 173 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 174
 175 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 176                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 177                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 178
 179 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 180                                  BIT(DMA_MEM_TO_DEV) | \
 181                                  BIT(DMA_DEV_TO_DEV))
 182
 183 /*
 184  * Mode/Count of data node descriptors - IPCv2
 185  */
 186 struct sdma_mode_count {
 187         u32 count   : 16; /* size of the buffer pointed by this BD */
 188         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 189         u32 command :  8; /* command mostly used for channel 0 */
 190 };
 191
 192 /*
 193  * Buffer descriptor
 194  */
 195 struct sdma_buffer_descriptor {
 196         struct sdma_mode_count  mode;
 197         u32 buffer_addr;        /* address of the buffer described */
 198         u32 ext_buffer_addr;    /* extended buffer address */
 199 } __attribute__ ((packed));
 200
 201 /**
 202  * struct sdma_channel_control - Channel control Block
 203  *
 204  * @current_bd_ptr      current buffer descriptor processed
 205  * @base_bd_ptr         first element of buffer descriptor array
 206  * @unused              padding. The SDMA engine expects an array of 128 byte
 207  *                      control blocks
 208  */
 209 struct sdma_channel_control {
 210         u32 current_bd_ptr;
 211         u32 base_bd_ptr;
 212         u32 unused[2];
 213 } __attribute__ ((packed));
 214
 215 /**
 216  * struct sdma_state_registers - SDMA context for a channel
 217  *
 218  * @pc:         program counter
 219  * @t:          test bit: status of arithmetic & test instruction
 220  * @rpc:        return program counter
 221  * @sf:         source fault while loading data
 222  * @spc:        loop start program counter
 223  * @df:         destination fault while storing data
 224  * @epc:        loop end program counter
 225  * @lm:         loop mode
 226  */
 227 struct sdma_state_registers {
 228         u32 pc     :14;
 229         u32 unused1: 1;
 230         u32 t      : 1;
 231         u32 rpc    :14;
 232         u32 unused0: 1;
 233         u32 sf     : 1;
 234         u32 spc    :14;
 235         u32 unused2: 1;
 236         u32 df     : 1;
 237         u32 epc    :14;
 238         u32 lm     : 2;
 239 } __attribute__ ((packed));
 240
 241 /**
 242  * struct sdma_context_data - sdma context specific to a channel
 243  *
 244  * @channel_state:      channel state bits
 245  * @gReg:               general registers
 246  * @mda:                burst dma destination address register
 247  * @msa:                burst dma source address register
 248  * @ms:                 burst dma status register
 249  * @md:                 burst dma data register
 250  * @pda:                peripheral dma destination address register
 251  * @psa:                peripheral dma source address register
 252  * @ps:                 peripheral dma status register
 253  * @pd:                 peripheral dma data register
 254  * @ca:                 CRC polynomial register
 255  * @cs:                 CRC accumulator register
 256  * @dda:                dedicated core destination address register
 257  * @dsa:                dedicated core source address register
 258  * @ds:                 dedicated core status register
 259  * @dd:                 dedicated core data register
 260  */
 261 struct sdma_context_data {
 262         struct sdma_state_registers  channel_state;
 263         u32  gReg[8];
 264         u32  mda;
 265         u32  msa;
 266         u32  ms;
 267         u32  md;
 268         u32  pda;
 269         u32  psa;
 270         u32  ps;
 271         u32  pd;
 272         u32  ca;
 273         u32  cs;
 274         u32  dda;
 275         u32  dsa;
 276         u32  ds;
 277         u32  dd;
 278         u32  scratch0;
 279         u32  scratch1;
 280         u32  scratch2;
 281         u32  scratch3;
 282         u32  scratch4;
 283         u32  scratch5;
 284         u32  scratch6;
 285         u32  scratch7;
 286 } __attribute__ ((packed));
 287
 288
 289 struct sdma_engine;
 290
 291 /**
 292  * struct sdma_desc - descriptor structor for one transfer
 293  * @vd                  descriptor for virt dma
 294  * @num_bd              max NUM_BD. number of descriptors currently handling
 295  * @buf_tail            ID of the buffer that was processed
 296  * @buf_ptail           ID of the previous buffer that was processed
 297  * @period_len          period length, used in cyclic.
 298  * @chn_real_count      the real count updated from bd->mode.count
 299  * @chn_count           the transfer count setuped
 300  * @sdmac               sdma_channel pointer
 301  * @bd                  pointer of alloced bd
 302  */
 303 struct sdma_desc {
 304         struct virt_dma_desc    vd;
 305         unsigned int            num_bd;
 306         dma_addr_t              bd_phys;
 307         unsigned int            buf_tail;
 308         unsigned int            buf_ptail;
 309         unsigned int            period_len;
 310         unsigned int            chn_real_count;
 311         unsigned int            chn_count;
 312         struct sdma_channel     *sdmac;
 313         struct sdma_buffer_descriptor *bd;
 314 };
 315
 316 /**
 317  * struct sdma_channel - housekeeping for a SDMA channel
 318  *
 319  * @sdma                pointer to the SDMA engine for this channel
 320  * @channel             the channel number, matches dmaengine chan_id + 1
 321  * @direction           transfer type. Needed for setting SDMA script
 322  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 323  * @event_id0           aka dma request line
 324  * @event_id1           for channels that use 2 events
 325  * @word_size           peripheral access size
 326  */
 327 struct sdma_channel {
 328         struct virt_dma_chan            vc;
 329         struct sdma_desc                *desc;
 330         struct sdma_engine              *sdma;
 331         unsigned int                    channel;
 332         enum dma_transfer_direction             direction;
 333         enum sdma_peripheral_type       peripheral_type;
 334         unsigned int                    event_id0;
 335         unsigned int                    event_id1;
 336         enum dma_slave_buswidth         word_size;
 337         unsigned int                    pc_from_device, pc_to_device;
 338         unsigned int                    device_to_device;
 339         unsigned long                   flags;
 340         dma_addr_t                      per_address, per_address2;
 341         unsigned long                   event_mask[2];
 342         unsigned long                   watermark_level;
 343         u32                             shp_addr, per_addr;
 344         enum dma_status                 status;
 345         struct imx_dma_data             data;
 346 };
 347
 348 #define IMX_DMA_SG_LOOP         BIT(0)
 349
 350 #define MAX_DMA_CHANNELS 32
 351 #define MXC_SDMA_DEFAULT_PRIORITY 1
 352 #define MXC_SDMA_MIN_PRIORITY 1
 353 #define MXC_SDMA_MAX_PRIORITY 7
 354
 355 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 356
 357 /**
 358  * struct sdma_firmware_header - Layout of the firmware image
 359  *
 360  * @magic               "SDMA"
 361  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 362  *                      changes.
 363  * @version_minor       firmware minor version (for binary compatible changes)
 364  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 365  * @num_script_addrs    Number of script addresses in this image
 366  * @ram_code_start      offset of SDMA ram image in this firmware image
 367  * @ram_code_size       size of SDMA ram image
 368  * @script_addrs        Stores the start address of the SDMA scripts
 369  *                      (in SDMA memory space)
 370  */
 371 struct sdma_firmware_header {
 372         u32     magic;
 373         u32     version_major;
 374         u32     version_minor;
 375         u32     script_addrs_start;
 376         u32     num_script_addrs;
 377         u32     ram_code_start;
 378         u32     ram_code_size;
 379 };
 380
 381 struct sdma_driver_data {
 382         int chnenbl0;
 383         int num_events;
 384         struct sdma_script_start_addrs  *script_addrs;
 385 };
 386
 387 struct sdma_engine {
 388         struct device                   *dev;
 389         struct device_dma_parameters    dma_parms;
 390         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 391         struct sdma_channel_control     *channel_control;
 392         void __iomem                    *regs;
 393         struct sdma_context_data        *context;
 394         dma_addr_t                      context_phys;
 395         struct dma_device               dma_device;
 396         struct clk                      *clk_ipg;
 397         struct clk                      *clk_ahb;
 398         spinlock_t                      channel_0_lock;
 399         u32                             script_number;
 400         struct sdma_script_start_addrs  *script_addrs;
 401         const struct sdma_driver_data   *drvdata;
 402         u32                             spba_start_addr;
 403         u32                             spba_end_addr;
 404         unsigned int                    irq;
 405         dma_addr_t                      bd0_phys;
 406         struct sdma_buffer_descriptor   *bd0;
 407 };
 408
 409 static struct sdma_driver_data sdma_imx31 = {
 410         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 411         .num_events = 32,
 412 };
 413
 414 static struct sdma_script_start_addrs sdma_script_imx25 = {
 415         .ap_2_ap_addr = 729,
 416         .uart_2_mcu_addr = 904,
 417         .per_2_app_addr = 1255,
 418         .mcu_2_app_addr = 834,
 419         .uartsh_2_mcu_addr = 1120,
 420         .per_2_shp_addr = 1329,
 421         .mcu_2_shp_addr = 1048,
 422         .ata_2_mcu_addr = 1560,
 423         .mcu_2_ata_addr = 1479,
 424         .app_2_per_addr = 1189,
 425         .app_2_mcu_addr = 770,
 426         .shp_2_per_addr = 1407,
 427         .shp_2_mcu_addr = 979,
 428 };
 429
 430 static struct sdma_driver_data sdma_imx25 = {
 431         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 432         .num_events = 48,
 433         .script_addrs = &sdma_script_imx25,
 434 };
 435
 436 static struct sdma_driver_data sdma_imx35 = {
 437         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 438         .num_events = 48,
 439 };
 440
 441 static struct sdma_script_start_addrs sdma_script_imx51 = {
 442         .ap_2_ap_addr = 642,
 443         .uart_2_mcu_addr = 817,
 444         .mcu_2_app_addr = 747,
 445         .mcu_2_shp_addr = 961,
 446         .ata_2_mcu_addr = 1473,
 447         .mcu_2_ata_addr = 1392,
 448         .app_2_per_addr = 1033,
 449         .app_2_mcu_addr = 683,
 450         .shp_2_per_addr = 1251,
 451         .shp_2_mcu_addr = 892,
 452 };
 453
 454 static struct sdma_driver_data sdma_imx51 = {
 455         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 456         .num_events = 48,
 457         .script_addrs = &sdma_script_imx51,
 458 };
 459
 460 static struct sdma_script_start_addrs sdma_script_imx53 = {
 461         .ap_2_ap_addr = 642,
 462         .app_2_mcu_addr = 683,
 463         .mcu_2_app_addr = 747,
 464         .uart_2_mcu_addr = 817,
 465         .shp_2_mcu_addr = 891,
 466         .mcu_2_shp_addr = 960,
 467         .uartsh_2_mcu_addr = 1032,
 468         .spdif_2_mcu_addr = 1100,
 469         .mcu_2_spdif_addr = 1134,
 470         .firi_2_mcu_addr = 1193,
 471         .mcu_2_firi_addr = 1290,
 472 };
 473
 474 static struct sdma_driver_data sdma_imx53 = {
 475         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 476         .num_events = 48,
 477         .script_addrs = &sdma_script_imx53,
 478 };
 479
 480 static struct sdma_script_start_addrs sdma_script_imx6q = {
 481         .ap_2_ap_addr = 642,
 482         .uart_2_mcu_addr = 817,
 483         .mcu_2_app_addr = 747,
 484         .per_2_per_addr = 6331,
 485         .uartsh_2_mcu_addr = 1032,
 486         .mcu_2_shp_addr = 960,
 487         .app_2_mcu_addr = 683,
 488         .shp_2_mcu_addr = 891,
 489         .spdif_2_mcu_addr = 1100,
 490         .mcu_2_spdif_addr = 1134,
 491 };
 492
 493 static struct sdma_driver_data sdma_imx6q = {
 494         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 495         .num_events = 48,
 496         .script_addrs = &sdma_script_imx6q,
 497 };
 498
 499 static struct sdma_script_start_addrs sdma_script_imx7d = {
 500         .ap_2_ap_addr = 644,
 501         .uart_2_mcu_addr = 819,
 502         .mcu_2_app_addr = 749,
 503         .uartsh_2_mcu_addr = 1034,
 504         .mcu_2_shp_addr = 962,
 505         .app_2_mcu_addr = 685,
 506         .shp_2_mcu_addr = 893,
 507         .spdif_2_mcu_addr = 1102,
 508         .mcu_2_spdif_addr = 1136,
 509 };
 510
 511 static struct sdma_driver_data sdma_imx7d = {
 512         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 513         .num_events = 48,
 514         .script_addrs = &sdma_script_imx7d,
 515 };
 516
 517 static const struct platform_device_id sdma_devtypes[] = {
 518         {
 519                 .name = "imx25-sdma",
 520                 .driver_data = (unsigned long)&sdma_imx25,
 521         }, {
 522                 .name = "imx31-sdma",
 523                 .driver_data = (unsigned long)&sdma_imx31,
 524         }, {
 525                 .name = "imx35-sdma",
 526                 .driver_data = (unsigned long)&sdma_imx35,
 527         }, {
 528                 .name = "imx51-sdma",
 529                 .driver_data = (unsigned long)&sdma_imx51,
 530         }, {
 531                 .name = "imx53-sdma",
 532                 .driver_data = (unsigned long)&sdma_imx53,
 533         }, {
 534                 .name = "imx6q-sdma",
 535                 .driver_data = (unsigned long)&sdma_imx6q,
 536         }, {
 537                 .name = "imx7d-sdma",
 538                 .driver_data = (unsigned long)&sdma_imx7d,
 539         }, {
 540                 /* sentinel */
 541         }
 542 };
 543 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 544
 545 static const struct of_device_id sdma_dt_ids[] = {
 546         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 547         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 548         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 549         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 550         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 551         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 552         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 553         { /* sentinel */ }
 554 };
 555 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 556
 557 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 558 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 559 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 560 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 561
 562 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 563 {
 564         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 565         return chnenbl0 + event * 4;
 566 }
 567
 568 static int sdma_config_ownership(struct sdma_channel *sdmac,
 569                 bool event_override, bool mcu_override, bool dsp_override)
 570 {
 571         struct sdma_engine *sdma = sdmac->sdma;
 572         int channel = sdmac->channel;
 573         unsigned long evt, mcu, dsp;
 574
 575         if (event_override && mcu_override && dsp_override)
 576                 return -EINVAL;
 577
 578         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 579         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 580         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 581
 582         if (dsp_override)
 583                 __clear_bit(channel, &dsp);
 584         else
 585                 __set_bit(channel, &dsp);
 586
 587         if (event_override)
 588                 __clear_bit(channel, &evt);
 589         else
 590                 __set_bit(channel, &evt);
 591
 592         if (mcu_override)
 593                 __clear_bit(channel, &mcu);
 594         else
 595                 __set_bit(channel, &mcu);
 596
 597         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 598         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 599         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 600
 601         return 0;
 602 }
 603
 604 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 605 {
 606         writel(BIT(channel), sdma->regs + SDMA_H_START);
 607 }
 608
 609 /*
 610  * sdma_run_channel0 - run a channel and wait till it's done
 611  */
 612 static int sdma_run_channel0(struct sdma_engine *sdma)
 613 {
 614         int ret;
 615         u32 reg;
 616
 617         sdma_enable_channel(sdma, 0);
 618
 619         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 620                                                 reg, !(reg & 1), 1, 500);
 621         if (ret)
 622                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 623
 624         /* Set bits of CONFIG register with dynamic context switching */
 625         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 626                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 627
 628         return ret;
 629 }
 630
 631 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 632                 u32 address)
 633 {
 634         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 635         void *buf_virt;
 636         dma_addr_t buf_phys;
 637         int ret;
 638         unsigned long flags;
 639
 640         buf_virt = dma_alloc_coherent(NULL,
 641                         size,
 642                         &buf_phys, GFP_KERNEL);
 643         if (!buf_virt) {
 644                 return -ENOMEM;
 645         }
 646
 647         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 648
 649         bd0->mode.command = C0_SETPM;
 650         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 651         bd0->mode.count = size / 2;
 652         bd0->buffer_addr = buf_phys;
 653         bd0->ext_buffer_addr = address;
 654
 655         memcpy(buf_virt, buf, size);
 656
 657         ret = sdma_run_channel0(sdma);
 658
 659         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 660
 661         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 662
 663         return ret;
 664 }
 665
 666 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 667 {
 668         struct sdma_engine *sdma = sdmac->sdma;
 669         int channel = sdmac->channel;
 670         unsigned long val;
 671         u32 chnenbl = chnenbl_ofs(sdma, event);
 672
 673         val = readl_relaxed(sdma->regs + chnenbl);
 674         __set_bit(channel, &val);
 675         writel_relaxed(val, sdma->regs + chnenbl);
 676 }
 677
 678 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 679 {
 680         struct sdma_engine *sdma = sdmac->sdma;
 681         int channel = sdmac->channel;
 682         u32 chnenbl = chnenbl_ofs(sdma, event);
 683         unsigned long val;
 684
 685         val = readl_relaxed(sdma->regs + chnenbl);
 686         __clear_bit(channel, &val);
 687         writel_relaxed(val, sdma->regs + chnenbl);
 688 }
 689
 690 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
 691 {
 692         return container_of(t, struct sdma_desc, vd.tx);
 693 }
 694
 695 static void sdma_start_desc(struct sdma_channel *sdmac)
 696 {
 697         struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
 698         struct sdma_desc *desc;
 699         struct sdma_engine *sdma = sdmac->sdma;
 700         int channel = sdmac->channel;
 701
 702         if (!vd) {
 703                 sdmac->desc = NULL;
 704                 return;
 705         }
 706         sdmac->desc = desc = to_sdma_desc(&vd->tx);
 707         /*
 708          * Do not delete the node in desc_issued list in cyclic mode, otherwise
 709          * the desc alloced will never be freed in vchan_dma_desc_free_list
 710          */
 711         if (!(sdmac->flags & IMX_DMA_SG_LOOP))
 712                 list_del(&vd->node);
 713
 714         sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
 715         sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
 716         sdma_enable_channel(sdma, sdmac->channel);
 717 }
 718
 719 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 720 {
 721         struct sdma_buffer_descriptor *bd;
 722         int error = 0;
 723         enum dma_status old_status = sdmac->status;
 724
 725         /*
 726          * loop mode. Iterate over descriptors, re-setup them and
 727          * call callback function.
 728          */
 729         while (sdmac->desc) {
 730                 struct sdma_desc *desc = sdmac->desc;
 731
 732                 bd = &desc->bd[desc->buf_tail];
 733
 734                 if (bd->mode.status & BD_DONE)
 735                         break;
 736
 737                 if (bd->mode.status & BD_RROR) {
 738                         bd->mode.status &= ~BD_RROR;
 739                         sdmac->status = DMA_ERROR;
 740                         error = -EIO;
 741                 }
 742
 743                /*
 744                 * We use bd->mode.count to calculate the residue, since contains
 745                 * the number of bytes present in the current buffer descriptor.
 746                 */
 747
 748                 desc->chn_real_count = bd->mode.count;
 749                 bd->mode.status |= BD_DONE;
 750                 bd->mode.count = desc->period_len;
 751                 desc->buf_ptail = desc->buf_tail;
 752                 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
 753
 754                 /*
 755                  * The callback is called from the interrupt context in order
 756                  * to reduce latency and to avoid the risk of altering the
 757                  * SDMA transaction status by the time the client tasklet is
 758                  * executed.
 759                  */
 760                 spin_unlock(&sdmac->vc.lock);
 761                 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
 762                 spin_lock(&sdmac->vc.lock);
 763
 764                 if (error)
 765                         sdmac->status = old_status;
 766         }
 767 }
 768
 769 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
 770 {
 771         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 772         struct sdma_buffer_descriptor *bd;
 773         int i, error = 0;
 774
 775         sdmac->desc->chn_real_count = 0;
 776         /*
 777          * non loop mode. Iterate over all descriptors, collect
 778          * errors and call callback function
 779          */
 780         for (i = 0; i < sdmac->desc->num_bd; i++) {
 781                 bd = &sdmac->desc->bd[i];
 782
 783                  if (bd->mode.status & (BD_DONE | BD_RROR))
 784                         error = -EIO;
 785                  sdmac->desc->chn_real_count += bd->mode.count;
 786         }
 787
 788         if (error)
 789                 sdmac->status = DMA_ERROR;
 790         else
 791                 sdmac->status = DMA_COMPLETE;
 792 }
 793
 794 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 795 {
 796         struct sdma_engine *sdma = dev_id;
 797         unsigned long stat;
 798
 799         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 800         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 801         /* channel 0 is special and not handled here, see run_channel0() */
 802         stat &= ~1;
 803
 804         while (stat) {
 805                 int channel = fls(stat) - 1;
 806                 struct sdma_channel *sdmac = &sdma->channel[channel];
 807                 struct sdma_desc *desc;
 808
 809                 spin_lock(&sdmac->vc.lock);
 810                 desc = sdmac->desc;
 811                 if (desc) {
 812                         if (sdmac->flags & IMX_DMA_SG_LOOP) {
 813                                 sdma_update_channel_loop(sdmac);
 814                         } else {
 815                                 mxc_sdma_handle_channel_normal(sdmac);
 816                                 vchan_cookie_complete(&desc->vd);
 817                                 sdma_start_desc(sdmac);
 818                         }
 819                 }
 820
 821                 spin_unlock(&sdmac->vc.lock);
 822                 __clear_bit(channel, &stat);
 823         }
 824
 825         return IRQ_HANDLED;
 826 }
 827
 828 /*
 829  * sets the pc of SDMA script according to the peripheral type
 830  */
 831 static void sdma_get_pc(struct sdma_channel *sdmac,
 832                 enum sdma_peripheral_type peripheral_type)
 833 {
 834         struct sdma_engine *sdma = sdmac->sdma;
 835         int per_2_emi = 0, emi_2_per = 0;
 836         /*
 837          * These are needed once we start to support transfers between
 838          * two peripherals or memory-to-memory transfers
 839          */
 840         int per_2_per = 0;
 841
 842         sdmac->pc_from_device = 0;
 843         sdmac->pc_to_device = 0;
 844         sdmac->device_to_device = 0;
 845
 846         switch (peripheral_type) {
 847         case IMX_DMATYPE_MEMORY:
 848                 break;
 849         case IMX_DMATYPE_DSP:
 850                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 851                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 852                 break;
 853         case IMX_DMATYPE_FIRI:
 854                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 855                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 856                 break;
 857         case IMX_DMATYPE_UART:
 858                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 859                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 860                 break;
 861         case IMX_DMATYPE_UART_SP:
 862                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 863                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 864                 break;
 865         case IMX_DMATYPE_ATA:
 866                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 867                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 868                 break;
 869         case IMX_DMATYPE_CSPI:
 870         case IMX_DMATYPE_EXT:
 871         case IMX_DMATYPE_SSI:
 872         case IMX_DMATYPE_SAI:
 873                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 874                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 875                 break;
 876         case IMX_DMATYPE_SSI_DUAL:
 877                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 878                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 879                 break;
 880         case IMX_DMATYPE_SSI_SP:
 881         case IMX_DMATYPE_MMC:
 882         case IMX_DMATYPE_SDHC:
 883         case IMX_DMATYPE_CSPI_SP:
 884         case IMX_DMATYPE_ESAI:
 885         case IMX_DMATYPE_MSHC_SP:
 886                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 887                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 888                 break;
 889         case IMX_DMATYPE_ASRC:
 890                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 891                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 892                 per_2_per = sdma->script_addrs->per_2_per_addr;
 893                 break;
 894         case IMX_DMATYPE_ASRC_SP:
 895                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 896                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 897                 per_2_per = sdma->script_addrs->per_2_per_addr;
 898                 break;
 899         case IMX_DMATYPE_MSHC:
 900                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 901                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 902                 break;
 903         case IMX_DMATYPE_CCM:
 904                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 905                 break;
 906         case IMX_DMATYPE_SPDIF:
 907                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 908                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 909                 break;
 910         case IMX_DMATYPE_IPU_MEMORY:
 911                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 912                 break;
 913         default:
 914                 break;
 915         }
 916
 917         sdmac->pc_from_device = per_2_emi;
 918         sdmac->pc_to_device = emi_2_per;
 919         sdmac->device_to_device = per_2_per;
 920 }
 921
 922 static int sdma_load_context(struct sdma_channel *sdmac)
 923 {
 924         struct sdma_engine *sdma = sdmac->sdma;
 925         int channel = sdmac->channel;
 926         int load_address;
 927         struct sdma_context_data *context = sdma->context;
 928         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 929         int ret;
 930         unsigned long flags;
 931
 932         if (sdmac->direction == DMA_DEV_TO_MEM)
 933                 load_address = sdmac->pc_from_device;
 934         else if (sdmac->direction == DMA_DEV_TO_DEV)
 935                 load_address = sdmac->device_to_device;
 936         else
 937                 load_address = sdmac->pc_to_device;
 938
 939         if (load_address < 0)
 940                 return load_address;
 941
 942         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 943         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 944         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 945         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 946         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 947         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 948
 949         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 950
 951         memset(context, 0, sizeof(*context));
 952         context->channel_state.pc = load_address;
 953
 954         /* Send by context the event mask,base address for peripheral
 955          * and watermark level
 956          */
 957         context->gReg[0] = sdmac->event_mask[1];
 958         context->gReg[1] = sdmac->event_mask[0];
 959         context->gReg[2] = sdmac->per_addr;
 960         context->gReg[6] = sdmac->shp_addr;
 961         context->gReg[7] = sdmac->watermark_level;
 962
 963         bd0->mode.command = C0_SETDM;
 964         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 965         bd0->mode.count = sizeof(*context) / 4;
 966         bd0->buffer_addr = sdma->context_phys;
 967         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 968         ret = sdma_run_channel0(sdma);
 969
 970         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 971
 972         return ret;
 973 }
 974
 975 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 976 {
 977         return container_of(chan, struct sdma_channel, vc.chan);
 978 }
 979
 980 static int sdma_disable_channel(struct dma_chan *chan)
 981 {
 982         struct sdma_channel *sdmac = to_sdma_chan(chan);
 983         struct sdma_engine *sdma = sdmac->sdma;
 984         int channel = sdmac->channel;
 985
 986         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 987         sdmac->status = DMA_ERROR;
 988
 989         return 0;
 990 }
 991
 992 static int sdma_disable_channel_with_delay(struct dma_chan *chan)
 993 {
 994         struct sdma_channel *sdmac = to_sdma_chan(chan);
 995         unsigned long flags;
 996         LIST_HEAD(head);
 997
 998         sdma_disable_channel(chan);
 999         spin_lock_irqsave(&sdmac->vc.lock, flags);
1000         vchan_get_all_descriptors(&sdmac->vc, &head);
1001         sdmac->desc = NULL;
1002         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1003         vchan_dma_desc_free_list(&sdmac->vc, &head);
1004
1005         /*
1006          * According to NXP R&D team a delay of one BD SDMA cost time
1007          * (maximum is 1ms) should be added after disable of the channel
1008          * bit, to ensure SDMA core has really been stopped after SDMA
1009          * clients call .device_terminate_all.
1010          */
1011         mdelay(1);
1012
1013         return 0;
1014 }
1015
1016 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1017 {
1018         struct sdma_engine *sdma = sdmac->sdma;
1019
1020         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1021         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1022
1023         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1024         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1025
1026         if (sdmac->event_id0 > 31)
1027                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1028
1029         if (sdmac->event_id1 > 31)
1030                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1031
1032         /*
1033          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1034          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1035          * r0(event_mask[1]) and r1(event_mask[0]).
1036          */
1037         if (lwml > hwml) {
1038                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1039                                                 SDMA_WATERMARK_LEVEL_HWML);
1040                 sdmac->watermark_level |= hwml;
1041                 sdmac->watermark_level |= lwml << 16;
1042                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1043         }
1044
1045         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1046                         sdmac->per_address2 <= sdma->spba_end_addr)
1047                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1048
1049         if (sdmac->per_address >= sdma->spba_start_addr &&
1050                         sdmac->per_address <= sdma->spba_end_addr)
1051                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1052
1053         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1054 }
1055
1056 static int sdma_config_channel(struct dma_chan *chan)
1057 {
1058         struct sdma_channel *sdmac = to_sdma_chan(chan);
1059         int ret;
1060
1061         sdma_disable_channel(chan);
1062
1063         sdmac->event_mask[0] = 0;
1064         sdmac->event_mask[1] = 0;
1065         sdmac->shp_addr = 0;
1066         sdmac->per_addr = 0;
1067
1068         if (sdmac->event_id0) {
1069                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1070                         return -EINVAL;
1071                 sdma_event_enable(sdmac, sdmac->event_id0);
1072         }
1073
1074         if (sdmac->event_id1) {
1075                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1076                         return -EINVAL;
1077                 sdma_event_enable(sdmac, sdmac->event_id1);
1078         }
1079
1080         switch (sdmac->peripheral_type) {
1081         case IMX_DMATYPE_DSP:
1082                 sdma_config_ownership(sdmac, false, true, true);
1083                 break;
1084         case IMX_DMATYPE_MEMORY:
1085                 sdma_config_ownership(sdmac, false, true, false);
1086                 break;
1087         default:
1088                 sdma_config_ownership(sdmac, true, true, false);
1089                 break;
1090         }
1091
1092         sdma_get_pc(sdmac, sdmac->peripheral_type);
1093
1094         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1095                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1096                 /* Handle multiple event channels differently */
1097                 if (sdmac->event_id1) {
1098                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1099                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1100                                 sdma_set_watermarklevel_for_p2p(sdmac);
1101                 } else
1102                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1103
1104                 /* Address */
1105                 sdmac->shp_addr = sdmac->per_address;
1106                 sdmac->per_addr = sdmac->per_address2;
1107         } else {
1108                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1109         }
1110
1111         ret = sdma_load_context(sdmac);
1112
1113         return ret;
1114 }
1115
1116 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1117                 unsigned int priority)
1118 {
1119         struct sdma_engine *sdma = sdmac->sdma;
1120         int channel = sdmac->channel;
1121
1122         if (priority < MXC_SDMA_MIN_PRIORITY
1123             || priority > MXC_SDMA_MAX_PRIORITY) {
1124                 return -EINVAL;
1125         }
1126
1127         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1128
1129         return 0;
1130 }
1131
1132 static int sdma_request_channel0(struct sdma_engine *sdma)
1133 {
1134         int ret = -EBUSY;
1135
1136         sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
1137                                         GFP_NOWAIT);
1138         if (!sdma->bd0) {
1139                 ret = -ENOMEM;
1140                 goto out;
1141         }
1142
1143         sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1144         sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1145
1146         sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1147         return 0;
1148 out:
1149
1150         return ret;
1151 }
1152
1153
1154 static int sdma_alloc_bd(struct sdma_desc *desc)
1155 {
1156         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1157         int ret = 0;
1158
1159         desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys,
1160                                         GFP_ATOMIC);
1161         if (!desc->bd) {
1162                 ret = -ENOMEM;
1163                 goto out;
1164         }
1165 out:
1166         return ret;
1167 }
1168
1169 static void sdma_free_bd(struct sdma_desc *desc)
1170 {
1171         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1172
1173         dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
1174 }
1175
1176 static void sdma_desc_free(struct virt_dma_desc *vd)
1177 {
1178         struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1179
1180         sdma_free_bd(desc);
1181         kfree(desc);
1182 }
1183
1184 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1185 {
1186         struct sdma_channel *sdmac = to_sdma_chan(chan);
1187         struct imx_dma_data *data = chan->private;
1188         int prio, ret;
1189
1190         if (!data)
1191                 return -EINVAL;
1192
1193         switch (data->priority) {
1194         case DMA_PRIO_HIGH:
1195                 prio = 3;
1196                 break;
1197         case DMA_PRIO_MEDIUM:
1198                 prio = 2;
1199                 break;
1200         case DMA_PRIO_LOW:
1201         default:
1202                 prio = 1;
1203                 break;
1204         }
1205
1206         sdmac->peripheral_type = data->peripheral_type;
1207         sdmac->event_id0 = data->dma_request;
1208         sdmac->event_id1 = data->dma_request2;
1209
1210         ret = clk_enable(sdmac->sdma->clk_ipg);
1211         if (ret)
1212                 return ret;
1213         ret = clk_enable(sdmac->sdma->clk_ahb);
1214         if (ret)
1215                 goto disable_clk_ipg;
1216
1217         ret = sdma_set_channel_priority(sdmac, prio);
1218         if (ret)
1219                 goto disable_clk_ahb;
1220
1221         return 0;
1222
1223 disable_clk_ahb:
1224         clk_disable(sdmac->sdma->clk_ahb);
1225 disable_clk_ipg:
1226         clk_disable(sdmac->sdma->clk_ipg);
1227         return ret;
1228 }
1229
1230 static void sdma_free_chan_resources(struct dma_chan *chan)
1231 {
1232         struct sdma_channel *sdmac = to_sdma_chan(chan);
1233         struct sdma_engine *sdma = sdmac->sdma;
1234
1235         sdma_disable_channel_with_delay(chan);
1236
1237         if (sdmac->event_id0)
1238                 sdma_event_disable(sdmac, sdmac->event_id0);
1239         if (sdmac->event_id1)
1240                 sdma_event_disable(sdmac, sdmac->event_id1);
1241
1242         sdmac->event_id0 = 0;
1243         sdmac->event_id1 = 0;
1244
1245         sdma_set_channel_priority(sdmac, 0);
1246
1247         clk_disable(sdma->clk_ipg);
1248         clk_disable(sdma->clk_ahb);
1249 }
1250
1251 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1252                 struct dma_chan *chan, struct scatterlist *sgl,
1253                 unsigned int sg_len, enum dma_transfer_direction direction,
1254                 unsigned long flags, void *context)
1255 {
1256         struct sdma_channel *sdmac = to_sdma_chan(chan);
1257         struct sdma_engine *sdma = sdmac->sdma;
1258         int ret, i, count;
1259         int channel = sdmac->channel;
1260         struct scatterlist *sg;
1261         struct sdma_desc *desc;
1262
1263         if (sdmac->status == DMA_IN_PROGRESS)
1264                 return NULL;
1265         sdmac->status = DMA_IN_PROGRESS;
1266
1267         sdmac->flags = 0;
1268
1269         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1270         if (!desc)
1271                 goto err_out;
1272
1273         desc->buf_tail = 0;
1274         desc->buf_ptail = 0;
1275         desc->sdmac = sdmac;
1276         desc->num_bd = sg_len;
1277         desc->chn_real_count = 0;
1278
1279         if (sdma_alloc_bd(desc)) {
1280                 kfree(desc);
1281                 goto err_out;
1282         }
1283
1284         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1285                         sg_len, channel);
1286
1287         sdmac->direction = direction;
1288         ret = sdma_load_context(sdmac);
1289         if (ret)
1290                 goto err_bd_out;
1291
1292         desc->chn_count = 0;
1293         for_each_sg(sgl, sg, sg_len, i) {
1294                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1295                 int param;
1296
1297                 bd->buffer_addr = sg->dma_address;
1298
1299                 count = sg_dma_len(sg);
1300
1301                 if (count > 0xffff) {
1302                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1303                                         channel, count, 0xffff);
1304                         ret = -EINVAL;
1305                         goto err_bd_out;
1306                 }
1307
1308                 bd->mode.count = count;
1309                 desc->chn_count += count;
1310
1311                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1312                         ret =  -EINVAL;
1313                         goto err_bd_out;
1314                 }
1315
1316                 switch (sdmac->word_size) {
1317                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1318                         bd->mode.command = 0;
1319                         if (count & 3 || sg->dma_address & 3)
1320                                 goto err_bd_out;
1321                         break;
1322                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1323                         bd->mode.command = 2;
1324                         if (count & 1 || sg->dma_address & 1)
1325                                 goto err_bd_out;
1326                         break;
1327                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1328                         bd->mode.command = 1;
1329                         break;
1330                 default:
1331                         goto err_bd_out;
1332                 }
1333
1334                 param = BD_DONE | BD_EXTD | BD_CONT;
1335
1336                 if (i + 1 == sg_len) {
1337                         param |= BD_INTR;
1338                         param |= BD_LAST;
1339                         param &= ~BD_CONT;
1340                 }
1341
1342                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1343                                 i, count, (u64)sg->dma_address,
1344                                 param & BD_WRAP ? "wrap" : "",
1345                                 param & BD_INTR ? " intr" : "");
1346
1347                 bd->mode.status = param;
1348         }
1349
1350         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1351 err_bd_out:
1352         sdma_free_bd(desc);
1353         kfree(desc);
1354 err_out:
1355         sdmac->status = DMA_ERROR;
1356         return NULL;
1357 }
1358
1359 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1360                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1361                 size_t period_len, enum dma_transfer_direction direction,
1362                 unsigned long flags)
1363 {
1364         struct sdma_channel *sdmac = to_sdma_chan(chan);
1365         struct sdma_engine *sdma = sdmac->sdma;
1366         int num_periods = buf_len / period_len;
1367         int channel = sdmac->channel;
1368         int ret, i = 0, buf = 0;
1369         struct sdma_desc *desc;
1370
1371         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1372
1373         if (sdmac->status == DMA_IN_PROGRESS)
1374                 return NULL;
1375
1376         sdmac->status = DMA_IN_PROGRESS;
1377
1378         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1379         if (!desc)
1380                 goto err_out;
1381
1382         desc->buf_tail = 0;
1383         desc->buf_ptail = 0;
1384         desc->sdmac = sdmac;
1385         desc->num_bd = num_periods;
1386         desc->chn_real_count = 0;
1387         desc->period_len = period_len;
1388
1389         sdmac->flags |= IMX_DMA_SG_LOOP;
1390         sdmac->direction = direction;
1391
1392         if (sdma_alloc_bd(desc)) {
1393                 kfree(desc);
1394                 goto err_bd_out;
1395         }
1396
1397         ret = sdma_load_context(sdmac);
1398         if (ret)
1399                 goto err_bd_out;
1400
1401         if (period_len > 0xffff) {
1402                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1403                                 channel, period_len, 0xffff);
1404                 goto err_bd_out;
1405         }
1406
1407         while (buf < buf_len) {
1408                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1409                 int param;
1410
1411                 bd->buffer_addr = dma_addr;
1412
1413                 bd->mode.count = period_len;
1414
1415                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1416                         goto err_bd_out;
1417                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1418                         bd->mode.command = 0;
1419                 else
1420                         bd->mode.command = sdmac->word_size;
1421
1422                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1423                 if (i + 1 == num_periods)
1424                         param |= BD_WRAP;
1425
1426                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1427                                 i, period_len, (u64)dma_addr,
1428                                 param & BD_WRAP ? "wrap" : "",
1429                                 param & BD_INTR ? " intr" : "");
1430
1431                 bd->mode.status = param;
1432
1433                 dma_addr += period_len;
1434                 buf += period_len;
1435
1436                 i++;
1437         }
1438
1439         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1440 err_bd_out:
1441         sdma_free_bd(desc);
1442         kfree(desc);
1443 err_out:
1444         sdmac->status = DMA_ERROR;
1445         return NULL;
1446 }
1447
1448 static int sdma_config(struct dma_chan *chan,
1449                        struct dma_slave_config *dmaengine_cfg)
1450 {
1451         struct sdma_channel *sdmac = to_sdma_chan(chan);
1452
1453         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1454                 sdmac->per_address = dmaengine_cfg->src_addr;
1455                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1456                         dmaengine_cfg->src_addr_width;
1457                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1458         } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1459                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1460                 sdmac->per_address = dmaengine_cfg->dst_addr;
1461                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1462                         SDMA_WATERMARK_LEVEL_LWML;
1463                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1464                         SDMA_WATERMARK_LEVEL_HWML;
1465                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1466         } else {
1467                 sdmac->per_address = dmaengine_cfg->dst_addr;
1468                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1469                         dmaengine_cfg->dst_addr_width;
1470                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1471         }
1472         sdmac->direction = dmaengine_cfg->direction;
1473         return sdma_config_channel(chan);
1474 }
1475
1476 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1477                                       dma_cookie_t cookie,
1478                                       struct dma_tx_state *txstate)
1479 {
1480         struct sdma_channel *sdmac = to_sdma_chan(chan);
1481         struct sdma_desc *desc;
1482         u32 residue;
1483         struct virt_dma_desc *vd;
1484         enum dma_status ret;
1485         unsigned long flags;
1486
1487         ret = dma_cookie_status(chan, cookie, txstate);
1488         if (ret == DMA_COMPLETE || !txstate)
1489                 return ret;
1490
1491         spin_lock_irqsave(&sdmac->vc.lock, flags);
1492         vd = vchan_find_desc(&sdmac->vc, cookie);
1493         if (vd) {
1494                 desc = to_sdma_desc(&vd->tx);
1495                 if (sdmac->flags & IMX_DMA_SG_LOOP)
1496                         residue = (desc->num_bd - desc->buf_ptail) *
1497                                 desc->period_len - desc->chn_real_count;
1498                 else
1499                         residue = desc->chn_count - desc->chn_real_count;
1500         } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1501                 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1502         } else {
1503                 residue = 0;
1504         }
1505         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1506
1507         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1508                          residue);
1509
1510         return sdmac->status;
1511 }
1512
1513 static void sdma_issue_pending(struct dma_chan *chan)
1514 {
1515         struct sdma_channel *sdmac = to_sdma_chan(chan);
1516         unsigned long flags;
1517
1518         spin_lock_irqsave(&sdmac->vc.lock, flags);
1519         if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1520                 sdma_start_desc(sdmac);
1521         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1522 }
1523
1524 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1525 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1526 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1527 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1528
1529 static void sdma_add_scripts(struct sdma_engine *sdma,
1530                 const struct sdma_script_start_addrs *addr)
1531 {
1532         s32 *addr_arr = (u32 *)addr;
1533         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1534         int i;
1535
1536         /* use the default firmware in ROM if missing external firmware */
1537         if (!sdma->script_number)
1538                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1539
1540         for (i = 0; i < sdma->script_number; i++)
1541                 if (addr_arr[i] > 0)
1542                         saddr_arr[i] = addr_arr[i];
1543 }
1544
1545 static void sdma_load_firmware(const struct firmware *fw, void *context)
1546 {
1547         struct sdma_engine *sdma = context;
1548         const struct sdma_firmware_header *header;
1549         const struct sdma_script_start_addrs *addr;
1550         unsigned short *ram_code;
1551
1552         if (!fw) {
1553                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1554                 /* In this case we just use the ROM firmware. */
1555                 return;
1556         }
1557
1558         if (fw->size < sizeof(*header))
1559                 goto err_firmware;
1560
1561         header = (struct sdma_firmware_header *)fw->data;
1562
1563         if (header->magic != SDMA_FIRMWARE_MAGIC)
1564                 goto err_firmware;
1565         if (header->ram_code_start + header->ram_code_size > fw->size)
1566                 goto err_firmware;
1567         switch (header->version_major) {
1568         case 1:
1569                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1570                 break;
1571         case 2:
1572                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1573                 break;
1574         case 3:
1575                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1576                 break;
1577         case 4:
1578                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1579                 break;
1580         default:
1581                 dev_err(sdma->dev, "unknown firmware version\n");
1582                 goto err_firmware;
1583         }
1584
1585         addr = (void *)header + header->script_addrs_start;
1586         ram_code = (void *)header + header->ram_code_start;
1587
1588         clk_enable(sdma->clk_ipg);
1589         clk_enable(sdma->clk_ahb);
1590         /* download the RAM image for SDMA */
1591         sdma_load_script(sdma, ram_code,
1592                         header->ram_code_size,
1593                         addr->ram_code_start_addr);
1594         clk_disable(sdma->clk_ipg);
1595         clk_disable(sdma->clk_ahb);
1596
1597         sdma_add_scripts(sdma, addr);
1598
1599         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1600                         header->version_major,
1601                         header->version_minor);
1602
1603 err_firmware:
1604         release_firmware(fw);
1605 }
1606
1607 #define EVENT_REMAP_CELLS 3
1608
1609 static int sdma_event_remap(struct sdma_engine *sdma)
1610 {
1611         struct device_node *np = sdma->dev->of_node;
1612         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1613         struct property *event_remap;
1614         struct regmap *gpr;
1615         char propname[] = "fsl,sdma-event-remap";
1616         u32 reg, val, shift, num_map, i;
1617         int ret = 0;
1618
1619         if (IS_ERR(np) || IS_ERR(gpr_np))
1620                 goto out;
1621
1622         event_remap = of_find_property(np, propname, NULL);
1623         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1624         if (!num_map) {
1625                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1626                 goto out;
1627         } else if (num_map % EVENT_REMAP_CELLS) {
1628                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1629                                 propname, EVENT_REMAP_CELLS);
1630                 ret = -EINVAL;
1631                 goto out;
1632         }
1633
1634         gpr = syscon_node_to_regmap(gpr_np);
1635         if (IS_ERR(gpr)) {
1636                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1637                 ret = PTR_ERR(gpr);
1638                 goto out;
1639         }
1640
1641         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1642                 ret = of_property_read_u32_index(np, propname, i, &reg);
1643                 if (ret) {
1644                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1645                                         propname, i);
1646                         goto out;
1647                 }
1648
1649                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1650                 if (ret) {
1651                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1652                                         propname, i + 1);
1653                         goto out;
1654                 }
1655
1656                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1657                 if (ret) {
1658                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1659                                         propname, i + 2);
1660                         goto out;
1661                 }
1662
1663                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1664         }
1665
1666 out:
1667         if (!IS_ERR(gpr_np))
1668                 of_node_put(gpr_np);
1669
1670         return ret;
1671 }
1672
1673 static int sdma_get_firmware(struct sdma_engine *sdma,
1674                 const char *fw_name)
1675 {
1676         int ret;
1677
1678         ret = request_firmware_nowait(THIS_MODULE,
1679                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1680                         GFP_KERNEL, sdma, sdma_load_firmware);
1681
1682         return ret;
1683 }
1684
1685 static int sdma_init(struct sdma_engine *sdma)
1686 {
1687         int i, ret;
1688         dma_addr_t ccb_phys;
1689
1690         ret = clk_enable(sdma->clk_ipg);
1691         if (ret)
1692                 return ret;
1693         ret = clk_enable(sdma->clk_ahb);
1694         if (ret)
1695                 goto disable_clk_ipg;
1696
1697         /* Be sure SDMA has not started yet */
1698         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1699
1700         sdma->channel_control = dma_alloc_coherent(NULL,
1701                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1702                         sizeof(struct sdma_context_data),
1703                         &ccb_phys, GFP_KERNEL);
1704
1705         if (!sdma->channel_control) {
1706                 ret = -ENOMEM;
1707                 goto err_dma_alloc;
1708         }
1709
1710         sdma->context = (void *)sdma->channel_control +
1711                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1712         sdma->context_phys = ccb_phys +
1713                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1714
1715         /* Zero-out the CCB structures array just allocated */
1716         memset(sdma->channel_control, 0,
1717                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1718
1719         /* disable all channels */
1720         for (i = 0; i < sdma->drvdata->num_events; i++)
1721                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1722
1723         /* All channels have priority 0 */
1724         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1725                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1726
1727         ret = sdma_request_channel0(sdma);
1728         if (ret)
1729                 goto err_dma_alloc;
1730
1731         sdma_config_ownership(&sdma->channel[0], false, true, false);
1732
1733         /* Set Command Channel (Channel Zero) */
1734         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1735
1736         /* Set bits of CONFIG register but with static context switching */
1737         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1738         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1739
1740         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1741
1742         /* Initializes channel's priorities */
1743         sdma_set_channel_priority(&sdma->channel[0], 7);
1744
1745         clk_disable(sdma->clk_ipg);
1746         clk_disable(sdma->clk_ahb);
1747
1748         return 0;
1749
1750 err_dma_alloc:
1751         clk_disable(sdma->clk_ahb);
1752 disable_clk_ipg:
1753         clk_disable(sdma->clk_ipg);
1754         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1755         return ret;
1756 }
1757
1758 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1759 {
1760         struct sdma_channel *sdmac = to_sdma_chan(chan);
1761         struct imx_dma_data *data = fn_param;
1762
1763         if (!imx_dma_is_general_purpose(chan))
1764                 return false;
1765
1766         sdmac->data = *data;
1767         chan->private = &sdmac->data;
1768
1769         return true;
1770 }
1771
1772 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1773                                    struct of_dma *ofdma)
1774 {
1775         struct sdma_engine *sdma = ofdma->of_dma_data;
1776         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1777         struct imx_dma_data data;
1778
1779         if (dma_spec->args_count != 3)
1780                 return NULL;
1781
1782         data.dma_request = dma_spec->args[0];
1783         data.peripheral_type = dma_spec->args[1];
1784         data.priority = dma_spec->args[2];
1785         /*
1786          * init dma_request2 to zero, which is not used by the dts.
1787          * For P2P, dma_request2 is init from dma_request_channel(),
1788          * chan->private will point to the imx_dma_data, and in
1789          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1790          * be set to sdmac->event_id1.
1791          */
1792         data.dma_request2 = 0;
1793
1794         return dma_request_channel(mask, sdma_filter_fn, &data);
1795 }
1796
1797 static int sdma_probe(struct platform_device *pdev)
1798 {
1799         const struct of_device_id *of_id =
1800                         of_match_device(sdma_dt_ids, &pdev->dev);
1801         struct device_node *np = pdev->dev.of_node;
1802         struct device_node *spba_bus;
1803         const char *fw_name;
1804         int ret;
1805         int irq;
1806         struct resource *iores;
1807         struct resource spba_res;
1808         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1809         int i;
1810         struct sdma_engine *sdma;
1811         s32 *saddr_arr;
1812         const struct sdma_driver_data *drvdata = NULL;
1813
1814         if (of_id)
1815                 drvdata = of_id->data;
1816         else if (pdev->id_entry)
1817                 drvdata = (void *)pdev->id_entry->driver_data;
1818
1819         if (!drvdata) {
1820                 dev_err(&pdev->dev, "unable to find driver data\n");
1821                 return -EINVAL;
1822         }
1823
1824         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1825         if (ret)
1826                 return ret;
1827
1828         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1829         if (!sdma)
1830                 return -ENOMEM;
1831
1832         spin_lock_init(&sdma->channel_0_lock);
1833
1834         sdma->dev = &pdev->dev;
1835         sdma->drvdata = drvdata;
1836
1837         irq = platform_get_irq(pdev, 0);
1838         if (irq < 0)
1839                 return irq;
1840
1841         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1842         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1843         if (IS_ERR(sdma->regs))
1844                 return PTR_ERR(sdma->regs);
1845
1846         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1847         if (IS_ERR(sdma->clk_ipg))
1848                 return PTR_ERR(sdma->clk_ipg);
1849
1850         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1851         if (IS_ERR(sdma->clk_ahb))
1852                 return PTR_ERR(sdma->clk_ahb);
1853
1854         ret = clk_prepare(sdma->clk_ipg);
1855         if (ret)
1856                 return ret;
1857
1858         ret = clk_prepare(sdma->clk_ahb);
1859         if (ret)
1860                 goto err_clk;
1861
1862         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1863                                sdma);
1864         if (ret)
1865                 goto err_irq;
1866
1867         sdma->irq = irq;
1868
1869         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1870         if (!sdma->script_addrs) {
1871                 ret = -ENOMEM;
1872                 goto err_irq;
1873         }
1874
1875         /* initially no scripts available */
1876         saddr_arr = (s32 *)sdma->script_addrs;
1877         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1878                 saddr_arr[i] = -EINVAL;
1879
1880         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1881         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1882
1883         INIT_LIST_HEAD(&sdma->dma_device.channels);
1884         /* Initialize channel parameters */
1885         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1886                 struct sdma_channel *sdmac = &sdma->channel[i];
1887
1888                 sdmac->sdma = sdma;
1889
1890                 sdmac->channel = i;
1891                 sdmac->vc.desc_free = sdma_desc_free;
1892                 /*
1893                  * Add the channel to the DMAC list. Do not add channel 0 though
1894                  * because we need it internally in the SDMA driver. This also means
1895                  * that channel 0 in dmaengine counting matches sdma channel 1.
1896                  */
1897                 if (i)
1898                         vchan_init(&sdmac->vc, &sdma->dma_device);
1899         }
1900
1901         ret = sdma_init(sdma);
1902         if (ret)
1903                 goto err_init;
1904
1905         ret = sdma_event_remap(sdma);
1906         if (ret)
1907                 goto err_init;
1908
1909         if (sdma->drvdata->script_addrs)
1910                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1911         if (pdata && pdata->script_addrs)
1912                 sdma_add_scripts(sdma, pdata->script_addrs);
1913
1914         if (pdata) {
1915                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1916                 if (ret)
1917                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1918         } else {
1919                 /*
1920                  * Because that device tree does not encode ROM script address,
1921                  * the RAM script in firmware is mandatory for device tree
1922                  * probe, otherwise it fails.
1923                  */
1924                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1925                                               &fw_name);
1926                 if (ret)
1927                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1928                 else {
1929                         ret = sdma_get_firmware(sdma, fw_name);
1930                         if (ret)
1931                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1932                 }
1933         }
1934
1935         sdma->dma_device.dev = &pdev->dev;
1936
1937         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1938         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1939         sdma->dma_device.device_tx_status = sdma_tx_status;
1940         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1941         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1942         sdma->dma_device.device_config = sdma_config;
1943         sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
1944         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
1945         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
1946         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
1947         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1948         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1949         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1950         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1951
1952         platform_set_drvdata(pdev, sdma);
1953
1954         ret = dma_async_device_register(&sdma->dma_device);
1955         if (ret) {
1956                 dev_err(&pdev->dev, "unable to register\n");
1957                 goto err_init;
1958         }
1959
1960         if (np) {
1961                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1962                 if (ret) {
1963                         dev_err(&pdev->dev, "failed to register controller\n");
1964                         goto err_register;
1965                 }
1966
1967                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1968                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1969                 if (!ret) {
1970                         sdma->spba_start_addr = spba_res.start;
1971                         sdma->spba_end_addr = spba_res.end;
1972                 }
1973                 of_node_put(spba_bus);
1974         }
1975
1976         return 0;
1977
1978 err_register:
1979         dma_async_device_unregister(&sdma->dma_device);
1980 err_init:
1981         kfree(sdma->script_addrs);
1982 err_irq:
1983         clk_unprepare(sdma->clk_ahb);
1984 err_clk:
1985         clk_unprepare(sdma->clk_ipg);
1986         return ret;
1987 }
1988
1989 static int sdma_remove(struct platform_device *pdev)
1990 {
1991         struct sdma_engine *sdma = platform_get_drvdata(pdev);
1992         int i;
1993
1994         devm_free_irq(&pdev->dev, sdma->irq, sdma);
1995         dma_async_device_unregister(&sdma->dma_device);
1996         kfree(sdma->script_addrs);
1997         clk_unprepare(sdma->clk_ahb);
1998         clk_unprepare(sdma->clk_ipg);
1999         /* Kill the tasklet */
2000         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2001                 struct sdma_channel *sdmac = &sdma->channel[i];
2002
2003                 tasklet_kill(&sdmac->vc.task);
2004                 sdma_free_chan_resources(&sdmac->vc.chan);
2005         }
2006
2007         platform_set_drvdata(pdev, NULL);
2008         return 0;
2009 }
2010
2011 static struct platform_driver sdma_driver = {
2012         .driver         = {
2013                 .name   = "imx-sdma",
2014                 .of_match_table = sdma_dt_ids,
2015         },
2016         .id_table       = sdma_devtypes,
2017         .remove         = sdma_remove,
2018         .probe          = sdma_probe,
2019 };
2020
2021 module_platform_driver(sdma_driver);
2022
2023 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2024 MODULE_DESCRIPTION("i.MX SDMA driver");
2025 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2026 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2027 #endif
2028 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2029 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2030 #endif
2031 MODULE_LICENSE("GPL");