drivers/dma/imx-sdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-sdma.c
   4 //
   5 // This file contains a driver for the Freescale Smart DMA engine
   6 //
   7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8 //
   9 // Based on code from Freescale:
  10 //
  11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  12
  13 #include <linux/init.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mm.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firmware.h>
  28 #include <linux/slab.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_dma.h>
  35
  36 #include <asm/irq.h>
  37 #include <linux/platform_data/dma-imx-sdma.h>
  38 #include <linux/platform_data/dma-imx.h>
  39 #include <linux/regmap.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  42
  43 #include "dmaengine.h"
  44 #include "virt-dma.h"
  45
  46 /* SDMA registers */
  47 #define SDMA_H_C0PTR            0x000
  48 #define SDMA_H_INTR             0x004
  49 #define SDMA_H_STATSTOP         0x008
  50 #define SDMA_H_START            0x00c
  51 #define SDMA_H_EVTOVR           0x010
  52 #define SDMA_H_DSPOVR           0x014
  53 #define SDMA_H_HOSTOVR          0x018
  54 #define SDMA_H_EVTPEND          0x01c
  55 #define SDMA_H_DSPENBL          0x020
  56 #define SDMA_H_RESET            0x024
  57 #define SDMA_H_EVTERR           0x028
  58 #define SDMA_H_INTRMSK          0x02c
  59 #define SDMA_H_PSW              0x030
  60 #define SDMA_H_EVTERRDBG        0x034
  61 #define SDMA_H_CONFIG           0x038
  62 #define SDMA_ONCE_ENB           0x040
  63 #define SDMA_ONCE_DATA          0x044
  64 #define SDMA_ONCE_INSTR         0x048
  65 #define SDMA_ONCE_STAT          0x04c
  66 #define SDMA_ONCE_CMD           0x050
  67 #define SDMA_EVT_MIRROR         0x054
  68 #define SDMA_ILLINSTADDR        0x058
  69 #define SDMA_CHN0ADDR           0x05c
  70 #define SDMA_ONCE_RTB           0x060
  71 #define SDMA_XTRIG_CONF1        0x070
  72 #define SDMA_XTRIG_CONF2        0x074
  73 #define SDMA_CHNENBL0_IMX35     0x200
  74 #define SDMA_CHNENBL0_IMX31     0x080
  75 #define SDMA_CHNPRI_0           0x100
  76
  77 /*
  78  * Buffer descriptor status values.
  79  */
  80 #define BD_DONE  0x01
  81 #define BD_WRAP  0x02
  82 #define BD_CONT  0x04
  83 #define BD_INTR  0x08
  84 #define BD_RROR  0x10
  85 #define BD_LAST  0x20
  86 #define BD_EXTD  0x80
  87
  88 /*
  89  * Data Node descriptor status values.
  90  */
  91 #define DND_END_OF_FRAME  0x80
  92 #define DND_END_OF_XFER   0x40
  93 #define DND_DONE          0x20
  94 #define DND_UNUSED        0x01
  95
  96 /*
  97  * IPCV2 descriptor status values.
  98  */
  99 #define BD_IPCV2_END_OF_FRAME  0x40
 100
 101 #define IPCV2_MAX_NODES        50
 102 /*
 103  * Error bit set in the CCB status field by the SDMA,
 104  * in setbd routine, in case of a transfer error
 105  */
 106 #define DATA_ERROR  0x10000000
 107
 108 /*
 109  * Buffer descriptor commands.
 110  */
 111 #define C0_ADDR             0x01
 112 #define C0_LOAD             0x02
 113 #define C0_DUMP             0x03
 114 #define C0_SETCTX           0x07
 115 #define C0_GETCTX           0x03
 116 #define C0_SETDM            0x01
 117 #define C0_SETPM            0x04
 118 #define C0_GETDM            0x02
 119 #define C0_GETPM            0x08
 120 /*
 121  * Change endianness indicator in the BD command field
 122  */
 123 #define CHANGE_ENDIANNESS   0x80
 124
 125 /*
 126  *  p_2_p watermark_level description
 127  *      Bits            Name                    Description
 128  *      0-7             Lower WML               Lower watermark level
 129  *      8               PS                      1: Pad Swallowing
 130  *                                              0: No Pad Swallowing
 131  *      9               PA                      1: Pad Adding
 132  *                                              0: No Pad Adding
 133  *      10              SPDIF                   If this bit is set both source
 134  *                                              and destination are on SPBA
 135  *      11              Source Bit(SP)          1: Source on SPBA
 136  *                                              0: Source on AIPS
 137  *      12              Destination Bit(DP)     1: Destination on SPBA
 138  *                                              0: Destination on AIPS
 139  *      13-15           ---------               MUST BE 0
 140  *      16-23           Higher WML              HWML
 141  *      24-27           N                       Total number of samples after
 142  *                                              which Pad adding/Swallowing
 143  *                                              must be done. It must be odd.
 144  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 145  *                                              LWML event mask
 146  *                                              0: LWE in EVENTS register
 147  *                                              1: LWE in EVENTS2 register
 148  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 149  *                                              HWML event mask
 150  *                                              0: HWE in EVENTS register
 151  *                                              1: HWE in EVENTS2 register
 152  *      30              ---------               MUST BE 0
 153  *      31              CONT                    1: Amount of samples to be
 154  *                                              transferred is unknown and
 155  *                                              script will keep on
 156  *                                              transferring samples as long as
 157  *                                              both events are detected and
 158  *                                              script must be manually stopped
 159  *                                              by the application
 160  *                                              0: The amount of samples to be
 161  *                                              transferred is equal to the
 162  *                                              count field of mode word
 163  */
 164 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 165 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 166 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 167 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 168 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 169 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 170 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 171 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 172 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 173 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 174
 175 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 176                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 177                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 178
 179 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 180                                  BIT(DMA_MEM_TO_DEV) | \
 181                                  BIT(DMA_DEV_TO_DEV))
 182
 183 /*
 184  * Mode/Count of data node descriptors - IPCv2
 185  */
 186 struct sdma_mode_count {
 187         u32 count   : 16; /* size of the buffer pointed by this BD */
 188         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 189         u32 command :  8; /* command mostly used for channel 0 */
 190 };
 191
 192 /*
 193  * Buffer descriptor
 194  */
 195 struct sdma_buffer_descriptor {
 196         struct sdma_mode_count  mode;
 197         u32 buffer_addr;        /* address of the buffer described */
 198         u32 ext_buffer_addr;    /* extended buffer address */
 199 } __attribute__ ((packed));
 200
 201 /**
 202  * struct sdma_channel_control - Channel control Block
 203  *
 204  * @current_bd_ptr      current buffer descriptor processed
 205  * @base_bd_ptr         first element of buffer descriptor array
 206  * @unused              padding. The SDMA engine expects an array of 128 byte
 207  *                      control blocks
 208  */
 209 struct sdma_channel_control {
 210         u32 current_bd_ptr;
 211         u32 base_bd_ptr;
 212         u32 unused[2];
 213 } __attribute__ ((packed));
 214
 215 /**
 216  * struct sdma_state_registers - SDMA context for a channel
 217  *
 218  * @pc:         program counter
 219  * @t:          test bit: status of arithmetic & test instruction
 220  * @rpc:        return program counter
 221  * @sf:         source fault while loading data
 222  * @spc:        loop start program counter
 223  * @df:         destination fault while storing data
 224  * @epc:        loop end program counter
 225  * @lm:         loop mode
 226  */
 227 struct sdma_state_registers {
 228         u32 pc     :14;
 229         u32 unused1: 1;
 230         u32 t      : 1;
 231         u32 rpc    :14;
 232         u32 unused0: 1;
 233         u32 sf     : 1;
 234         u32 spc    :14;
 235         u32 unused2: 1;
 236         u32 df     : 1;
 237         u32 epc    :14;
 238         u32 lm     : 2;
 239 } __attribute__ ((packed));
 240
 241 /**
 242  * struct sdma_context_data - sdma context specific to a channel
 243  *
 244  * @channel_state:      channel state bits
 245  * @gReg:               general registers
 246  * @mda:                burst dma destination address register
 247  * @msa:                burst dma source address register
 248  * @ms:                 burst dma status register
 249  * @md:                 burst dma data register
 250  * @pda:                peripheral dma destination address register
 251  * @psa:                peripheral dma source address register
 252  * @ps:                 peripheral dma status register
 253  * @pd:                 peripheral dma data register
 254  * @ca:                 CRC polynomial register
 255  * @cs:                 CRC accumulator register
 256  * @dda:                dedicated core destination address register
 257  * @dsa:                dedicated core source address register
 258  * @ds:                 dedicated core status register
 259  * @dd:                 dedicated core data register
 260  */
 261 struct sdma_context_data {
 262         struct sdma_state_registers  channel_state;
 263         u32  gReg[8];
 264         u32  mda;
 265         u32  msa;
 266         u32  ms;
 267         u32  md;
 268         u32  pda;
 269         u32  psa;
 270         u32  ps;
 271         u32  pd;
 272         u32  ca;
 273         u32  cs;
 274         u32  dda;
 275         u32  dsa;
 276         u32  ds;
 277         u32  dd;
 278         u32  scratch0;
 279         u32  scratch1;
 280         u32  scratch2;
 281         u32  scratch3;
 282         u32  scratch4;
 283         u32  scratch5;
 284         u32  scratch6;
 285         u32  scratch7;
 286 } __attribute__ ((packed));
 287
 288 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 289
 290 struct sdma_engine;
 291
 292 /**
 293  * struct sdma_desc - descriptor structor for one transfer
 294  * @vd                  descriptor for virt dma
 295  * @num_bd              max NUM_BD. number of descriptors currently handling
 296  * @buf_tail            ID of the buffer that was processed
 297  * @buf_ptail           ID of the previous buffer that was processed
 298  * @period_len          period length, used in cyclic.
 299  * @chn_real_count      the real count updated from bd->mode.count
 300  * @chn_count           the transfer count setuped
 301  * @sdmac               sdma_channel pointer
 302  * @bd                  pointer of alloced bd
 303  */
 304 struct sdma_desc {
 305         struct virt_dma_desc    vd;
 306         unsigned int            num_bd;
 307         dma_addr_t              bd_phys;
 308         unsigned int            buf_tail;
 309         unsigned int            buf_ptail;
 310         unsigned int            period_len;
 311         unsigned int            chn_real_count;
 312         unsigned int            chn_count;
 313         struct sdma_channel     *sdmac;
 314         struct sdma_buffer_descriptor *bd;
 315 };
 316
 317 /**
 318  * struct sdma_channel - housekeeping for a SDMA channel
 319  *
 320  * @sdma                pointer to the SDMA engine for this channel
 321  * @channel             the channel number, matches dmaengine chan_id + 1
 322  * @direction           transfer type. Needed for setting SDMA script
 323  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 324  * @event_id0           aka dma request line
 325  * @event_id1           for channels that use 2 events
 326  * @word_size           peripheral access size
 327  */
 328 struct sdma_channel {
 329         struct virt_dma_chan            vc;
 330         struct sdma_desc                *desc;
 331         struct sdma_engine              *sdma;
 332         unsigned int                    channel;
 333         enum dma_transfer_direction             direction;
 334         enum sdma_peripheral_type       peripheral_type;
 335         unsigned int                    event_id0;
 336         unsigned int                    event_id1;
 337         enum dma_slave_buswidth         word_size;
 338         unsigned int                    pc_from_device, pc_to_device;
 339         unsigned int                    device_to_device;
 340         unsigned long                   flags;
 341         dma_addr_t                      per_address, per_address2;
 342         unsigned long                   event_mask[2];
 343         unsigned long                   watermark_level;
 344         u32                             shp_addr, per_addr;
 345         enum dma_status                 status;
 346         struct imx_dma_data             data;
 347 };
 348
 349 #define IMX_DMA_SG_LOOP         BIT(0)
 350
 351 #define MAX_DMA_CHANNELS 32
 352 #define MXC_SDMA_DEFAULT_PRIORITY 1
 353 #define MXC_SDMA_MIN_PRIORITY 1
 354 #define MXC_SDMA_MAX_PRIORITY 7
 355
 356 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 357
 358 /**
 359  * struct sdma_firmware_header - Layout of the firmware image
 360  *
 361  * @magic               "SDMA"
 362  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 363  *                      changes.
 364  * @version_minor       firmware minor version (for binary compatible changes)
 365  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 366  * @num_script_addrs    Number of script addresses in this image
 367  * @ram_code_start      offset of SDMA ram image in this firmware image
 368  * @ram_code_size       size of SDMA ram image
 369  * @script_addrs        Stores the start address of the SDMA scripts
 370  *                      (in SDMA memory space)
 371  */
 372 struct sdma_firmware_header {
 373         u32     magic;
 374         u32     version_major;
 375         u32     version_minor;
 376         u32     script_addrs_start;
 377         u32     num_script_addrs;
 378         u32     ram_code_start;
 379         u32     ram_code_size;
 380 };
 381
 382 struct sdma_driver_data {
 383         int chnenbl0;
 384         int num_events;
 385         struct sdma_script_start_addrs  *script_addrs;
 386 };
 387
 388 struct sdma_engine {
 389         struct device                   *dev;
 390         struct device_dma_parameters    dma_parms;
 391         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 392         struct sdma_channel_control     *channel_control;
 393         void __iomem                    *regs;
 394         struct sdma_context_data        *context;
 395         dma_addr_t                      context_phys;
 396         struct dma_device               dma_device;
 397         struct clk                      *clk_ipg;
 398         struct clk                      *clk_ahb;
 399         spinlock_t                      channel_0_lock;
 400         u32                             script_number;
 401         struct sdma_script_start_addrs  *script_addrs;
 402         const struct sdma_driver_data   *drvdata;
 403         u32                             spba_start_addr;
 404         u32                             spba_end_addr;
 405         unsigned int                    irq;
 406         dma_addr_t                      bd0_phys;
 407         struct sdma_buffer_descriptor   *bd0;
 408 };
 409
 410 static struct sdma_driver_data sdma_imx31 = {
 411         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 412         .num_events = 32,
 413 };
 414
 415 static struct sdma_script_start_addrs sdma_script_imx25 = {
 416         .ap_2_ap_addr = 729,
 417         .uart_2_mcu_addr = 904,
 418         .per_2_app_addr = 1255,
 419         .mcu_2_app_addr = 834,
 420         .uartsh_2_mcu_addr = 1120,
 421         .per_2_shp_addr = 1329,
 422         .mcu_2_shp_addr = 1048,
 423         .ata_2_mcu_addr = 1560,
 424         .mcu_2_ata_addr = 1479,
 425         .app_2_per_addr = 1189,
 426         .app_2_mcu_addr = 770,
 427         .shp_2_per_addr = 1407,
 428         .shp_2_mcu_addr = 979,
 429 };
 430
 431 static struct sdma_driver_data sdma_imx25 = {
 432         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 433         .num_events = 48,
 434         .script_addrs = &sdma_script_imx25,
 435 };
 436
 437 static struct sdma_driver_data sdma_imx35 = {
 438         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 439         .num_events = 48,
 440 };
 441
 442 static struct sdma_script_start_addrs sdma_script_imx51 = {
 443         .ap_2_ap_addr = 642,
 444         .uart_2_mcu_addr = 817,
 445         .mcu_2_app_addr = 747,
 446         .mcu_2_shp_addr = 961,
 447         .ata_2_mcu_addr = 1473,
 448         .mcu_2_ata_addr = 1392,
 449         .app_2_per_addr = 1033,
 450         .app_2_mcu_addr = 683,
 451         .shp_2_per_addr = 1251,
 452         .shp_2_mcu_addr = 892,
 453 };
 454
 455 static struct sdma_driver_data sdma_imx51 = {
 456         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 457         .num_events = 48,
 458         .script_addrs = &sdma_script_imx51,
 459 };
 460
 461 static struct sdma_script_start_addrs sdma_script_imx53 = {
 462         .ap_2_ap_addr = 642,
 463         .app_2_mcu_addr = 683,
 464         .mcu_2_app_addr = 747,
 465         .uart_2_mcu_addr = 817,
 466         .shp_2_mcu_addr = 891,
 467         .mcu_2_shp_addr = 960,
 468         .uartsh_2_mcu_addr = 1032,
 469         .spdif_2_mcu_addr = 1100,
 470         .mcu_2_spdif_addr = 1134,
 471         .firi_2_mcu_addr = 1193,
 472         .mcu_2_firi_addr = 1290,
 473 };
 474
 475 static struct sdma_driver_data sdma_imx53 = {
 476         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 477         .num_events = 48,
 478         .script_addrs = &sdma_script_imx53,
 479 };
 480
 481 static struct sdma_script_start_addrs sdma_script_imx6q = {
 482         .ap_2_ap_addr = 642,
 483         .uart_2_mcu_addr = 817,
 484         .mcu_2_app_addr = 747,
 485         .per_2_per_addr = 6331,
 486         .uartsh_2_mcu_addr = 1032,
 487         .mcu_2_shp_addr = 960,
 488         .app_2_mcu_addr = 683,
 489         .shp_2_mcu_addr = 891,
 490         .spdif_2_mcu_addr = 1100,
 491         .mcu_2_spdif_addr = 1134,
 492 };
 493
 494 static struct sdma_driver_data sdma_imx6q = {
 495         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 496         .num_events = 48,
 497         .script_addrs = &sdma_script_imx6q,
 498 };
 499
 500 static struct sdma_script_start_addrs sdma_script_imx7d = {
 501         .ap_2_ap_addr = 644,
 502         .uart_2_mcu_addr = 819,
 503         .mcu_2_app_addr = 749,
 504         .uartsh_2_mcu_addr = 1034,
 505         .mcu_2_shp_addr = 962,
 506         .app_2_mcu_addr = 685,
 507         .shp_2_mcu_addr = 893,
 508         .spdif_2_mcu_addr = 1102,
 509         .mcu_2_spdif_addr = 1136,
 510 };
 511
 512 static struct sdma_driver_data sdma_imx7d = {
 513         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 514         .num_events = 48,
 515         .script_addrs = &sdma_script_imx7d,
 516 };
 517
 518 static const struct platform_device_id sdma_devtypes[] = {
 519         {
 520                 .name = "imx25-sdma",
 521                 .driver_data = (unsigned long)&sdma_imx25,
 522         }, {
 523                 .name = "imx31-sdma",
 524                 .driver_data = (unsigned long)&sdma_imx31,
 525         }, {
 526                 .name = "imx35-sdma",
 527                 .driver_data = (unsigned long)&sdma_imx35,
 528         }, {
 529                 .name = "imx51-sdma",
 530                 .driver_data = (unsigned long)&sdma_imx51,
 531         }, {
 532                 .name = "imx53-sdma",
 533                 .driver_data = (unsigned long)&sdma_imx53,
 534         }, {
 535                 .name = "imx6q-sdma",
 536                 .driver_data = (unsigned long)&sdma_imx6q,
 537         }, {
 538                 .name = "imx7d-sdma",
 539                 .driver_data = (unsigned long)&sdma_imx7d,
 540         }, {
 541                 /* sentinel */
 542         }
 543 };
 544 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 545
 546 static const struct of_device_id sdma_dt_ids[] = {
 547         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 548         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 549         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 550         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 551         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 552         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 553         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 554         { /* sentinel */ }
 555 };
 556 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 557
 558 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 559 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 560 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 561 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 562
 563 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 564 {
 565         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 566         return chnenbl0 + event * 4;
 567 }
 568
 569 static int sdma_config_ownership(struct sdma_channel *sdmac,
 570                 bool event_override, bool mcu_override, bool dsp_override)
 571 {
 572         struct sdma_engine *sdma = sdmac->sdma;
 573         int channel = sdmac->channel;
 574         unsigned long evt, mcu, dsp;
 575
 576         if (event_override && mcu_override && dsp_override)
 577                 return -EINVAL;
 578
 579         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 580         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 581         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 582
 583         if (dsp_override)
 584                 __clear_bit(channel, &dsp);
 585         else
 586                 __set_bit(channel, &dsp);
 587
 588         if (event_override)
 589                 __clear_bit(channel, &evt);
 590         else
 591                 __set_bit(channel, &evt);
 592
 593         if (mcu_override)
 594                 __clear_bit(channel, &mcu);
 595         else
 596                 __set_bit(channel, &mcu);
 597
 598         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 599         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 600         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 601
 602         return 0;
 603 }
 604
 605 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 606 {
 607         writel(BIT(channel), sdma->regs + SDMA_H_START);
 608 }
 609
 610 /*
 611  * sdma_run_channel0 - run a channel and wait till it's done
 612  */
 613 static int sdma_run_channel0(struct sdma_engine *sdma)
 614 {
 615         int ret;
 616         u32 reg;
 617
 618         sdma_enable_channel(sdma, 0);
 619
 620         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 621                                                 reg, !(reg & 1), 1, 500);
 622         if (ret)
 623                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 624
 625         /* Set bits of CONFIG register with dynamic context switching */
 626         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 627                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 628
 629         return ret;
 630 }
 631
 632 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 633                 u32 address)
 634 {
 635         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 636         void *buf_virt;
 637         dma_addr_t buf_phys;
 638         int ret;
 639         unsigned long flags;
 640
 641         buf_virt = dma_alloc_coherent(NULL,
 642                         size,
 643                         &buf_phys, GFP_KERNEL);
 644         if (!buf_virt) {
 645                 return -ENOMEM;
 646         }
 647
 648         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 649
 650         bd0->mode.command = C0_SETPM;
 651         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 652         bd0->mode.count = size / 2;
 653         bd0->buffer_addr = buf_phys;
 654         bd0->ext_buffer_addr = address;
 655
 656         memcpy(buf_virt, buf, size);
 657
 658         ret = sdma_run_channel0(sdma);
 659
 660         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 661
 662         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 663
 664         return ret;
 665 }
 666
 667 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 668 {
 669         struct sdma_engine *sdma = sdmac->sdma;
 670         int channel = sdmac->channel;
 671         unsigned long val;
 672         u32 chnenbl = chnenbl_ofs(sdma, event);
 673
 674         val = readl_relaxed(sdma->regs + chnenbl);
 675         __set_bit(channel, &val);
 676         writel_relaxed(val, sdma->regs + chnenbl);
 677 }
 678
 679 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 680 {
 681         struct sdma_engine *sdma = sdmac->sdma;
 682         int channel = sdmac->channel;
 683         u32 chnenbl = chnenbl_ofs(sdma, event);
 684         unsigned long val;
 685
 686         val = readl_relaxed(sdma->regs + chnenbl);
 687         __clear_bit(channel, &val);
 688         writel_relaxed(val, sdma->regs + chnenbl);
 689 }
 690
 691 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
 692 {
 693         return container_of(t, struct sdma_desc, vd.tx);
 694 }
 695
 696 static void sdma_start_desc(struct sdma_channel *sdmac)
 697 {
 698         struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
 699         struct sdma_desc *desc;
 700         struct sdma_engine *sdma = sdmac->sdma;
 701         int channel = sdmac->channel;
 702
 703         if (!vd) {
 704                 sdmac->desc = NULL;
 705                 return;
 706         }
 707         sdmac->desc = desc = to_sdma_desc(&vd->tx);
 708         /*
 709          * Do not delete the node in desc_issued list in cyclic mode, otherwise
 710          * the desc alloced will never be freed in vchan_dma_desc_free_list
 711          */
 712         if (!(sdmac->flags & IMX_DMA_SG_LOOP))
 713                 list_del(&vd->node);
 714
 715         sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
 716         sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
 717         sdma_enable_channel(sdma, sdmac->channel);
 718 }
 719
 720 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 721 {
 722         struct sdma_buffer_descriptor *bd;
 723         int error = 0;
 724         enum dma_status old_status = sdmac->status;
 725
 726         /*
 727          * loop mode. Iterate over descriptors, re-setup them and
 728          * call callback function.
 729          */
 730         while (sdmac->desc) {
 731                 struct sdma_desc *desc = sdmac->desc;
 732
 733                 bd = &desc->bd[desc->buf_tail];
 734
 735                 if (bd->mode.status & BD_DONE)
 736                         break;
 737
 738                 if (bd->mode.status & BD_RROR) {
 739                         bd->mode.status &= ~BD_RROR;
 740                         sdmac->status = DMA_ERROR;
 741                         error = -EIO;
 742                 }
 743
 744                /*
 745                 * We use bd->mode.count to calculate the residue, since contains
 746                 * the number of bytes present in the current buffer descriptor.
 747                 */
 748
 749                 desc->chn_real_count = bd->mode.count;
 750                 bd->mode.status |= BD_DONE;
 751                 bd->mode.count = desc->period_len;
 752                 desc->buf_ptail = desc->buf_tail;
 753                 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
 754
 755                 /*
 756                  * The callback is called from the interrupt context in order
 757                  * to reduce latency and to avoid the risk of altering the
 758                  * SDMA transaction status by the time the client tasklet is
 759                  * executed.
 760                  */
 761                 spin_unlock(&sdmac->vc.lock);
 762                 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
 763                 spin_lock(&sdmac->vc.lock);
 764
 765                 if (error)
 766                         sdmac->status = old_status;
 767         }
 768 }
 769
 770 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
 771 {
 772         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 773         struct sdma_buffer_descriptor *bd;
 774         int i, error = 0;
 775
 776         sdmac->desc->chn_real_count = 0;
 777         /*
 778          * non loop mode. Iterate over all descriptors, collect
 779          * errors and call callback function
 780          */
 781         for (i = 0; i < sdmac->desc->num_bd; i++) {
 782                 bd = &sdmac->desc->bd[i];
 783
 784                  if (bd->mode.status & (BD_DONE | BD_RROR))
 785                         error = -EIO;
 786                  sdmac->desc->chn_real_count += bd->mode.count;
 787         }
 788
 789         if (error)
 790                 sdmac->status = DMA_ERROR;
 791         else
 792                 sdmac->status = DMA_COMPLETE;
 793 }
 794
 795 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 796 {
 797         struct sdma_engine *sdma = dev_id;
 798         unsigned long stat;
 799
 800         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 801         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 802         /* channel 0 is special and not handled here, see run_channel0() */
 803         stat &= ~1;
 804
 805         while (stat) {
 806                 int channel = fls(stat) - 1;
 807                 struct sdma_channel *sdmac = &sdma->channel[channel];
 808                 struct sdma_desc *desc;
 809
 810                 spin_lock(&sdmac->vc.lock);
 811                 desc = sdmac->desc;
 812                 if (desc) {
 813                         if (sdmac->flags & IMX_DMA_SG_LOOP) {
 814                                 sdma_update_channel_loop(sdmac);
 815                         } else {
 816                                 mxc_sdma_handle_channel_normal(sdmac);
 817                                 vchan_cookie_complete(&desc->vd);
 818                                 sdma_start_desc(sdmac);
 819                         }
 820                 }
 821
 822                 spin_unlock(&sdmac->vc.lock);
 823                 __clear_bit(channel, &stat);
 824         }
 825
 826         return IRQ_HANDLED;
 827 }
 828
 829 /*
 830  * sets the pc of SDMA script according to the peripheral type
 831  */
 832 static void sdma_get_pc(struct sdma_channel *sdmac,
 833                 enum sdma_peripheral_type peripheral_type)
 834 {
 835         struct sdma_engine *sdma = sdmac->sdma;
 836         int per_2_emi = 0, emi_2_per = 0;
 837         /*
 838          * These are needed once we start to support transfers between
 839          * two peripherals or memory-to-memory transfers
 840          */
 841         int per_2_per = 0;
 842
 843         sdmac->pc_from_device = 0;
 844         sdmac->pc_to_device = 0;
 845         sdmac->device_to_device = 0;
 846
 847         switch (peripheral_type) {
 848         case IMX_DMATYPE_MEMORY:
 849                 break;
 850         case IMX_DMATYPE_DSP:
 851                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 852                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 853                 break;
 854         case IMX_DMATYPE_FIRI:
 855                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 856                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 857                 break;
 858         case IMX_DMATYPE_UART:
 859                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 860                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 861                 break;
 862         case IMX_DMATYPE_UART_SP:
 863                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 864                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 865                 break;
 866         case IMX_DMATYPE_ATA:
 867                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 868                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 869                 break;
 870         case IMX_DMATYPE_CSPI:
 871         case IMX_DMATYPE_EXT:
 872         case IMX_DMATYPE_SSI:
 873         case IMX_DMATYPE_SAI:
 874                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 875                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 876                 break;
 877         case IMX_DMATYPE_SSI_DUAL:
 878                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 879                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 880                 break;
 881         case IMX_DMATYPE_SSI_SP:
 882         case IMX_DMATYPE_MMC:
 883         case IMX_DMATYPE_SDHC:
 884         case IMX_DMATYPE_CSPI_SP:
 885         case IMX_DMATYPE_ESAI:
 886         case IMX_DMATYPE_MSHC_SP:
 887                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 888                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 889                 break;
 890         case IMX_DMATYPE_ASRC:
 891                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 892                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 893                 per_2_per = sdma->script_addrs->per_2_per_addr;
 894                 break;
 895         case IMX_DMATYPE_ASRC_SP:
 896                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 897                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 898                 per_2_per = sdma->script_addrs->per_2_per_addr;
 899                 break;
 900         case IMX_DMATYPE_MSHC:
 901                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 902                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 903                 break;
 904         case IMX_DMATYPE_CCM:
 905                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 906                 break;
 907         case IMX_DMATYPE_SPDIF:
 908                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 909                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 910                 break;
 911         case IMX_DMATYPE_IPU_MEMORY:
 912                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 913                 break;
 914         default:
 915                 break;
 916         }
 917
 918         sdmac->pc_from_device = per_2_emi;
 919         sdmac->pc_to_device = emi_2_per;
 920         sdmac->device_to_device = per_2_per;
 921 }
 922
 923 static int sdma_load_context(struct sdma_channel *sdmac)
 924 {
 925         struct sdma_engine *sdma = sdmac->sdma;
 926         int channel = sdmac->channel;
 927         int load_address;
 928         struct sdma_context_data *context = sdma->context;
 929         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 930         int ret;
 931         unsigned long flags;
 932
 933         if (sdmac->direction == DMA_DEV_TO_MEM)
 934                 load_address = sdmac->pc_from_device;
 935         else if (sdmac->direction == DMA_DEV_TO_DEV)
 936                 load_address = sdmac->device_to_device;
 937         else
 938                 load_address = sdmac->pc_to_device;
 939
 940         if (load_address < 0)
 941                 return load_address;
 942
 943         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 944         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 945         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 946         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 947         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 948         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 949
 950         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 951
 952         memset(context, 0, sizeof(*context));
 953         context->channel_state.pc = load_address;
 954
 955         /* Send by context the event mask,base address for peripheral
 956          * and watermark level
 957          */
 958         context->gReg[0] = sdmac->event_mask[1];
 959         context->gReg[1] = sdmac->event_mask[0];
 960         context->gReg[2] = sdmac->per_addr;
 961         context->gReg[6] = sdmac->shp_addr;
 962         context->gReg[7] = sdmac->watermark_level;
 963
 964         bd0->mode.command = C0_SETDM;
 965         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 966         bd0->mode.count = sizeof(*context) / 4;
 967         bd0->buffer_addr = sdma->context_phys;
 968         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 969         ret = sdma_run_channel0(sdma);
 970
 971         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 972
 973         return ret;
 974 }
 975
 976 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 977 {
 978         return container_of(chan, struct sdma_channel, vc.chan);
 979 }
 980
 981 static int sdma_disable_channel(struct dma_chan *chan)
 982 {
 983         struct sdma_channel *sdmac = to_sdma_chan(chan);
 984         struct sdma_engine *sdma = sdmac->sdma;
 985         int channel = sdmac->channel;
 986
 987         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 988         sdmac->status = DMA_ERROR;
 989
 990         return 0;
 991 }
 992
 993 static int sdma_disable_channel_with_delay(struct dma_chan *chan)
 994 {
 995         struct sdma_channel *sdmac = to_sdma_chan(chan);
 996         unsigned long flags;
 997         LIST_HEAD(head);
 998
 999         sdma_disable_channel(chan);
1000         spin_lock_irqsave(&sdmac->vc.lock, flags);
1001         vchan_get_all_descriptors(&sdmac->vc, &head);
1002         sdmac->desc = NULL;
1003         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1004         vchan_dma_desc_free_list(&sdmac->vc, &head);
1005
1006         /*
1007          * According to NXP R&D team a delay of one BD SDMA cost time
1008          * (maximum is 1ms) should be added after disable of the channel
1009          * bit, to ensure SDMA core has really been stopped after SDMA
1010          * clients call .device_terminate_all.
1011          */
1012         mdelay(1);
1013
1014         return 0;
1015 }
1016
1017 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1018 {
1019         struct sdma_engine *sdma = sdmac->sdma;
1020
1021         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1022         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1023
1024         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1025         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1026
1027         if (sdmac->event_id0 > 31)
1028                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1029
1030         if (sdmac->event_id1 > 31)
1031                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1032
1033         /*
1034          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1035          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1036          * r0(event_mask[1]) and r1(event_mask[0]).
1037          */
1038         if (lwml > hwml) {
1039                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1040                                                 SDMA_WATERMARK_LEVEL_HWML);
1041                 sdmac->watermark_level |= hwml;
1042                 sdmac->watermark_level |= lwml << 16;
1043                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1044         }
1045
1046         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1047                         sdmac->per_address2 <= sdma->spba_end_addr)
1048                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1049
1050         if (sdmac->per_address >= sdma->spba_start_addr &&
1051                         sdmac->per_address <= sdma->spba_end_addr)
1052                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1053
1054         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1055 }
1056
1057 static int sdma_config_channel(struct dma_chan *chan)
1058 {
1059         struct sdma_channel *sdmac = to_sdma_chan(chan);
1060         int ret;
1061
1062         sdma_disable_channel(chan);
1063
1064         sdmac->event_mask[0] = 0;
1065         sdmac->event_mask[1] = 0;
1066         sdmac->shp_addr = 0;
1067         sdmac->per_addr = 0;
1068
1069         if (sdmac->event_id0) {
1070                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1071                         return -EINVAL;
1072                 sdma_event_enable(sdmac, sdmac->event_id0);
1073         }
1074
1075         if (sdmac->event_id1) {
1076                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1077                         return -EINVAL;
1078                 sdma_event_enable(sdmac, sdmac->event_id1);
1079         }
1080
1081         switch (sdmac->peripheral_type) {
1082         case IMX_DMATYPE_DSP:
1083                 sdma_config_ownership(sdmac, false, true, true);
1084                 break;
1085         case IMX_DMATYPE_MEMORY:
1086                 sdma_config_ownership(sdmac, false, true, false);
1087                 break;
1088         default:
1089                 sdma_config_ownership(sdmac, true, true, false);
1090                 break;
1091         }
1092
1093         sdma_get_pc(sdmac, sdmac->peripheral_type);
1094
1095         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1096                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1097                 /* Handle multiple event channels differently */
1098                 if (sdmac->event_id1) {
1099                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1100                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1101                                 sdma_set_watermarklevel_for_p2p(sdmac);
1102                 } else
1103                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1104
1105                 /* Address */
1106                 sdmac->shp_addr = sdmac->per_address;
1107                 sdmac->per_addr = sdmac->per_address2;
1108         } else {
1109                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1110         }
1111
1112         ret = sdma_load_context(sdmac);
1113
1114         return ret;
1115 }
1116
1117 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1118                 unsigned int priority)
1119 {
1120         struct sdma_engine *sdma = sdmac->sdma;
1121         int channel = sdmac->channel;
1122
1123         if (priority < MXC_SDMA_MIN_PRIORITY
1124             || priority > MXC_SDMA_MAX_PRIORITY) {
1125                 return -EINVAL;
1126         }
1127
1128         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1129
1130         return 0;
1131 }
1132
1133 static int sdma_request_channel0(struct sdma_engine *sdma)
1134 {
1135         int ret = -EBUSY;
1136
1137         sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
1138                                         GFP_NOWAIT);
1139         if (!sdma->bd0) {
1140                 ret = -ENOMEM;
1141                 goto out;
1142         }
1143
1144         sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1145         sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1146
1147         sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1148         return 0;
1149 out:
1150
1151         return ret;
1152 }
1153
1154
1155 static int sdma_alloc_bd(struct sdma_desc *desc)
1156 {
1157         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1158         int ret = 0;
1159
1160         desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys,
1161                                         GFP_ATOMIC);
1162         if (!desc->bd) {
1163                 ret = -ENOMEM;
1164                 goto out;
1165         }
1166 out:
1167         return ret;
1168 }
1169
1170 static void sdma_free_bd(struct sdma_desc *desc)
1171 {
1172         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1173
1174         dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
1175 }
1176
1177 static void sdma_desc_free(struct virt_dma_desc *vd)
1178 {
1179         struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1180
1181         sdma_free_bd(desc);
1182         kfree(desc);
1183 }
1184
1185 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1186 {
1187         struct sdma_channel *sdmac = to_sdma_chan(chan);
1188         struct imx_dma_data *data = chan->private;
1189         int prio, ret;
1190
1191         if (!data)
1192                 return -EINVAL;
1193
1194         switch (data->priority) {
1195         case DMA_PRIO_HIGH:
1196                 prio = 3;
1197                 break;
1198         case DMA_PRIO_MEDIUM:
1199                 prio = 2;
1200                 break;
1201         case DMA_PRIO_LOW:
1202         default:
1203                 prio = 1;
1204                 break;
1205         }
1206
1207         sdmac->peripheral_type = data->peripheral_type;
1208         sdmac->event_id0 = data->dma_request;
1209         sdmac->event_id1 = data->dma_request2;
1210
1211         ret = clk_enable(sdmac->sdma->clk_ipg);
1212         if (ret)
1213                 return ret;
1214         ret = clk_enable(sdmac->sdma->clk_ahb);
1215         if (ret)
1216                 goto disable_clk_ipg;
1217
1218         ret = sdma_set_channel_priority(sdmac, prio);
1219         if (ret)
1220                 goto disable_clk_ahb;
1221
1222         return 0;
1223
1224 disable_clk_ahb:
1225         clk_disable(sdmac->sdma->clk_ahb);
1226 disable_clk_ipg:
1227         clk_disable(sdmac->sdma->clk_ipg);
1228         return ret;
1229 }
1230
1231 static void sdma_free_chan_resources(struct dma_chan *chan)
1232 {
1233         struct sdma_channel *sdmac = to_sdma_chan(chan);
1234         struct sdma_engine *sdma = sdmac->sdma;
1235
1236         sdma_disable_channel_with_delay(chan);
1237
1238         if (sdmac->event_id0)
1239                 sdma_event_disable(sdmac, sdmac->event_id0);
1240         if (sdmac->event_id1)
1241                 sdma_event_disable(sdmac, sdmac->event_id1);
1242
1243         sdmac->event_id0 = 0;
1244         sdmac->event_id1 = 0;
1245
1246         sdma_set_channel_priority(sdmac, 0);
1247
1248         clk_disable(sdma->clk_ipg);
1249         clk_disable(sdma->clk_ahb);
1250 }
1251
1252 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1253                 struct dma_chan *chan, struct scatterlist *sgl,
1254                 unsigned int sg_len, enum dma_transfer_direction direction,
1255                 unsigned long flags, void *context)
1256 {
1257         struct sdma_channel *sdmac = to_sdma_chan(chan);
1258         struct sdma_engine *sdma = sdmac->sdma;
1259         int ret, i, count;
1260         int channel = sdmac->channel;
1261         struct scatterlist *sg;
1262         struct sdma_desc *desc;
1263
1264         if (sdmac->status == DMA_IN_PROGRESS)
1265                 return NULL;
1266         sdmac->status = DMA_IN_PROGRESS;
1267
1268         sdmac->flags = 0;
1269
1270         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1271         if (!desc)
1272                 goto err_out;
1273
1274         desc->buf_tail = 0;
1275         desc->buf_ptail = 0;
1276         desc->sdmac = sdmac;
1277         desc->num_bd = sg_len;
1278         desc->chn_real_count = 0;
1279
1280         if (sdma_alloc_bd(desc)) {
1281                 kfree(desc);
1282                 goto err_out;
1283         }
1284
1285         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1286                         sg_len, channel);
1287
1288         sdmac->direction = direction;
1289         ret = sdma_load_context(sdmac);
1290         if (ret)
1291                 goto err_bd_out;
1292
1293         if (sg_len > NUM_BD) {
1294                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1295                                 channel, sg_len, NUM_BD);
1296                 ret = -EINVAL;
1297                 goto err_bd_out;
1298         }
1299
1300         desc->chn_count = 0;
1301         for_each_sg(sgl, sg, sg_len, i) {
1302                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1303                 int param;
1304
1305                 bd->buffer_addr = sg->dma_address;
1306
1307                 count = sg_dma_len(sg);
1308
1309                 if (count > 0xffff) {
1310                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1311                                         channel, count, 0xffff);
1312                         ret = -EINVAL;
1313                         goto err_bd_out;
1314                 }
1315
1316                 bd->mode.count = count;
1317                 desc->chn_count += count;
1318
1319                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1320                         ret =  -EINVAL;
1321                         goto err_bd_out;
1322                 }
1323
1324                 switch (sdmac->word_size) {
1325                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1326                         bd->mode.command = 0;
1327                         if (count & 3 || sg->dma_address & 3)
1328                                 goto err_bd_out;
1329                         break;
1330                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1331                         bd->mode.command = 2;
1332                         if (count & 1 || sg->dma_address & 1)
1333                                 goto err_bd_out;
1334                         break;
1335                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1336                         bd->mode.command = 1;
1337                         break;
1338                 default:
1339                         goto err_bd_out;
1340                 }
1341
1342                 param = BD_DONE | BD_EXTD | BD_CONT;
1343
1344                 if (i + 1 == sg_len) {
1345                         param |= BD_INTR;
1346                         param |= BD_LAST;
1347                         param &= ~BD_CONT;
1348                 }
1349
1350                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1351                                 i, count, (u64)sg->dma_address,
1352                                 param & BD_WRAP ? "wrap" : "",
1353                                 param & BD_INTR ? " intr" : "");
1354
1355                 bd->mode.status = param;
1356         }
1357
1358         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1359 err_bd_out:
1360         sdma_free_bd(desc);
1361         kfree(desc);
1362 err_out:
1363         sdmac->status = DMA_ERROR;
1364         return NULL;
1365 }
1366
1367 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1368                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1369                 size_t period_len, enum dma_transfer_direction direction,
1370                 unsigned long flags)
1371 {
1372         struct sdma_channel *sdmac = to_sdma_chan(chan);
1373         struct sdma_engine *sdma = sdmac->sdma;
1374         int num_periods = buf_len / period_len;
1375         int channel = sdmac->channel;
1376         int ret, i = 0, buf = 0;
1377         struct sdma_desc *desc;
1378
1379         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1380
1381         if (sdmac->status == DMA_IN_PROGRESS)
1382                 return NULL;
1383
1384         sdmac->status = DMA_IN_PROGRESS;
1385
1386         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1387         if (!desc)
1388                 goto err_out;
1389
1390         desc->buf_tail = 0;
1391         desc->buf_ptail = 0;
1392         desc->sdmac = sdmac;
1393         desc->num_bd = num_periods;
1394         desc->chn_real_count = 0;
1395         desc->period_len = period_len;
1396
1397         sdmac->flags |= IMX_DMA_SG_LOOP;
1398         sdmac->direction = direction;
1399
1400         if (sdma_alloc_bd(desc)) {
1401                 kfree(desc);
1402                 goto err_bd_out;
1403         }
1404
1405         ret = sdma_load_context(sdmac);
1406         if (ret)
1407                 goto err_bd_out;
1408
1409         if (num_periods > NUM_BD) {
1410                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1411                                 channel, num_periods, NUM_BD);
1412                 goto err_bd_out;
1413         }
1414
1415         if (period_len > 0xffff) {
1416                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1417                                 channel, period_len, 0xffff);
1418                 goto err_bd_out;
1419         }
1420
1421         while (buf < buf_len) {
1422                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1423                 int param;
1424
1425                 bd->buffer_addr = dma_addr;
1426
1427                 bd->mode.count = period_len;
1428
1429                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1430                         goto err_bd_out;
1431                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1432                         bd->mode.command = 0;
1433                 else
1434                         bd->mode.command = sdmac->word_size;
1435
1436                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1437                 if (i + 1 == num_periods)
1438                         param |= BD_WRAP;
1439
1440                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1441                                 i, period_len, (u64)dma_addr,
1442                                 param & BD_WRAP ? "wrap" : "",
1443                                 param & BD_INTR ? " intr" : "");
1444
1445                 bd->mode.status = param;
1446
1447                 dma_addr += period_len;
1448                 buf += period_len;
1449
1450                 i++;
1451         }
1452
1453         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1454 err_bd_out:
1455         sdma_free_bd(desc);
1456         kfree(desc);
1457 err_out:
1458         sdmac->status = DMA_ERROR;
1459         return NULL;
1460 }
1461
1462 static int sdma_config(struct dma_chan *chan,
1463                        struct dma_slave_config *dmaengine_cfg)
1464 {
1465         struct sdma_channel *sdmac = to_sdma_chan(chan);
1466
1467         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1468                 sdmac->per_address = dmaengine_cfg->src_addr;
1469                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1470                         dmaengine_cfg->src_addr_width;
1471                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1472         } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1473                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1474                 sdmac->per_address = dmaengine_cfg->dst_addr;
1475                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1476                         SDMA_WATERMARK_LEVEL_LWML;
1477                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1478                         SDMA_WATERMARK_LEVEL_HWML;
1479                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1480         } else {
1481                 sdmac->per_address = dmaengine_cfg->dst_addr;
1482                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1483                         dmaengine_cfg->dst_addr_width;
1484                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1485         }
1486         sdmac->direction = dmaengine_cfg->direction;
1487         return sdma_config_channel(chan);
1488 }
1489
1490 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1491                                       dma_cookie_t cookie,
1492                                       struct dma_tx_state *txstate)
1493 {
1494         struct sdma_channel *sdmac = to_sdma_chan(chan);
1495         struct sdma_desc *desc;
1496         u32 residue;
1497         struct virt_dma_desc *vd;
1498         enum dma_status ret;
1499         unsigned long flags;
1500
1501         ret = dma_cookie_status(chan, cookie, txstate);
1502         if (ret == DMA_COMPLETE || !txstate)
1503                 return ret;
1504
1505         spin_lock_irqsave(&sdmac->vc.lock, flags);
1506         vd = vchan_find_desc(&sdmac->vc, cookie);
1507         if (vd) {
1508                 desc = to_sdma_desc(&vd->tx);
1509                 if (sdmac->flags & IMX_DMA_SG_LOOP)
1510                         residue = (desc->num_bd - desc->buf_ptail) *
1511                                 desc->period_len - desc->chn_real_count;
1512                 else
1513                         residue = desc->chn_count - desc->chn_real_count;
1514         } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1515                 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1516         } else {
1517                 residue = 0;
1518         }
1519         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1520
1521         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1522                          residue);
1523
1524         return sdmac->status;
1525 }
1526
1527 static void sdma_issue_pending(struct dma_chan *chan)
1528 {
1529         struct sdma_channel *sdmac = to_sdma_chan(chan);
1530         unsigned long flags;
1531
1532         spin_lock_irqsave(&sdmac->vc.lock, flags);
1533         if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1534                 sdma_start_desc(sdmac);
1535         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1536 }
1537
1538 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1539 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1540 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1541 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1542
1543 static void sdma_add_scripts(struct sdma_engine *sdma,
1544                 const struct sdma_script_start_addrs *addr)
1545 {
1546         s32 *addr_arr = (u32 *)addr;
1547         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1548         int i;
1549
1550         /* use the default firmware in ROM if missing external firmware */
1551         if (!sdma->script_number)
1552                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1553
1554         for (i = 0; i < sdma->script_number; i++)
1555                 if (addr_arr[i] > 0)
1556                         saddr_arr[i] = addr_arr[i];
1557 }
1558
1559 static void sdma_load_firmware(const struct firmware *fw, void *context)
1560 {
1561         struct sdma_engine *sdma = context;
1562         const struct sdma_firmware_header *header;
1563         const struct sdma_script_start_addrs *addr;
1564         unsigned short *ram_code;
1565
1566         if (!fw) {
1567                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1568                 /* In this case we just use the ROM firmware. */
1569                 return;
1570         }
1571
1572         if (fw->size < sizeof(*header))
1573                 goto err_firmware;
1574
1575         header = (struct sdma_firmware_header *)fw->data;
1576
1577         if (header->magic != SDMA_FIRMWARE_MAGIC)
1578                 goto err_firmware;
1579         if (header->ram_code_start + header->ram_code_size > fw->size)
1580                 goto err_firmware;
1581         switch (header->version_major) {
1582         case 1:
1583                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1584                 break;
1585         case 2:
1586                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1587                 break;
1588         case 3:
1589                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1590                 break;
1591         case 4:
1592                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1593                 break;
1594         default:
1595                 dev_err(sdma->dev, "unknown firmware version\n");
1596                 goto err_firmware;
1597         }
1598
1599         addr = (void *)header + header->script_addrs_start;
1600         ram_code = (void *)header + header->ram_code_start;
1601
1602         clk_enable(sdma->clk_ipg);
1603         clk_enable(sdma->clk_ahb);
1604         /* download the RAM image for SDMA */
1605         sdma_load_script(sdma, ram_code,
1606                         header->ram_code_size,
1607                         addr->ram_code_start_addr);
1608         clk_disable(sdma->clk_ipg);
1609         clk_disable(sdma->clk_ahb);
1610
1611         sdma_add_scripts(sdma, addr);
1612
1613         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1614                         header->version_major,
1615                         header->version_minor);
1616
1617 err_firmware:
1618         release_firmware(fw);
1619 }
1620
1621 #define EVENT_REMAP_CELLS 3
1622
1623 static int sdma_event_remap(struct sdma_engine *sdma)
1624 {
1625         struct device_node *np = sdma->dev->of_node;
1626         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1627         struct property *event_remap;
1628         struct regmap *gpr;
1629         char propname[] = "fsl,sdma-event-remap";
1630         u32 reg, val, shift, num_map, i;
1631         int ret = 0;
1632
1633         if (IS_ERR(np) || IS_ERR(gpr_np))
1634                 goto out;
1635
1636         event_remap = of_find_property(np, propname, NULL);
1637         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1638         if (!num_map) {
1639                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1640                 goto out;
1641         } else if (num_map % EVENT_REMAP_CELLS) {
1642                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1643                                 propname, EVENT_REMAP_CELLS);
1644                 ret = -EINVAL;
1645                 goto out;
1646         }
1647
1648         gpr = syscon_node_to_regmap(gpr_np);
1649         if (IS_ERR(gpr)) {
1650                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1651                 ret = PTR_ERR(gpr);
1652                 goto out;
1653         }
1654
1655         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1656                 ret = of_property_read_u32_index(np, propname, i, &reg);
1657                 if (ret) {
1658                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1659                                         propname, i);
1660                         goto out;
1661                 }
1662
1663                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1664                 if (ret) {
1665                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1666                                         propname, i + 1);
1667                         goto out;
1668                 }
1669
1670                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1671                 if (ret) {
1672                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1673                                         propname, i + 2);
1674                         goto out;
1675                 }
1676
1677                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1678         }
1679
1680 out:
1681         if (!IS_ERR(gpr_np))
1682                 of_node_put(gpr_np);
1683
1684         return ret;
1685 }
1686
1687 static int sdma_get_firmware(struct sdma_engine *sdma,
1688                 const char *fw_name)
1689 {
1690         int ret;
1691
1692         ret = request_firmware_nowait(THIS_MODULE,
1693                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1694                         GFP_KERNEL, sdma, sdma_load_firmware);
1695
1696         return ret;
1697 }
1698
1699 static int sdma_init(struct sdma_engine *sdma)
1700 {
1701         int i, ret;
1702         dma_addr_t ccb_phys;
1703
1704         ret = clk_enable(sdma->clk_ipg);
1705         if (ret)
1706                 return ret;
1707         ret = clk_enable(sdma->clk_ahb);
1708         if (ret)
1709                 goto disable_clk_ipg;
1710
1711         /* Be sure SDMA has not started yet */
1712         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1713
1714         sdma->channel_control = dma_alloc_coherent(NULL,
1715                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1716                         sizeof(struct sdma_context_data),
1717                         &ccb_phys, GFP_KERNEL);
1718
1719         if (!sdma->channel_control) {
1720                 ret = -ENOMEM;
1721                 goto err_dma_alloc;
1722         }
1723
1724         sdma->context = (void *)sdma->channel_control +
1725                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1726         sdma->context_phys = ccb_phys +
1727                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1728
1729         /* Zero-out the CCB structures array just allocated */
1730         memset(sdma->channel_control, 0,
1731                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1732
1733         /* disable all channels */
1734         for (i = 0; i < sdma->drvdata->num_events; i++)
1735                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1736
1737         /* All channels have priority 0 */
1738         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1739                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1740
1741         ret = sdma_request_channel0(sdma);
1742         if (ret)
1743                 goto err_dma_alloc;
1744
1745         sdma_config_ownership(&sdma->channel[0], false, true, false);
1746
1747         /* Set Command Channel (Channel Zero) */
1748         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1749
1750         /* Set bits of CONFIG register but with static context switching */
1751         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1752         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1753
1754         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1755
1756         /* Initializes channel's priorities */
1757         sdma_set_channel_priority(&sdma->channel[0], 7);
1758
1759         clk_disable(sdma->clk_ipg);
1760         clk_disable(sdma->clk_ahb);
1761
1762         return 0;
1763
1764 err_dma_alloc:
1765         clk_disable(sdma->clk_ahb);
1766 disable_clk_ipg:
1767         clk_disable(sdma->clk_ipg);
1768         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1769         return ret;
1770 }
1771
1772 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1773 {
1774         struct sdma_channel *sdmac = to_sdma_chan(chan);
1775         struct imx_dma_data *data = fn_param;
1776
1777         if (!imx_dma_is_general_purpose(chan))
1778                 return false;
1779
1780         sdmac->data = *data;
1781         chan->private = &sdmac->data;
1782
1783         return true;
1784 }
1785
1786 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1787                                    struct of_dma *ofdma)
1788 {
1789         struct sdma_engine *sdma = ofdma->of_dma_data;
1790         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1791         struct imx_dma_data data;
1792
1793         if (dma_spec->args_count != 3)
1794                 return NULL;
1795
1796         data.dma_request = dma_spec->args[0];
1797         data.peripheral_type = dma_spec->args[1];
1798         data.priority = dma_spec->args[2];
1799         /*
1800          * init dma_request2 to zero, which is not used by the dts.
1801          * For P2P, dma_request2 is init from dma_request_channel(),
1802          * chan->private will point to the imx_dma_data, and in
1803          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1804          * be set to sdmac->event_id1.
1805          */
1806         data.dma_request2 = 0;
1807
1808         return dma_request_channel(mask, sdma_filter_fn, &data);
1809 }
1810
1811 static int sdma_probe(struct platform_device *pdev)
1812 {
1813         const struct of_device_id *of_id =
1814                         of_match_device(sdma_dt_ids, &pdev->dev);
1815         struct device_node *np = pdev->dev.of_node;
1816         struct device_node *spba_bus;
1817         const char *fw_name;
1818         int ret;
1819         int irq;
1820         struct resource *iores;
1821         struct resource spba_res;
1822         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1823         int i;
1824         struct sdma_engine *sdma;
1825         s32 *saddr_arr;
1826         const struct sdma_driver_data *drvdata = NULL;
1827
1828         if (of_id)
1829                 drvdata = of_id->data;
1830         else if (pdev->id_entry)
1831                 drvdata = (void *)pdev->id_entry->driver_data;
1832
1833         if (!drvdata) {
1834                 dev_err(&pdev->dev, "unable to find driver data\n");
1835                 return -EINVAL;
1836         }
1837
1838         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1839         if (ret)
1840                 return ret;
1841
1842         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1843         if (!sdma)
1844                 return -ENOMEM;
1845
1846         spin_lock_init(&sdma->channel_0_lock);
1847
1848         sdma->dev = &pdev->dev;
1849         sdma->drvdata = drvdata;
1850
1851         irq = platform_get_irq(pdev, 0);
1852         if (irq < 0)
1853                 return irq;
1854
1855         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1856         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1857         if (IS_ERR(sdma->regs))
1858                 return PTR_ERR(sdma->regs);
1859
1860         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1861         if (IS_ERR(sdma->clk_ipg))
1862                 return PTR_ERR(sdma->clk_ipg);
1863
1864         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1865         if (IS_ERR(sdma->clk_ahb))
1866                 return PTR_ERR(sdma->clk_ahb);
1867
1868         ret = clk_prepare(sdma->clk_ipg);
1869         if (ret)
1870                 return ret;
1871
1872         ret = clk_prepare(sdma->clk_ahb);
1873         if (ret)
1874                 goto err_clk;
1875
1876         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1877                                sdma);
1878         if (ret)
1879                 goto err_irq;
1880
1881         sdma->irq = irq;
1882
1883         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1884         if (!sdma->script_addrs) {
1885                 ret = -ENOMEM;
1886                 goto err_irq;
1887         }
1888
1889         /* initially no scripts available */
1890         saddr_arr = (s32 *)sdma->script_addrs;
1891         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1892                 saddr_arr[i] = -EINVAL;
1893
1894         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1895         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1896
1897         INIT_LIST_HEAD(&sdma->dma_device.channels);
1898         /* Initialize channel parameters */
1899         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1900                 struct sdma_channel *sdmac = &sdma->channel[i];
1901
1902                 sdmac->sdma = sdma;
1903
1904                 sdmac->channel = i;
1905                 sdmac->vc.desc_free = sdma_desc_free;
1906                 /*
1907                  * Add the channel to the DMAC list. Do not add channel 0 though
1908                  * because we need it internally in the SDMA driver. This also means
1909                  * that channel 0 in dmaengine counting matches sdma channel 1.
1910                  */
1911                 if (i)
1912                         vchan_init(&sdmac->vc, &sdma->dma_device);
1913         }
1914
1915         ret = sdma_init(sdma);
1916         if (ret)
1917                 goto err_init;
1918
1919         ret = sdma_event_remap(sdma);
1920         if (ret)
1921                 goto err_init;
1922
1923         if (sdma->drvdata->script_addrs)
1924                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1925         if (pdata && pdata->script_addrs)
1926                 sdma_add_scripts(sdma, pdata->script_addrs);
1927
1928         if (pdata) {
1929                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1930                 if (ret)
1931                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1932         } else {
1933                 /*
1934                  * Because that device tree does not encode ROM script address,
1935                  * the RAM script in firmware is mandatory for device tree
1936                  * probe, otherwise it fails.
1937                  */
1938                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1939                                               &fw_name);
1940                 if (ret)
1941                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1942                 else {
1943                         ret = sdma_get_firmware(sdma, fw_name);
1944                         if (ret)
1945                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1946                 }
1947         }
1948
1949         sdma->dma_device.dev = &pdev->dev;
1950
1951         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1952         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1953         sdma->dma_device.device_tx_status = sdma_tx_status;
1954         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1955         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1956         sdma->dma_device.device_config = sdma_config;
1957         sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
1958         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
1959         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
1960         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
1961         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1962         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1963         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1964         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1965
1966         platform_set_drvdata(pdev, sdma);
1967
1968         ret = dma_async_device_register(&sdma->dma_device);
1969         if (ret) {
1970                 dev_err(&pdev->dev, "unable to register\n");
1971                 goto err_init;
1972         }
1973
1974         if (np) {
1975                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1976                 if (ret) {
1977                         dev_err(&pdev->dev, "failed to register controller\n");
1978                         goto err_register;
1979                 }
1980
1981                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1982                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1983                 if (!ret) {
1984                         sdma->spba_start_addr = spba_res.start;
1985                         sdma->spba_end_addr = spba_res.end;
1986                 }
1987                 of_node_put(spba_bus);
1988         }
1989
1990         return 0;
1991
1992 err_register:
1993         dma_async_device_unregister(&sdma->dma_device);
1994 err_init:
1995         kfree(sdma->script_addrs);
1996 err_irq:
1997         clk_unprepare(sdma->clk_ahb);
1998 err_clk:
1999         clk_unprepare(sdma->clk_ipg);
2000         return ret;
2001 }
2002
2003 static int sdma_remove(struct platform_device *pdev)
2004 {
2005         struct sdma_engine *sdma = platform_get_drvdata(pdev);
2006         int i;
2007
2008         devm_free_irq(&pdev->dev, sdma->irq, sdma);
2009         dma_async_device_unregister(&sdma->dma_device);
2010         kfree(sdma->script_addrs);
2011         clk_unprepare(sdma->clk_ahb);
2012         clk_unprepare(sdma->clk_ipg);
2013         /* Kill the tasklet */
2014         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2015                 struct sdma_channel *sdmac = &sdma->channel[i];
2016
2017                 tasklet_kill(&sdmac->vc.task);
2018                 sdma_free_chan_resources(&sdmac->vc.chan);
2019         }
2020
2021         platform_set_drvdata(pdev, NULL);
2022         return 0;
2023 }
2024
2025 static struct platform_driver sdma_driver = {
2026         .driver         = {
2027                 .name   = "imx-sdma",
2028                 .of_match_table = sdma_dt_ids,
2029         },
2030         .id_table       = sdma_devtypes,
2031         .remove         = sdma_remove,
2032         .probe          = sdma_probe,
2033 };
2034
2035 module_platform_driver(sdma_driver);
2036
2037 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2038 MODULE_DESCRIPTION("i.MX SDMA driver");
2039 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2040 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2041 #endif
2042 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2043 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2044 #endif
2045 MODULE_LICENSE("GPL");