2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
17 #ifndef _IOAT_REGISTERS_H_
18 #define _IOAT_REGISTERS_H_
20 #define IOAT_PCI_DMACTRL_OFFSET 0x48
21 #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
22 #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
24 #define IOAT_PCI_DEVICE_ID_OFFSET 0x02
25 #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148
26 #define IOAT_PCI_CHANERR_INT_OFFSET 0x180
27 #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
29 /* PCIe config registers */
32 #define IOAT_DEVCTRL_OFFSET 0x8
33 /* relaxed ordering enable */
34 #define IOAT_DEVCTRL_ROE 0x10
36 /* MMIO Device Registers */
37 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
39 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
40 #define IOAT_XFERCAP_4KB 12
41 #define IOAT_XFERCAP_8KB 13
42 #define IOAT_XFERCAP_16KB 14
43 #define IOAT_XFERCAP_32KB 15
44 #define IOAT_XFERCAP_32GB 0
46 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
47 #define IOAT_GENCTRL_DEBUG_EN 0x01
49 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
50 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
51 #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
52 #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
53 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
55 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
57 #define IOAT_VER_OFFSET 0x08 /* 8-bit */
58 #define IOAT_VER_MAJOR_MASK 0xF0
59 #define IOAT_VER_MINOR_MASK 0x0F
60 #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4)
61 #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
63 #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
65 #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
66 #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */
67 #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */
69 #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
70 #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
71 #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002
72 #define IOAT_DEVICE_MEMORY_BYPASS 0x0004
73 #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008
75 #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */
76 #define IOAT_CAP_PAGE_BREAK 0x00000001
77 #define IOAT_CAP_CRC 0x00000002
78 #define IOAT_CAP_SKIP_MARKER 0x00000004
79 #define IOAT_CAP_DCA 0x00000010
80 #define IOAT_CAP_CRC_MOVE 0x00000020
81 #define IOAT_CAP_FILL_BLOCK 0x00000040
82 #define IOAT_CAP_APIC 0x00000080
83 #define IOAT_CAP_XOR 0x00000100
84 #define IOAT_CAP_PQ 0x00000200
85 #define IOAT_CAP_DWBES 0x00002000
86 #define IOAT_CAP_RAID16SS 0x00020000
87 #define IOAT_CAP_DPS 0x00800000
89 #define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */
91 #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
93 /* DMA Channel Registers */
94 #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
95 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
96 #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200
97 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
98 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
99 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010
100 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
101 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
102 #define IOAT_CHANCTRL_INT_REARM 0x0001
103 #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\
104 IOAT_CHANCTRL_ERR_INT_EN |\
105 IOAT_CHANCTRL_ERR_COMPLETION_EN |\
106 IOAT_CHANCTRL_ANY_ERR_ABORT_EN)
108 #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
109 #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
110 #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */
112 #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
113 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL)
114 #define IOAT_CHANSTS_SOFT_ERR 0x10ULL
115 #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL
116 #define IOAT_CHANSTS_STATUS 0x7ULL
117 #define IOAT_CHANSTS_ACTIVE 0x0
118 #define IOAT_CHANSTS_DONE 0x1
119 #define IOAT_CHANSTS_SUSPENDED 0x2
120 #define IOAT_CHANSTS_HALTED 0x3
124 #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */
126 #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */
127 #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
128 #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */
130 /* CB DCA Memory Space Registers */
131 #define IOAT_DCAOFFSET_OFFSET 0x14
132 /* CB_BAR + IOAT_DCAOFFSET value */
133 #define IOAT_DCA_VER_OFFSET 0x00
134 #define IOAT_DCA_VER_MAJOR_MASK 0xF0
135 #define IOAT_DCA_VER_MINOR_MASK 0x0F
137 #define IOAT_DCA_COMP_OFFSET 0x02
138 #define IOAT_DCA_COMP_V1 0x1
140 #define IOAT_FSB_CAPABILITY_OFFSET 0x04
141 #define IOAT_FSB_CAPABILITY_PREFETCH 0x1
143 #define IOAT_PCI_CAPABILITY_OFFSET 0x06
144 #define IOAT_PCI_CAPABILITY_MEMWR 0x1
146 #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08
147 #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1
149 #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A
150 #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1
152 #define IOAT_APICID_TAG_MAP_OFFSET 0x0C
153 #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F
154 #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
155 #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0
156 #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
157 #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00
158 #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
159 #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000
160 #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
161 #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000
162 #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
163 #define IOAT_APICID_TAG_CB2_VALID 0x8080808080
165 #define IOAT_DCA_GREQID_OFFSET 0x10
166 #define IOAT_DCA_GREQID_SIZE 0x04
167 #define IOAT_DCA_GREQID_MASK 0xFFFF
168 #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000
169 #define IOAT_DCA_GREQID_VALID 0x20000000
170 #define IOAT_DCA_GREQID_LASTID 0x80000000
172 #define IOAT3_CSI_CAPABILITY_OFFSET 0x08
173 #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1
175 #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A
176 #define IOAT3_PCI_CAPABILITY_MEMWR 0x1
178 #define IOAT3_CSI_CONTROL_OFFSET 0x0C
179 #define IOAT3_CSI_CONTROL_PREFETCH 0x1
181 #define IOAT3_PCI_CONTROL_OFFSET 0x0E
182 #define IOAT3_PCI_CONTROL_MEMWR 0x1
184 #define IOAT3_APICID_TAG_MAP_OFFSET 0x10
185 #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10
186 #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14
188 #define IOAT3_DCA_GREQID_OFFSET 0x02
190 #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
191 #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */
192 #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
193 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
194 #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C
195 #define IOAT2_CHAINADDR_OFFSET_LOW 0x10
196 #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
197 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
198 #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10
199 #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14
200 #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
201 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
203 #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
204 #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */
205 #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
206 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
207 #define IOAT_CHANCMD_RESET 0x20
208 #define IOAT_CHANCMD_RESUME 0x10
209 #define IOAT_CHANCMD_ABORT 0x08
210 #define IOAT_CHANCMD_SUSPEND 0x04
211 #define IOAT_CHANCMD_APPEND 0x02
212 #define IOAT_CHANCMD_START 0x01
214 #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
215 #define IOAT_CHANCMP_OFFSET_LOW 0x18
216 #define IOAT_CHANCMP_OFFSET_HIGH 0x1C
218 #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
219 #define IOAT_CDAR_OFFSET_LOW 0x20
220 #define IOAT_CDAR_OFFSET_HIGH 0x24
222 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
223 #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001
224 #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002
225 #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004
226 #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008
227 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
228 #define IOAT_CHANERR_CHANCMD_ERR 0x0020
229 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
230 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
231 #define IOAT_CHANERR_READ_DATA_ERR 0x0100
232 #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
233 #define IOAT_CHANERR_CONTROL_ERR 0x0400
234 #define IOAT_CHANERR_LENGTH_ERR 0x0800
235 #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
236 #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
237 #define IOAT_CHANERR_SOFT_ERR 0x4000
238 #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000
239 #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000
240 #define IOAT_CHANERR_XOR_Q_ERR 0x20000
241 #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000
243 #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
244 #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \
245 IOAT_CHANERR_WRITE_DATA_ERR)
247 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
249 #define IOAT_CHAN_DRSCTL_OFFSET 0xB6
250 #define IOAT_CHAN_DRSZ_4KB 0x0000
251 #define IOAT_CHAN_DRSZ_8KB 0x0001
252 #define IOAT_CHAN_DRSZ_2MB 0x0009
253 #define IOAT_CHAN_DRS_EN 0x0100
254 #define IOAT_CHAN_DRS_AUTOWRAP 0x0200
256 #define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC
257 #define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0
258 #define IOAT_CHAN_LTR_SWSEL_IDLE 0x1
260 #define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0
261 #define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */
262 #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */
263 #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */
265 #define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4
266 #define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */
267 #define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */
268 #define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */
270 #endif /* _IOAT_REGISTERS_H_ */