drivers/dma/sf-pdma/sf-pdma.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * SiFive FU540 Platform DMA driver
   4  * Copyright (C) 2019 SiFive
   5  *
   6  * Based partially on:
   7  * - drivers/dma/fsl-edma.c
   8  * - drivers/dma/dw-edma/
   9  * - drivers/dma/pxa-dma.c
  10  *
  11  * See the following sources for further documentation:
  12  * - Chapter 12 "Platform DMA Engine (PDMA)" of
  13  *   SiFive FU540-C000 v1.0
  14  *   https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  15  */
  16 #ifndef _SF_PDMA_H
  17 #define _SF_PDMA_H
  18
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-direction.h>
  21
  22 #include "../dmaengine.h"
  23 #include "../virt-dma.h"
  24
  25 #define PDMA_NR_CH                                      4
  26
  27 #if (PDMA_NR_CH != 4)
  28 #error "Please define PDMA_NR_CH to 4"
  29 #endif
  30
  31 #define PDMA_BASE_ADDR                                  0x3000000
  32 #define PDMA_CHAN_OFFSET                                0x1000
  33
  34 /* Register Offset */
  35 #define PDMA_CTRL                                       0x000
  36 #define PDMA_XFER_TYPE                                  0x004
  37 #define PDMA_XFER_SIZE                                  0x008
  38 #define PDMA_DST_ADDR                                   0x010
  39 #define PDMA_SRC_ADDR                                   0x018
  40 #define PDMA_ACT_TYPE                                   0x104 /* Read-only */
  41 #define PDMA_REMAINING_BYTE                             0x108 /* Read-only */
  42 #define PDMA_CUR_DST_ADDR                               0x110 /* Read-only*/
  43 #define PDMA_CUR_SRC_ADDR                               0x118 /* Read-only*/
  44
  45 /* CTRL */
  46 #define PDMA_CLEAR_CTRL                                 0x0
  47 #define PDMA_CLAIM_MASK                                 GENMASK(0, 0)
  48 #define PDMA_RUN_MASK                                   GENMASK(1, 1)
  49 #define PDMA_ENABLE_DONE_INT_MASK                       GENMASK(14, 14)
  50 #define PDMA_ENABLE_ERR_INT_MASK                        GENMASK(15, 15)
  51 #define PDMA_DONE_STATUS_MASK                           GENMASK(30, 30)
  52 #define PDMA_ERR_STATUS_MASK                            GENMASK(31, 31)
  53
  54 /* Transfer Type */
  55 #define PDMA_FULL_SPEED                                 0xFF000008
  56
  57 /* Error Recovery */
  58 #define MAX_RETRY                                       1
  59
  60 struct pdma_regs {
  61         /* read-write regs */
  62         void __iomem *ctrl;             /* 4 bytes */
  63
  64         void __iomem *xfer_type;        /* 4 bytes */
  65         void __iomem *xfer_size;        /* 8 bytes */
  66         void __iomem *dst_addr;         /* 8 bytes */
  67         void __iomem *src_addr;         /* 8 bytes */
  68
  69         /* read-only */
  70         void __iomem *act_type;         /* 4 bytes */
  71         void __iomem *residue;          /* 8 bytes */
  72         void __iomem *cur_dst_addr;     /* 8 bytes */
  73         void __iomem *cur_src_addr;     /* 8 bytes */
  74 };
  75
  76 struct sf_pdma_desc {
  77         u32                             xfer_type;
  78         u64                             xfer_size;
  79         u64                             dst_addr;
  80         u64                             src_addr;
  81         struct virt_dma_desc            vdesc;
  82         struct sf_pdma_chan             *chan;
  83         bool                            in_use;
  84         enum dma_transfer_direction     dirn;
  85         struct dma_async_tx_descriptor *async_tx;
  86 };
  87
  88 enum sf_pdma_pm_state {
  89         RUNNING = 0,
  90         SUSPENDED,
  91 };
  92
  93 struct sf_pdma_chan {
  94         struct virt_dma_chan            vchan;
  95         enum dma_status                 status;
  96         enum sf_pdma_pm_state           pm_state;
  97         u32                             slave_id;
  98         struct sf_pdma                  *pdma;
  99         struct sf_pdma_desc             *desc;
 100         struct dma_slave_config         cfg;
 101         u32                             attr;
 102         dma_addr_t                      dma_dev_addr;
 103         u32                             dma_dev_size;
 104         struct tasklet_struct           done_tasklet;
 105         struct tasklet_struct           err_tasklet;
 106         struct pdma_regs                regs;
 107         spinlock_t                      lock; /* protect chan data */
 108         bool                            xfer_err;
 109         int                             txirq;
 110         int                             errirq;
 111         int                             retries;
 112 };
 113
 114 struct sf_pdma {
 115         struct dma_device       dma_dev;
 116         void __iomem            *membase;
 117         void __iomem            *mappedbase;
 118         u32                     n_chans;
 119         struct sf_pdma_chan     chans[PDMA_NR_CH];
 120 };
 121
 122 #endif /* _SF_PDMA_H */