1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2 DMA Controller Driver
5 * Copyright (C) 2014 Renesas Electronics Inc.
7 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
18 #include <linux/of_dma.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
25 #include "../dmaengine.h"
28 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
29 * @node: entry in the parent's chunks list
30 * @src_addr: device source address
31 * @dst_addr: device destination address
32 * @size: transfer size in bytes
34 struct rcar_dmac_xfer_chunk {
35 struct list_head node;
43 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
44 * @sar: value of the SAR register (source address)
45 * @dar: value of the DAR register (destination address)
46 * @tcr: value of the TCR register (transfer count)
48 struct rcar_dmac_hw_desc {
53 } __attribute__((__packed__));
56 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
57 * @async_tx: base DMA asynchronous transaction descriptor
58 * @direction: direction of the DMA transfer
59 * @xfer_shift: log2 of the transfer size
60 * @chcr: value of the channel configuration register for this transfer
61 * @node: entry in the channel's descriptors lists
62 * @chunks: list of transfer chunks for this transfer
63 * @running: the transfer chunk being currently processed
64 * @nchunks: number of transfer chunks for this transfer
65 * @hwdescs.use: whether the transfer descriptor uses hardware descriptors
66 * @hwdescs.mem: hardware descriptors memory for the transfer
67 * @hwdescs.dma: device address of the hardware descriptors memory
68 * @hwdescs.size: size of the hardware descriptors in bytes
69 * @size: transfer size in bytes
70 * @cyclic: when set indicates that the DMA transfer is cyclic
72 struct rcar_dmac_desc {
73 struct dma_async_tx_descriptor async_tx;
74 enum dma_transfer_direction direction;
75 unsigned int xfer_shift;
78 struct list_head node;
79 struct list_head chunks;
80 struct rcar_dmac_xfer_chunk *running;
85 struct rcar_dmac_hw_desc *mem;
94 #define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx)
97 * struct rcar_dmac_desc_page - One page worth of descriptors
98 * @node: entry in the channel's pages list
99 * @descs: array of DMA descriptors
100 * @chunks: array of transfer chunk descriptors
102 struct rcar_dmac_desc_page {
103 struct list_head node;
106 struct rcar_dmac_desc descs[0];
107 struct rcar_dmac_xfer_chunk chunks[0];
111 #define RCAR_DMAC_DESCS_PER_PAGE \
112 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \
113 sizeof(struct rcar_dmac_desc))
114 #define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \
115 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \
116 sizeof(struct rcar_dmac_xfer_chunk))
119 * struct rcar_dmac_chan_slave - Slave configuration
120 * @slave_addr: slave memory address
121 * @xfer_size: size (in bytes) of hardware transfers
123 struct rcar_dmac_chan_slave {
124 phys_addr_t slave_addr;
125 unsigned int xfer_size;
129 * struct rcar_dmac_chan_map - Map of slave device phys to dma address
130 * @addr: slave dma address
131 * @dir: direction of mapping
132 * @slave: slave configuration that is mapped
134 struct rcar_dmac_chan_map {
136 enum dma_data_direction dir;
137 struct rcar_dmac_chan_slave slave;
141 * struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel
142 * @chan: base DMA channel object
143 * @iomem: channel I/O memory base
144 * @index: index of this channel in the controller
146 * @src: slave memory address and size on the source side
147 * @dst: slave memory address and size on the destination side
148 * @mid_rid: hardware MID/RID for the DMA client using this channel
149 * @lock: protects the channel CHCR register and the desc members
150 * @desc.free: list of free descriptors
151 * @desc.pending: list of pending descriptors (submitted with tx_submit)
152 * @desc.active: list of active descriptors (activated with issue_pending)
153 * @desc.done: list of completed descriptors
154 * @desc.wait: list of descriptors waiting for an ack
155 * @desc.running: the descriptor being processed (a member of the active list)
156 * @desc.chunks_free: list of free transfer chunk descriptors
157 * @desc.pages: list of pages used by allocated descriptors
159 struct rcar_dmac_chan {
160 struct dma_chan chan;
165 struct rcar_dmac_chan_slave src;
166 struct rcar_dmac_chan_slave dst;
167 struct rcar_dmac_chan_map map;
173 struct list_head free;
174 struct list_head pending;
175 struct list_head active;
176 struct list_head done;
177 struct list_head wait;
178 struct rcar_dmac_desc *running;
180 struct list_head chunks_free;
182 struct list_head pages;
186 #define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan)
189 * struct rcar_dmac - R-Car Gen2 DMA Controller
190 * @engine: base DMA engine object
191 * @dev: the hardware device
192 * @iomem: remapped I/O memory base
193 * @n_channels: number of available channels
194 * @channels: array of DMAC channels
195 * @modules: bitmask of client modules in use
198 struct dma_device engine;
202 unsigned int n_channels;
203 struct rcar_dmac_chan *channels;
205 DECLARE_BITMAP(modules, 256);
208 #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
210 /* -----------------------------------------------------------------------------
214 #define RCAR_DMAC_CHAN_OFFSET(i) (0x8000 + 0x80 * (i))
216 #define RCAR_DMAISTA 0x0020
217 #define RCAR_DMASEC 0x0030
218 #define RCAR_DMAOR 0x0060
219 #define RCAR_DMAOR_PRI_FIXED (0 << 8)
220 #define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8)
221 #define RCAR_DMAOR_AE (1 << 2)
222 #define RCAR_DMAOR_DME (1 << 0)
223 #define RCAR_DMACHCLR 0x0080
224 #define RCAR_DMADPSEC 0x00a0
226 #define RCAR_DMASAR 0x0000
227 #define RCAR_DMADAR 0x0004
228 #define RCAR_DMATCR 0x0008
229 #define RCAR_DMATCR_MASK 0x00ffffff
230 #define RCAR_DMATSR 0x0028
231 #define RCAR_DMACHCR 0x000c
232 #define RCAR_DMACHCR_CAE (1 << 31)
233 #define RCAR_DMACHCR_CAIE (1 << 30)
234 #define RCAR_DMACHCR_DPM_DISABLED (0 << 28)
235 #define RCAR_DMACHCR_DPM_ENABLED (1 << 28)
236 #define RCAR_DMACHCR_DPM_REPEAT (2 << 28)
237 #define RCAR_DMACHCR_DPM_INFINITE (3 << 28)
238 #define RCAR_DMACHCR_RPT_SAR (1 << 27)
239 #define RCAR_DMACHCR_RPT_DAR (1 << 26)
240 #define RCAR_DMACHCR_RPT_TCR (1 << 25)
241 #define RCAR_DMACHCR_DPB (1 << 22)
242 #define RCAR_DMACHCR_DSE (1 << 19)
243 #define RCAR_DMACHCR_DSIE (1 << 18)
244 #define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3))
245 #define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3))
246 #define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3))
247 #define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3))
248 #define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3))
249 #define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3))
250 #define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3))
251 #define RCAR_DMACHCR_DM_FIXED (0 << 14)
252 #define RCAR_DMACHCR_DM_INC (1 << 14)
253 #define RCAR_DMACHCR_DM_DEC (2 << 14)
254 #define RCAR_DMACHCR_SM_FIXED (0 << 12)
255 #define RCAR_DMACHCR_SM_INC (1 << 12)
256 #define RCAR_DMACHCR_SM_DEC (2 << 12)
257 #define RCAR_DMACHCR_RS_AUTO (4 << 8)
258 #define RCAR_DMACHCR_RS_DMARS (8 << 8)
259 #define RCAR_DMACHCR_IE (1 << 2)
260 #define RCAR_DMACHCR_TE (1 << 1)
261 #define RCAR_DMACHCR_DE (1 << 0)
262 #define RCAR_DMATCRB 0x0018
263 #define RCAR_DMATSRB 0x0038
264 #define RCAR_DMACHCRB 0x001c
265 #define RCAR_DMACHCRB_DCNT(n) ((n) << 24)
266 #define RCAR_DMACHCRB_DPTR_MASK (0xff << 16)
267 #define RCAR_DMACHCRB_DPTR_SHIFT 16
268 #define RCAR_DMACHCRB_DRST (1 << 15)
269 #define RCAR_DMACHCRB_DTS (1 << 8)
270 #define RCAR_DMACHCRB_SLM_NORMAL (0 << 4)
271 #define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4)
272 #define RCAR_DMACHCRB_PRI(n) ((n) << 0)
273 #define RCAR_DMARS 0x0040
274 #define RCAR_DMABUFCR 0x0048
275 #define RCAR_DMABUFCR_MBU(n) ((n) << 16)
276 #define RCAR_DMABUFCR_ULB(n) ((n) << 0)
277 #define RCAR_DMADPBASE 0x0050
278 #define RCAR_DMADPBASE_MASK 0xfffffff0
279 #define RCAR_DMADPBASE_SEL (1 << 0)
280 #define RCAR_DMADPCR 0x0054
281 #define RCAR_DMADPCR_DIPT(n) ((n) << 24)
282 #define RCAR_DMAFIXSAR 0x0010
283 #define RCAR_DMAFIXDAR 0x0014
284 #define RCAR_DMAFIXDPBASE 0x0060
286 /* Hardcode the MEMCPY transfer size to 4 bytes. */
287 #define RCAR_DMAC_MEMCPY_XFER_SIZE 4
289 /* -----------------------------------------------------------------------------
293 static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data)
295 if (reg == RCAR_DMAOR)
296 writew(data, dmac->iomem + reg);
298 writel(data, dmac->iomem + reg);
301 static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg)
303 if (reg == RCAR_DMAOR)
304 return readw(dmac->iomem + reg);
306 return readl(dmac->iomem + reg);
309 static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg)
311 if (reg == RCAR_DMARS)
312 return readw(chan->iomem + reg);
314 return readl(chan->iomem + reg);
317 static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
319 if (reg == RCAR_DMARS)
320 writew(data, chan->iomem + reg);
322 writel(data, chan->iomem + reg);
325 /* -----------------------------------------------------------------------------
326 * Initialization and configuration
329 static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan)
331 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
333 return !!(chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE));
336 static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
338 struct rcar_dmac_desc *desc = chan->desc.running;
339 u32 chcr = desc->chcr;
341 WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan));
343 if (chan->mid_rid >= 0)
344 rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
346 if (desc->hwdescs.use) {
347 struct rcar_dmac_xfer_chunk *chunk =
348 list_first_entry(&desc->chunks,
349 struct rcar_dmac_xfer_chunk, node);
351 dev_dbg(chan->chan.device->dev,
352 "chan%u: queue desc %p: %u@%pad\n",
353 chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
355 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
356 rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
357 chunk->src_addr >> 32);
358 rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
359 chunk->dst_addr >> 32);
360 rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
361 desc->hwdescs.dma >> 32);
363 rcar_dmac_chan_write(chan, RCAR_DMADPBASE,
364 (desc->hwdescs.dma & 0xfffffff0) |
366 rcar_dmac_chan_write(chan, RCAR_DMACHCRB,
367 RCAR_DMACHCRB_DCNT(desc->nchunks - 1) |
371 * Errata: When descriptor memory is accessed through an IOMMU
372 * the DMADAR register isn't initialized automatically from the
373 * first descriptor at beginning of transfer by the DMAC like it
374 * should. Initialize it manually with the destination address
375 * of the first chunk.
377 rcar_dmac_chan_write(chan, RCAR_DMADAR,
378 chunk->dst_addr & 0xffffffff);
381 * Program the descriptor stage interrupt to occur after the end
382 * of the first stage.
384 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1));
386 chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
387 | RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB;
390 * If the descriptor isn't cyclic enable normal descriptor mode
391 * and the transfer completion interrupt.
394 chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
396 * If the descriptor is cyclic and has a callback enable the
397 * descriptor stage interrupt in infinite repeat mode.
399 else if (desc->async_tx.callback)
400 chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
402 * Otherwise just select infinite repeat mode without any
406 chcr |= RCAR_DMACHCR_DPM_INFINITE;
408 struct rcar_dmac_xfer_chunk *chunk = desc->running;
410 dev_dbg(chan->chan.device->dev,
411 "chan%u: queue chunk %p: %u@%pad -> %pad\n",
412 chan->index, chunk, chunk->size, &chunk->src_addr,
415 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
416 rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
417 chunk->src_addr >> 32);
418 rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
419 chunk->dst_addr >> 32);
421 rcar_dmac_chan_write(chan, RCAR_DMASAR,
422 chunk->src_addr & 0xffffffff);
423 rcar_dmac_chan_write(chan, RCAR_DMADAR,
424 chunk->dst_addr & 0xffffffff);
425 rcar_dmac_chan_write(chan, RCAR_DMATCR,
426 chunk->size >> desc->xfer_shift);
428 chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
431 rcar_dmac_chan_write(chan, RCAR_DMACHCR,
432 chcr | RCAR_DMACHCR_DE | RCAR_DMACHCR_CAIE);
435 static int rcar_dmac_init(struct rcar_dmac *dmac)
439 /* Clear all channels and enable the DMAC globally. */
440 rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
441 rcar_dmac_write(dmac, RCAR_DMAOR,
442 RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
444 dmaor = rcar_dmac_read(dmac, RCAR_DMAOR);
445 if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) {
446 dev_warn(dmac->dev, "DMAOR initialization failed.\n");
453 /* -----------------------------------------------------------------------------
454 * Descriptors submission
457 static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx)
459 struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan);
460 struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx);
464 spin_lock_irqsave(&chan->lock, flags);
466 cookie = dma_cookie_assign(tx);
468 dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n",
469 chan->index, tx->cookie, desc);
471 list_add_tail(&desc->node, &chan->desc.pending);
472 desc->running = list_first_entry(&desc->chunks,
473 struct rcar_dmac_xfer_chunk, node);
475 spin_unlock_irqrestore(&chan->lock, flags);
480 /* -----------------------------------------------------------------------------
481 * Descriptors allocation and free
485 * rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors
486 * @chan: the DMA channel
487 * @gfp: allocation flags
489 static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
491 struct rcar_dmac_desc_page *page;
496 page = (void *)get_zeroed_page(gfp);
500 for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) {
501 struct rcar_dmac_desc *desc = &page->descs[i];
503 dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
504 desc->async_tx.tx_submit = rcar_dmac_tx_submit;
505 INIT_LIST_HEAD(&desc->chunks);
507 list_add_tail(&desc->node, &list);
510 spin_lock_irqsave(&chan->lock, flags);
511 list_splice_tail(&list, &chan->desc.free);
512 list_add_tail(&page->node, &chan->desc.pages);
513 spin_unlock_irqrestore(&chan->lock, flags);
519 * rcar_dmac_desc_put - Release a DMA transfer descriptor
520 * @chan: the DMA channel
521 * @desc: the descriptor
523 * Put the descriptor and its transfer chunk descriptors back in the channel's
524 * free descriptors lists. The descriptor's chunks list will be reinitialized to
525 * an empty list as a result.
527 * The descriptor must have been removed from the channel's lists before calling
530 static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan,
531 struct rcar_dmac_desc *desc)
535 spin_lock_irqsave(&chan->lock, flags);
536 list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free);
537 list_add(&desc->node, &chan->desc.free);
538 spin_unlock_irqrestore(&chan->lock, flags);
541 static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan)
543 struct rcar_dmac_desc *desc, *_desc;
548 * We have to temporarily move all descriptors from the wait list to a
549 * local list as iterating over the wait list, even with
550 * list_for_each_entry_safe, isn't safe if we release the channel lock
551 * around the rcar_dmac_desc_put() call.
553 spin_lock_irqsave(&chan->lock, flags);
554 list_splice_init(&chan->desc.wait, &list);
555 spin_unlock_irqrestore(&chan->lock, flags);
557 list_for_each_entry_safe(desc, _desc, &list, node) {
558 if (async_tx_test_ack(&desc->async_tx)) {
559 list_del(&desc->node);
560 rcar_dmac_desc_put(chan, desc);
564 if (list_empty(&list))
567 /* Put the remaining descriptors back in the wait list. */
568 spin_lock_irqsave(&chan->lock, flags);
569 list_splice(&list, &chan->desc.wait);
570 spin_unlock_irqrestore(&chan->lock, flags);
574 * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer
575 * @chan: the DMA channel
577 * Locking: This function must be called in a non-atomic context.
579 * Return: A pointer to the allocated descriptor or NULL if no descriptor can
582 static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan)
584 struct rcar_dmac_desc *desc;
588 /* Recycle acked descriptors before attempting allocation. */
589 rcar_dmac_desc_recycle_acked(chan);
591 spin_lock_irqsave(&chan->lock, flags);
593 while (list_empty(&chan->desc.free)) {
595 * No free descriptors, allocate a page worth of them and try
596 * again, as someone else could race us to get the newly
597 * allocated descriptors. If the allocation fails return an
600 spin_unlock_irqrestore(&chan->lock, flags);
601 ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT);
604 spin_lock_irqsave(&chan->lock, flags);
607 desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc, node);
608 list_del(&desc->node);
610 spin_unlock_irqrestore(&chan->lock, flags);
616 * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks
617 * @chan: the DMA channel
618 * @gfp: allocation flags
620 static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
622 struct rcar_dmac_desc_page *page;
627 page = (void *)get_zeroed_page(gfp);
631 for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) {
632 struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i];
634 list_add_tail(&chunk->node, &list);
637 spin_lock_irqsave(&chan->lock, flags);
638 list_splice_tail(&list, &chan->desc.chunks_free);
639 list_add_tail(&page->node, &chan->desc.pages);
640 spin_unlock_irqrestore(&chan->lock, flags);
646 * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer
647 * @chan: the DMA channel
649 * Locking: This function must be called in a non-atomic context.
651 * Return: A pointer to the allocated transfer chunk descriptor or NULL if no
652 * descriptor can be allocated.
654 static struct rcar_dmac_xfer_chunk *
655 rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan)
657 struct rcar_dmac_xfer_chunk *chunk;
661 spin_lock_irqsave(&chan->lock, flags);
663 while (list_empty(&chan->desc.chunks_free)) {
665 * No free descriptors, allocate a page worth of them and try
666 * again, as someone else could race us to get the newly
667 * allocated descriptors. If the allocation fails return an
670 spin_unlock_irqrestore(&chan->lock, flags);
671 ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT);
674 spin_lock_irqsave(&chan->lock, flags);
677 chunk = list_first_entry(&chan->desc.chunks_free,
678 struct rcar_dmac_xfer_chunk, node);
679 list_del(&chunk->node);
681 spin_unlock_irqrestore(&chan->lock, flags);
686 static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan,
687 struct rcar_dmac_desc *desc, size_t size)
690 * dma_alloc_coherent() allocates memory in page size increments. To
691 * avoid reallocating the hardware descriptors when the allocated size
692 * wouldn't change align the requested size to a multiple of the page
695 size = PAGE_ALIGN(size);
697 if (desc->hwdescs.size == size)
700 if (desc->hwdescs.mem) {
701 dma_free_coherent(chan->chan.device->dev, desc->hwdescs.size,
702 desc->hwdescs.mem, desc->hwdescs.dma);
703 desc->hwdescs.mem = NULL;
704 desc->hwdescs.size = 0;
710 desc->hwdescs.mem = dma_alloc_coherent(chan->chan.device->dev, size,
711 &desc->hwdescs.dma, GFP_NOWAIT);
712 if (!desc->hwdescs.mem)
715 desc->hwdescs.size = size;
718 static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan,
719 struct rcar_dmac_desc *desc)
721 struct rcar_dmac_xfer_chunk *chunk;
722 struct rcar_dmac_hw_desc *hwdesc;
724 rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc));
726 hwdesc = desc->hwdescs.mem;
730 list_for_each_entry(chunk, &desc->chunks, node) {
731 hwdesc->sar = chunk->src_addr;
732 hwdesc->dar = chunk->dst_addr;
733 hwdesc->tcr = chunk->size >> desc->xfer_shift;
740 /* -----------------------------------------------------------------------------
743 static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
749 * Ensure that the setting of the DE bit is actually 0 after
752 for (i = 0; i < 1024; i++) {
753 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
754 if (!(chcr & RCAR_DMACHCR_DE))
759 dev_err(chan->chan.device->dev, "CHCR DE check error\n");
762 static void rcar_dmac_sync_tcr(struct rcar_dmac_chan *chan)
764 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
766 if (!(chcr & RCAR_DMACHCR_DE))
769 /* set DE=0 and flush remaining data */
770 rcar_dmac_chan_write(chan, RCAR_DMACHCR, (chcr & ~RCAR_DMACHCR_DE));
772 /* make sure all remaining data was flushed */
773 rcar_dmac_chcr_de_barrier(chan);
776 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
779 static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
781 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
783 chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
784 RCAR_DMACHCR_TE | RCAR_DMACHCR_DE |
785 RCAR_DMACHCR_CAE | RCAR_DMACHCR_CAIE);
786 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
787 rcar_dmac_chcr_de_barrier(chan);
790 static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
792 struct rcar_dmac_desc *desc, *_desc;
796 spin_lock_irqsave(&chan->lock, flags);
798 /* Move all non-free descriptors to the local lists. */
799 list_splice_init(&chan->desc.pending, &descs);
800 list_splice_init(&chan->desc.active, &descs);
801 list_splice_init(&chan->desc.done, &descs);
802 list_splice_init(&chan->desc.wait, &descs);
804 chan->desc.running = NULL;
806 spin_unlock_irqrestore(&chan->lock, flags);
808 list_for_each_entry_safe(desc, _desc, &descs, node) {
809 list_del(&desc->node);
810 rcar_dmac_desc_put(chan, desc);
814 static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
818 /* Stop all channels. */
819 for (i = 0; i < dmac->n_channels; ++i) {
820 struct rcar_dmac_chan *chan = &dmac->channels[i];
822 /* Stop and reinitialize the channel. */
823 spin_lock_irq(&chan->lock);
824 rcar_dmac_chan_halt(chan);
825 spin_unlock_irq(&chan->lock);
830 /* -----------------------------------------------------------------------------
831 * Descriptors preparation
834 static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan,
835 struct rcar_dmac_desc *desc)
837 static const u32 chcr_ts[] = {
838 RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B,
839 RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B,
840 RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B,
844 unsigned int xfer_size;
847 switch (desc->direction) {
849 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED
850 | RCAR_DMACHCR_RS_DMARS;
851 xfer_size = chan->src.xfer_size;
855 chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC
856 | RCAR_DMACHCR_RS_DMARS;
857 xfer_size = chan->dst.xfer_size;
862 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC
863 | RCAR_DMACHCR_RS_AUTO;
864 xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE;
868 desc->xfer_shift = ilog2(xfer_size);
869 desc->chcr = chcr | chcr_ts[desc->xfer_shift];
873 * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list
875 * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
876 * converted to scatter-gather to guarantee consistent locking and a correct
877 * list manipulation. For slave DMA direction carries the usual meaning, and,
878 * logically, the SG list is RAM and the addr variable contains slave address,
879 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
880 * and the SG list contains only one element and points at the source buffer.
882 static struct dma_async_tx_descriptor *
883 rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
884 unsigned int sg_len, dma_addr_t dev_addr,
885 enum dma_transfer_direction dir, unsigned long dma_flags,
888 struct rcar_dmac_xfer_chunk *chunk;
889 struct rcar_dmac_desc *desc;
890 struct scatterlist *sg;
891 unsigned int nchunks = 0;
892 unsigned int max_chunk_size;
893 unsigned int full_size = 0;
894 bool cross_boundary = false;
896 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
901 desc = rcar_dmac_desc_get(chan);
905 desc->async_tx.flags = dma_flags;
906 desc->async_tx.cookie = -EBUSY;
908 desc->cyclic = cyclic;
909 desc->direction = dir;
911 rcar_dmac_chan_configure_desc(chan, desc);
913 max_chunk_size = RCAR_DMATCR_MASK << desc->xfer_shift;
916 * Allocate and fill the transfer chunk descriptors. We own the only
917 * reference to the DMA descriptor, there's no need for locking.
919 for_each_sg(sgl, sg, sg_len, i) {
920 dma_addr_t mem_addr = sg_dma_address(sg);
921 unsigned int len = sg_dma_len(sg);
925 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
927 high_dev_addr = dev_addr >> 32;
928 high_mem_addr = mem_addr >> 32;
931 if ((dev_addr >> 32 != high_dev_addr) ||
932 (mem_addr >> 32 != high_mem_addr))
933 cross_boundary = true;
936 unsigned int size = min(len, max_chunk_size);
938 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
940 * Prevent individual transfers from crossing 4GB
943 if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) {
944 size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
945 cross_boundary = true;
947 if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) {
948 size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
949 cross_boundary = true;
953 chunk = rcar_dmac_xfer_chunk_get(chan);
955 rcar_dmac_desc_put(chan, desc);
959 if (dir == DMA_DEV_TO_MEM) {
960 chunk->src_addr = dev_addr;
961 chunk->dst_addr = mem_addr;
963 chunk->src_addr = mem_addr;
964 chunk->dst_addr = dev_addr;
969 dev_dbg(chan->chan.device->dev,
970 "chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n",
971 chan->index, chunk, desc, i, sg, size, len,
972 &chunk->src_addr, &chunk->dst_addr);
975 if (dir == DMA_MEM_TO_MEM)
980 list_add_tail(&chunk->node, &desc->chunks);
985 desc->nchunks = nchunks;
986 desc->size = full_size;
989 * Use hardware descriptor lists if possible when more than one chunk
990 * needs to be transferred (otherwise they don't make much sense).
992 * Source/Destination address should be located in same 4GiB region
993 * in the 40bit address space when it uses Hardware descriptor,
994 * and cross_boundary is checking it.
996 desc->hwdescs.use = !cross_boundary && nchunks > 1;
997 if (desc->hwdescs.use) {
998 if (rcar_dmac_fill_hwdesc(chan, desc) < 0)
999 desc->hwdescs.use = false;
1002 return &desc->async_tx;
1005 /* -----------------------------------------------------------------------------
1006 * DMA engine operations
1009 static int rcar_dmac_alloc_chan_resources(struct dma_chan *chan)
1011 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1014 INIT_LIST_HEAD(&rchan->desc.chunks_free);
1015 INIT_LIST_HEAD(&rchan->desc.pages);
1017 /* Preallocate descriptors. */
1018 ret = rcar_dmac_xfer_chunk_alloc(rchan, GFP_KERNEL);
1022 ret = rcar_dmac_desc_alloc(rchan, GFP_KERNEL);
1026 return pm_runtime_get_sync(chan->device->dev);
1029 static void rcar_dmac_free_chan_resources(struct dma_chan *chan)
1031 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1032 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
1033 struct rcar_dmac_chan_map *map = &rchan->map;
1034 struct rcar_dmac_desc_page *page, *_page;
1035 struct rcar_dmac_desc *desc;
1038 /* Protect against ISR */
1039 spin_lock_irq(&rchan->lock);
1040 rcar_dmac_chan_halt(rchan);
1041 spin_unlock_irq(&rchan->lock);
1044 * Now no new interrupts will occur, but one might already be
1045 * running. Wait for it to finish before freeing resources.
1047 synchronize_irq(rchan->irq);
1049 if (rchan->mid_rid >= 0) {
1050 /* The caller is holding dma_list_mutex */
1051 clear_bit(rchan->mid_rid, dmac->modules);
1052 rchan->mid_rid = -EINVAL;
1055 list_splice_init(&rchan->desc.free, &list);
1056 list_splice_init(&rchan->desc.pending, &list);
1057 list_splice_init(&rchan->desc.active, &list);
1058 list_splice_init(&rchan->desc.done, &list);
1059 list_splice_init(&rchan->desc.wait, &list);
1061 rchan->desc.running = NULL;
1063 list_for_each_entry(desc, &list, node)
1064 rcar_dmac_realloc_hwdesc(rchan, desc, 0);
1066 list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) {
1067 list_del(&page->node);
1068 free_page((unsigned long)page);
1071 /* Remove slave mapping if present. */
1072 if (map->slave.xfer_size) {
1073 dma_unmap_resource(chan->device->dev, map->addr,
1074 map->slave.xfer_size, map->dir, 0);
1075 map->slave.xfer_size = 0;
1078 pm_runtime_put(chan->device->dev);
1081 static struct dma_async_tx_descriptor *
1082 rcar_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
1083 dma_addr_t dma_src, size_t len, unsigned long flags)
1085 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1086 struct scatterlist sgl;
1091 sg_init_table(&sgl, 1);
1092 sg_set_page(&sgl, pfn_to_page(PFN_DOWN(dma_src)), len,
1093 offset_in_page(dma_src));
1094 sg_dma_address(&sgl) = dma_src;
1095 sg_dma_len(&sgl) = len;
1097 return rcar_dmac_chan_prep_sg(rchan, &sgl, 1, dma_dest,
1098 DMA_MEM_TO_MEM, flags, false);
1101 static int rcar_dmac_map_slave_addr(struct dma_chan *chan,
1102 enum dma_transfer_direction dir)
1104 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1105 struct rcar_dmac_chan_map *map = &rchan->map;
1106 phys_addr_t dev_addr;
1108 enum dma_data_direction dev_dir;
1110 if (dir == DMA_DEV_TO_MEM) {
1111 dev_addr = rchan->src.slave_addr;
1112 dev_size = rchan->src.xfer_size;
1113 dev_dir = DMA_TO_DEVICE;
1115 dev_addr = rchan->dst.slave_addr;
1116 dev_size = rchan->dst.xfer_size;
1117 dev_dir = DMA_FROM_DEVICE;
1120 /* Reuse current map if possible. */
1121 if (dev_addr == map->slave.slave_addr &&
1122 dev_size == map->slave.xfer_size &&
1123 dev_dir == map->dir)
1126 /* Remove old mapping if present. */
1127 if (map->slave.xfer_size)
1128 dma_unmap_resource(chan->device->dev, map->addr,
1129 map->slave.xfer_size, map->dir, 0);
1130 map->slave.xfer_size = 0;
1132 /* Create new slave address map. */
1133 map->addr = dma_map_resource(chan->device->dev, dev_addr, dev_size,
1136 if (dma_mapping_error(chan->device->dev, map->addr)) {
1137 dev_err(chan->device->dev,
1138 "chan%u: failed to map %zx@%pap", rchan->index,
1139 dev_size, &dev_addr);
1143 dev_dbg(chan->device->dev, "chan%u: map %zx@%pap to %pad dir: %s\n",
1144 rchan->index, dev_size, &dev_addr, &map->addr,
1145 dev_dir == DMA_TO_DEVICE ? "DMA_TO_DEVICE" : "DMA_FROM_DEVICE");
1147 map->slave.slave_addr = dev_addr;
1148 map->slave.xfer_size = dev_size;
1154 static struct dma_async_tx_descriptor *
1155 rcar_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1156 unsigned int sg_len, enum dma_transfer_direction dir,
1157 unsigned long flags, void *context)
1159 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1161 /* Someone calling slave DMA on a generic channel? */
1162 if (rchan->mid_rid < 0 || !sg_len) {
1163 dev_warn(chan->device->dev,
1164 "%s: bad parameter: len=%d, id=%d\n",
1165 __func__, sg_len, rchan->mid_rid);
1169 if (rcar_dmac_map_slave_addr(chan, dir))
1172 return rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, rchan->map.addr,
1176 #define RCAR_DMAC_MAX_SG_LEN 32
1178 static struct dma_async_tx_descriptor *
1179 rcar_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
1180 size_t buf_len, size_t period_len,
1181 enum dma_transfer_direction dir, unsigned long flags)
1183 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1184 struct dma_async_tx_descriptor *desc;
1185 struct scatterlist *sgl;
1186 unsigned int sg_len;
1189 /* Someone calling slave DMA on a generic channel? */
1190 if (rchan->mid_rid < 0 || buf_len < period_len) {
1191 dev_warn(chan->device->dev,
1192 "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n",
1193 __func__, buf_len, period_len, rchan->mid_rid);
1197 if (rcar_dmac_map_slave_addr(chan, dir))
1200 sg_len = buf_len / period_len;
1201 if (sg_len > RCAR_DMAC_MAX_SG_LEN) {
1202 dev_err(chan->device->dev,
1203 "chan%u: sg length %d exceds limit %d",
1204 rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN);
1209 * Allocate the sg list dynamically as it would consume too much stack
1212 sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT);
1216 sg_init_table(sgl, sg_len);
1218 for (i = 0; i < sg_len; ++i) {
1219 dma_addr_t src = buf_addr + (period_len * i);
1221 sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len,
1222 offset_in_page(src));
1223 sg_dma_address(&sgl[i]) = src;
1224 sg_dma_len(&sgl[i]) = period_len;
1227 desc = rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, rchan->map.addr,
1234 static int rcar_dmac_device_config(struct dma_chan *chan,
1235 struct dma_slave_config *cfg)
1237 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1240 * We could lock this, but you shouldn't be configuring the
1241 * channel, while using it...
1243 rchan->src.slave_addr = cfg->src_addr;
1244 rchan->dst.slave_addr = cfg->dst_addr;
1245 rchan->src.xfer_size = cfg->src_addr_width;
1246 rchan->dst.xfer_size = cfg->dst_addr_width;
1251 static int rcar_dmac_chan_terminate_all(struct dma_chan *chan)
1253 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1254 unsigned long flags;
1256 spin_lock_irqsave(&rchan->lock, flags);
1257 rcar_dmac_chan_halt(rchan);
1258 spin_unlock_irqrestore(&rchan->lock, flags);
1261 * FIXME: No new interrupt can occur now, but the IRQ thread might still
1265 rcar_dmac_chan_reinit(rchan);
1270 static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
1271 dma_cookie_t cookie)
1273 struct rcar_dmac_desc *desc = chan->desc.running;
1274 struct rcar_dmac_xfer_chunk *running = NULL;
1275 struct rcar_dmac_xfer_chunk *chunk;
1276 enum dma_status status;
1277 unsigned int residue = 0;
1278 unsigned int dptr = 0;
1284 * If the cookie corresponds to a descriptor that has been completed
1285 * there is no residue. The same check has already been performed by the
1286 * caller but without holding the channel lock, so the descriptor could
1289 status = dma_cookie_status(&chan->chan, cookie, NULL);
1290 if (status == DMA_COMPLETE)
1294 * If the cookie doesn't correspond to the currently running transfer
1295 * then the descriptor hasn't been processed yet, and the residue is
1296 * equal to the full descriptor size.
1297 * Also, a client driver is possible to call this function before
1298 * rcar_dmac_isr_channel_thread() runs. In this case, the "desc.running"
1299 * will be the next descriptor, and the done list will appear. So, if
1300 * the argument cookie matches the done list's cookie, we can assume
1301 * the residue is zero.
1303 if (cookie != desc->async_tx.cookie) {
1304 list_for_each_entry(desc, &chan->desc.done, node) {
1305 if (cookie == desc->async_tx.cookie)
1308 list_for_each_entry(desc, &chan->desc.pending, node) {
1309 if (cookie == desc->async_tx.cookie)
1312 list_for_each_entry(desc, &chan->desc.active, node) {
1313 if (cookie == desc->async_tx.cookie)
1318 * No descriptor found for the cookie, there's thus no residue.
1319 * This shouldn't happen if the calling driver passes a correct
1322 WARN(1, "No descriptor for cookie!");
1327 * In descriptor mode the descriptor running pointer is not maintained
1328 * by the interrupt handler, find the running descriptor from the
1329 * descriptor pointer field in the CHCRB register. In non-descriptor
1330 * mode just use the running descriptor pointer.
1332 if (desc->hwdescs.use) {
1333 dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1334 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1336 dptr = desc->nchunks;
1338 WARN_ON(dptr >= desc->nchunks);
1340 running = desc->running;
1343 /* Compute the size of all chunks still to be transferred. */
1344 list_for_each_entry_reverse(chunk, &desc->chunks, node) {
1345 if (chunk == running || ++dptr == desc->nchunks)
1348 residue += chunk->size;
1351 if (desc->direction == DMA_DEV_TO_MEM)
1352 rcar_dmac_sync_tcr(chan);
1354 /* Add the residue for the current chunk. */
1355 residue += rcar_dmac_chan_read(chan, RCAR_DMATCRB) << desc->xfer_shift;
1360 static enum dma_status rcar_dmac_tx_status(struct dma_chan *chan,
1361 dma_cookie_t cookie,
1362 struct dma_tx_state *txstate)
1364 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1365 enum dma_status status;
1366 unsigned long flags;
1367 unsigned int residue;
1369 status = dma_cookie_status(chan, cookie, txstate);
1370 if (status == DMA_COMPLETE || !txstate)
1373 spin_lock_irqsave(&rchan->lock, flags);
1374 residue = rcar_dmac_chan_get_residue(rchan, cookie);
1375 spin_unlock_irqrestore(&rchan->lock, flags);
1377 /* if there's no residue, the cookie is complete */
1379 return DMA_COMPLETE;
1381 dma_set_residue(txstate, residue);
1386 static void rcar_dmac_issue_pending(struct dma_chan *chan)
1388 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1389 unsigned long flags;
1391 spin_lock_irqsave(&rchan->lock, flags);
1393 if (list_empty(&rchan->desc.pending))
1396 /* Append the pending list to the active list. */
1397 list_splice_tail_init(&rchan->desc.pending, &rchan->desc.active);
1400 * If no transfer is running pick the first descriptor from the active
1401 * list and start the transfer.
1403 if (!rchan->desc.running) {
1404 struct rcar_dmac_desc *desc;
1406 desc = list_first_entry(&rchan->desc.active,
1407 struct rcar_dmac_desc, node);
1408 rchan->desc.running = desc;
1410 rcar_dmac_chan_start_xfer(rchan);
1414 spin_unlock_irqrestore(&rchan->lock, flags);
1417 static void rcar_dmac_device_synchronize(struct dma_chan *chan)
1419 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1421 synchronize_irq(rchan->irq);
1424 /* -----------------------------------------------------------------------------
1428 static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan)
1430 struct rcar_dmac_desc *desc = chan->desc.running;
1433 if (WARN_ON(!desc || !desc->cyclic)) {
1435 * This should never happen, there should always be a running
1436 * cyclic descriptor when a descriptor stage end interrupt is
1437 * triggered. Warn and return.
1442 /* Program the interrupt pointer to the next stage. */
1443 stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1444 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1445 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage));
1447 return IRQ_WAKE_THREAD;
1450 static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan)
1452 struct rcar_dmac_desc *desc = chan->desc.running;
1453 irqreturn_t ret = IRQ_WAKE_THREAD;
1455 if (WARN_ON_ONCE(!desc)) {
1457 * This should never happen, there should always be a running
1458 * descriptor when a transfer end interrupt is triggered. Warn
1465 * The transfer end interrupt isn't generated for each chunk when using
1466 * descriptor mode. Only update the running chunk pointer in
1467 * non-descriptor mode.
1469 if (!desc->hwdescs.use) {
1471 * If we haven't completed the last transfer chunk simply move
1472 * to the next one. Only wake the IRQ thread if the transfer is
1475 if (!list_is_last(&desc->running->node, &desc->chunks)) {
1476 desc->running = list_next_entry(desc->running, node);
1483 * We've completed the last transfer chunk. If the transfer is
1484 * cyclic, move back to the first one.
1488 list_first_entry(&desc->chunks,
1489 struct rcar_dmac_xfer_chunk,
1495 /* The descriptor is complete, move it to the done list. */
1496 list_move_tail(&desc->node, &chan->desc.done);
1498 /* Queue the next descriptor, if any. */
1499 if (!list_empty(&chan->desc.active))
1500 chan->desc.running = list_first_entry(&chan->desc.active,
1501 struct rcar_dmac_desc,
1504 chan->desc.running = NULL;
1507 if (chan->desc.running)
1508 rcar_dmac_chan_start_xfer(chan);
1513 static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
1515 u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE;
1516 struct rcar_dmac_chan *chan = dev;
1517 irqreturn_t ret = IRQ_NONE;
1518 bool reinit = false;
1521 spin_lock(&chan->lock);
1523 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
1524 if (chcr & RCAR_DMACHCR_CAE) {
1525 rcar_dmac_chan_halt(chan);
1530 if (chcr & RCAR_DMACHCR_TE)
1531 mask |= RCAR_DMACHCR_DE;
1532 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
1533 if (mask & RCAR_DMACHCR_DE)
1534 rcar_dmac_chcr_de_barrier(chan);
1536 if (chcr & RCAR_DMACHCR_DSE)
1537 ret |= rcar_dmac_isr_desc_stage_end(chan);
1539 if (chcr & RCAR_DMACHCR_TE)
1540 ret |= rcar_dmac_isr_transfer_end(chan);
1543 spin_unlock(&chan->lock);
1546 dev_err(chan->chan.device->dev, "Channel Address Error\n");
1548 rcar_dmac_chan_reinit(chan);
1555 static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev)
1557 struct rcar_dmac_chan *chan = dev;
1558 struct rcar_dmac_desc *desc;
1559 struct dmaengine_desc_callback cb;
1561 spin_lock_irq(&chan->lock);
1563 /* For cyclic transfers notify the user after every chunk. */
1564 if (chan->desc.running && chan->desc.running->cyclic) {
1565 desc = chan->desc.running;
1566 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1568 if (dmaengine_desc_callback_valid(&cb)) {
1569 spin_unlock_irq(&chan->lock);
1570 dmaengine_desc_callback_invoke(&cb, NULL);
1571 spin_lock_irq(&chan->lock);
1576 * Call the callback function for all descriptors on the done list and
1577 * move them to the ack wait list.
1579 while (!list_empty(&chan->desc.done)) {
1580 desc = list_first_entry(&chan->desc.done, struct rcar_dmac_desc,
1582 dma_cookie_complete(&desc->async_tx);
1583 list_del(&desc->node);
1585 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1586 if (dmaengine_desc_callback_valid(&cb)) {
1587 spin_unlock_irq(&chan->lock);
1589 * We own the only reference to this descriptor, we can
1590 * safely dereference it without holding the channel
1593 dmaengine_desc_callback_invoke(&cb, NULL);
1594 spin_lock_irq(&chan->lock);
1597 list_add_tail(&desc->node, &chan->desc.wait);
1600 spin_unlock_irq(&chan->lock);
1602 /* Recycle all acked descriptors. */
1603 rcar_dmac_desc_recycle_acked(chan);
1608 /* -----------------------------------------------------------------------------
1609 * OF xlate and channel filter
1612 static bool rcar_dmac_chan_filter(struct dma_chan *chan, void *arg)
1614 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
1615 struct of_phandle_args *dma_spec = arg;
1618 * FIXME: Using a filter on OF platforms is a nonsense. The OF xlate
1619 * function knows from which device it wants to allocate a channel from,
1620 * and would be perfectly capable of selecting the channel it wants.
1621 * Forcing it to call dma_request_channel() and iterate through all
1622 * channels from all controllers is just pointless.
1624 if (chan->device->device_config != rcar_dmac_device_config ||
1625 dma_spec->np != chan->device->dev->of_node)
1628 return !test_and_set_bit(dma_spec->args[0], dmac->modules);
1631 static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec,
1632 struct of_dma *ofdma)
1634 struct rcar_dmac_chan *rchan;
1635 struct dma_chan *chan;
1636 dma_cap_mask_t mask;
1638 if (dma_spec->args_count != 1)
1641 /* Only slave DMA channels can be allocated via DT */
1643 dma_cap_set(DMA_SLAVE, mask);
1645 chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec);
1649 rchan = to_rcar_dmac_chan(chan);
1650 rchan->mid_rid = dma_spec->args[0];
1655 /* -----------------------------------------------------------------------------
1660 static int rcar_dmac_runtime_suspend(struct device *dev)
1665 static int rcar_dmac_runtime_resume(struct device *dev)
1667 struct rcar_dmac *dmac = dev_get_drvdata(dev);
1669 return rcar_dmac_init(dmac);
1673 static const struct dev_pm_ops rcar_dmac_pm = {
1675 * TODO for system sleep/resume:
1676 * - Wait for the current transfer to complete and stop the device,
1677 * - Resume transfers, if any.
1679 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1680 pm_runtime_force_resume)
1681 SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
1685 /* -----------------------------------------------------------------------------
1689 static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
1690 struct rcar_dmac_chan *rchan,
1693 struct platform_device *pdev = to_platform_device(dmac->dev);
1694 struct dma_chan *chan = &rchan->chan;
1695 char pdev_irqname[5];
1699 rchan->index = index;
1700 rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index);
1701 rchan->mid_rid = -EINVAL;
1703 spin_lock_init(&rchan->lock);
1705 INIT_LIST_HEAD(&rchan->desc.free);
1706 INIT_LIST_HEAD(&rchan->desc.pending);
1707 INIT_LIST_HEAD(&rchan->desc.active);
1708 INIT_LIST_HEAD(&rchan->desc.done);
1709 INIT_LIST_HEAD(&rchan->desc.wait);
1711 /* Request the channel interrupt. */
1712 sprintf(pdev_irqname, "ch%u", index);
1713 rchan->irq = platform_get_irq_byname(pdev, pdev_irqname);
1714 if (rchan->irq < 0) {
1715 dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
1719 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
1720 dev_name(dmac->dev), index);
1725 * Initialize the DMA engine channel and add it to the DMA engine
1728 chan->device = &dmac->engine;
1729 dma_cookie_init(chan);
1731 list_add_tail(&chan->device_node, &dmac->engine.channels);
1733 ret = devm_request_threaded_irq(dmac->dev, rchan->irq,
1734 rcar_dmac_isr_channel,
1735 rcar_dmac_isr_channel_thread, 0,
1738 dev_err(dmac->dev, "failed to request IRQ %u (%d)\n",
1746 static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
1748 struct device_node *np = dev->of_node;
1751 ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels);
1753 dev_err(dev, "unable to read dma-channels property\n");
1757 if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
1758 dev_err(dev, "invalid number of channels %u\n",
1766 static int rcar_dmac_probe(struct platform_device *pdev)
1768 const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE |
1769 DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
1770 DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
1771 DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
1772 unsigned int channels_offset = 0;
1773 struct dma_device *engine;
1774 struct rcar_dmac *dmac;
1775 struct resource *mem;
1779 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
1783 dmac->dev = &pdev->dev;
1784 platform_set_drvdata(pdev, dmac);
1785 dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40));
1787 ret = rcar_dmac_parse_of(&pdev->dev, dmac);
1792 * A still unconfirmed hardware bug prevents the IPMMU microTLB 0 to be
1793 * flushed correctly, resulting in memory corruption. DMAC 0 channel 0
1794 * is connected to microTLB 0 on currently supported platforms, so we
1795 * can't use it with the IPMMU. As the IOMMU API operates at the device
1796 * level we can't disable it selectively, so ignore channel 0 for now if
1797 * the device is part of an IOMMU group.
1799 if (pdev->dev.iommu_group) {
1801 channels_offset = 1;
1804 dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
1805 sizeof(*dmac->channels), GFP_KERNEL);
1806 if (!dmac->channels)
1809 /* Request resources. */
1810 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1811 dmac->iomem = devm_ioremap_resource(&pdev->dev, mem);
1812 if (IS_ERR(dmac->iomem))
1813 return PTR_ERR(dmac->iomem);
1815 /* Enable runtime PM and initialize the device. */
1816 pm_runtime_enable(&pdev->dev);
1817 ret = pm_runtime_get_sync(&pdev->dev);
1819 dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret);
1823 ret = rcar_dmac_init(dmac);
1824 pm_runtime_put(&pdev->dev);
1827 dev_err(&pdev->dev, "failed to reset device\n");
1831 /* Initialize engine */
1832 engine = &dmac->engine;
1834 dma_cap_set(DMA_MEMCPY, engine->cap_mask);
1835 dma_cap_set(DMA_SLAVE, engine->cap_mask);
1837 engine->dev = &pdev->dev;
1838 engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE);
1840 engine->src_addr_widths = widths;
1841 engine->dst_addr_widths = widths;
1842 engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1843 engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1845 engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources;
1846 engine->device_free_chan_resources = rcar_dmac_free_chan_resources;
1847 engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy;
1848 engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg;
1849 engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic;
1850 engine->device_config = rcar_dmac_device_config;
1851 engine->device_terminate_all = rcar_dmac_chan_terminate_all;
1852 engine->device_tx_status = rcar_dmac_tx_status;
1853 engine->device_issue_pending = rcar_dmac_issue_pending;
1854 engine->device_synchronize = rcar_dmac_device_synchronize;
1856 INIT_LIST_HEAD(&engine->channels);
1858 for (i = 0; i < dmac->n_channels; ++i) {
1859 ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i],
1860 i + channels_offset);
1865 /* Register the DMAC as a DMA provider for DT. */
1866 ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate,
1872 * Register the DMA engine device.
1874 * Default transfer size of 32 bytes requires 32-byte alignment.
1876 ret = dma_async_device_register(engine);
1883 of_dma_controller_free(pdev->dev.of_node);
1884 pm_runtime_disable(&pdev->dev);
1888 static int rcar_dmac_remove(struct platform_device *pdev)
1890 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1892 of_dma_controller_free(pdev->dev.of_node);
1893 dma_async_device_unregister(&dmac->engine);
1895 pm_runtime_disable(&pdev->dev);
1900 static void rcar_dmac_shutdown(struct platform_device *pdev)
1902 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1904 rcar_dmac_stop_all_chan(dmac);
1907 static const struct of_device_id rcar_dmac_of_ids[] = {
1908 { .compatible = "renesas,rcar-dmac", },
1911 MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids);
1913 static struct platform_driver rcar_dmac_driver = {
1915 .pm = &rcar_dmac_pm,
1916 .name = "rcar-dmac",
1917 .of_match_table = rcar_dmac_of_ids,
1919 .probe = rcar_dmac_probe,
1920 .remove = rcar_dmac_remove,
1921 .shutdown = rcar_dmac_shutdown,
1924 module_platform_driver(rcar_dmac_driver);
1926 MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver");
1927 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1928 MODULE_LICENSE("GPL v2");