3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
6 config EDAC_ATOMIC_SCRUB
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES && (EDAC=y)
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
61 APEI/GHES driver. By enabling this option, the error reports provided
62 by GHES are sent to userspace via the EDAC API.
64 When this option is enabled, it will disable the hardware-driven
65 mechanisms, if a GHES BIOS is detected, entering into the
66 "Firmware First" mode.
68 It should be noticed that keeping both GHES and a hardware-driven
69 error mechanism won't work well, as BIOS will race with OS, while
70 reading the error registers. So, if you want to not use "Firmware
71 first" GHES error mechanism, you should disable GHES either at
72 compilation time or by passing "ghes.disable=1" Kernel parameter
78 tristate "AMD64 (Opteron, Athlon64)"
79 depends on AMD_NB && EDAC_DECODE_MCE
81 Support for error detection and correction of DRAM ECC errors on
82 the AMD64 families (>= K8) of memory controllers.
84 config EDAC_AMD64_ERROR_INJECTION
85 bool "Sysfs HW Error injection facilities"
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
104 tristate "AMD 76x (760, 762, 768)"
105 depends on PCI && X86_32
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
112 depends on PCI && X86_32
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
119 depends on PCI && X86
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
124 config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
126 depends on PCI && X86_32
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
133 tristate "Intel 82875p (D82875P, E7210)"
134 depends on PCI && X86_32
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
140 tristate "Intel 82975x (D82975x)"
141 depends on PCI && X86
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
147 tristate "Intel 3000/3010"
148 depends on PCI && X86
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
154 tristate "Intel 3200"
155 depends on PCI && X86
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
161 tristate "Intel e312xx"
162 depends on PCI && X86
164 Support for error detection and correction on the Intel
165 E3-1200 based DRAM controllers.
169 depends on PCI && X86
171 Support for error detection and correction on the Intel
175 tristate "Intel 5400 (Seaburg) chipsets"
176 depends on PCI && X86
178 Support for error detection and correction the Intel
179 i5400 MCH chipset (Seaburg).
182 tristate "Intel i7 Core (Nehalem) processors"
183 depends on PCI && X86 && X86_MCE_INTEL
185 Support for error detection and correction the Intel
186 i7 Core (Nehalem) Integrated Memory Controller that exists on
187 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
188 and Xeon 55xx processors.
191 tristate "Intel 82860"
192 depends on PCI && X86_32
194 Support for error detection and correction on the Intel
198 tristate "Radisys 82600 embedded chipset"
199 depends on PCI && X86_32
201 Support for error detection and correction on the Radisys
202 82600 embedded chipset.
205 tristate "Intel Greencreek/Blackford chipset"
206 depends on X86 && PCI
208 Support for error detection and correction the Intel
209 Greekcreek/Blackford chipsets.
212 tristate "Intel San Clemente MCH"
213 depends on X86 && PCI
215 Support for error detection and correction the Intel
219 tristate "Intel Clarksboro MCH"
220 depends on X86 && PCI
222 Support for error detection and correction the Intel
223 Clarksboro MCH (Intel 7300 chipset).
226 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
227 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
229 Support for error detection and correction the Intel
230 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
233 tristate "Intel Skylake server Integrated MC"
234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
235 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
239 Support for error detection and correction the Intel
240 Skylake server Integrated Memory Controllers. If your
241 system has non-volatile DIMMs you should also manually
242 select CONFIG_ACPI_NFIT.
245 tristate "Intel 10nm server Integrated MC"
246 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
247 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
249 select ACPI_ADXL if ACPI
251 Support for error detection and correction the Intel
252 10nm server Integrated Memory Controllers. If your
253 system has non-volatile DIMMs you should also manually
254 select CONFIG_ACPI_NFIT.
257 tristate "Intel Pondicherry2"
258 depends on PCI && X86_64 && X86_MCE_INTEL
260 Support for error detection and correction on the Intel
261 Pondicherry2 Integrated Memory Controller. This SoC IP is
262 first used on the Apollo Lake platform and Denverton
263 micro-server but may appear on others in the future.
266 tristate "Freescale MPC83xx / MPC85xx"
269 Support for error detection and correction on the Freescale
270 MPC8349, MPC8560, MPC8540, MPC8548, T4240
272 config EDAC_LAYERSCAPE
273 tristate "Freescale Layerscape DDR"
274 depends on ARCH_LAYERSCAPE || SOC_LS1021A
276 Support for error detection and correction on Freescale memory
277 controllers on Layerscape SoCs.
280 tristate "Marvell MV64x60"
283 Support for error detection and correction on the Marvell
284 MV64360 and MV64460 chipsets.
287 tristate "PA Semi PWRficient"
288 depends on PPC_PASEMI && PCI
290 Support for error detection and correction on PA Semi
294 tristate "Cell Broadband Engine memory controller"
295 depends on PPC_CELL_COMMON
297 Support for error detection and correction on the
298 Cell Broadband Engine internal memory controller
299 on platform without a hypervisor
302 tristate "PPC4xx IBM DDR2 Memory Controller"
305 This enables support for EDAC on the ECC memory used
306 with the IBM DDR2 memory controller found in various
307 PowerPC 4xx embedded processors such as the 405EX[r],
308 440SP, 440SPe, 460EX, 460GT and 460SX.
311 tristate "AMD8131 HyperTransport PCI-X Tunnel"
312 depends on PCI && PPC_MAPLE
314 Support for error detection and correction on the
315 AMD8131 HyperTransport PCI-X Tunnel chip.
316 Note, add more Kconfig dependency if it's adopted
317 on some machine other than Maple.
320 tristate "AMD8111 HyperTransport I/O Hub"
321 depends on PCI && PPC_MAPLE
323 Support for error detection and correction on the
324 AMD8111 HyperTransport I/O Hub chip.
325 Note, add more Kconfig dependency if it's adopted
326 on some machine other than Maple.
329 tristate "IBM CPC925 Memory Controller (PPC970FX)"
332 Support for error detection and correction on the
333 IBM CPC925 Bridge and Memory Controller, which is
334 a companion chip to the PowerPC 970 family of
337 config EDAC_HIGHBANK_MC
338 tristate "Highbank Memory Controller"
339 depends on ARCH_HIGHBANK
341 Support for error detection and correction on the
342 Calxeda Highbank memory controller.
344 config EDAC_HIGHBANK_L2
345 tristate "Highbank L2 Cache"
346 depends on ARCH_HIGHBANK
348 Support for error detection and correction on the
349 Calxeda Highbank memory controller.
351 config EDAC_OCTEON_PC
352 tristate "Cavium Octeon Primary Caches"
353 depends on CPU_CAVIUM_OCTEON
355 Support for error detection and correction on the primary caches of
356 the cnMIPS cores of Cavium Octeon family SOCs.
358 config EDAC_OCTEON_L2C
359 tristate "Cavium Octeon Secondary Caches (L2C)"
360 depends on CAVIUM_OCTEON_SOC
362 Support for error detection and correction on the
363 Cavium Octeon family of SOCs.
365 config EDAC_OCTEON_LMC
366 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
367 depends on CAVIUM_OCTEON_SOC
369 Support for error detection and correction on the
370 Cavium Octeon family of SOCs.
372 config EDAC_OCTEON_PCI
373 tristate "Cavium Octeon PCI Controller"
374 depends on PCI && CAVIUM_OCTEON_SOC
376 Support for error detection and correction on the
377 Cavium Octeon family of SOCs.
380 tristate "Cavium ThunderX EDAC"
384 Support for error detection and correction on the
385 Cavium ThunderX memory controllers (LMC), Cache
386 Coherent Processor Interconnect (CCPI) and L2 cache
387 blocks (TAD, CBC, MCI).
390 bool "Altera SOCFPGA ECC"
391 depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
393 Support for error detection and correction on the
394 Altera SOCs. This must be selected for SDRAM ECC.
395 Note that the preloader must initialize the SDRAM
396 before loading the kernel.
398 config EDAC_ALTERA_L2C
399 bool "Altera L2 Cache ECC"
400 depends on EDAC_ALTERA=y && CACHE_L2X0
402 Support for error detection and correction on the
403 Altera L2 cache Memory for Altera SoCs. This option
406 config EDAC_ALTERA_OCRAM
407 bool "Altera On-Chip RAM ECC"
408 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
410 Support for error detection and correction on the
411 Altera On-Chip RAM Memory for Altera SoCs.
413 config EDAC_ALTERA_ETHERNET
414 bool "Altera Ethernet FIFO ECC"
415 depends on EDAC_ALTERA=y
417 Support for error detection and correction on the
418 Altera Ethernet FIFO Memory for Altera SoCs.
420 config EDAC_ALTERA_NAND
421 bool "Altera NAND FIFO ECC"
422 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
424 Support for error detection and correction on the
425 Altera NAND FIFO Memory for Altera SoCs.
427 config EDAC_ALTERA_DMA
428 bool "Altera DMA FIFO ECC"
429 depends on EDAC_ALTERA=y && PL330_DMA=y
431 Support for error detection and correction on the
432 Altera DMA FIFO Memory for Altera SoCs.
434 config EDAC_ALTERA_USB
435 bool "Altera USB FIFO ECC"
436 depends on EDAC_ALTERA=y && USB_DWC2
438 Support for error detection and correction on the
439 Altera USB FIFO Memory for Altera SoCs.
441 config EDAC_ALTERA_QSPI
442 bool "Altera QSPI FIFO ECC"
443 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
445 Support for error detection and correction on the
446 Altera QSPI FIFO Memory for Altera SoCs.
448 config EDAC_ALTERA_SDMMC
449 bool "Altera SDMMC FIFO ECC"
450 depends on EDAC_ALTERA=y && MMC_DW
452 Support for error detection and correction on the
453 Altera SDMMC FIFO Memory for Altera SoCs.
456 tristate "Synopsys DDR Memory Controller"
457 depends on ARCH_ZYNQ || ARCH_ZYNQMP
459 Support for error detection and correction on the Synopsys DDR
463 tristate "APM X-Gene SoC"
464 depends on (ARM64 || COMPILE_TEST)
466 Support for error detection and correction on the
467 APM X-Gene family of SOCs.
470 tristate "Texas Instruments DDR3 ECC Controller"
471 depends on ARCH_KEYSTONE || SOC_DRA7XX
473 Support for error detection and correction on the
477 tristate "QCOM EDAC Controller"
478 depends on ARCH_QCOM && QCOM_LLCC
480 Support for error detection and correction on the
481 Qualcomm Technologies, Inc. SoCs.
483 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
484 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
485 of Tag RAM and Data RAM.
487 For debugging issues having to do with stability and overall system
488 health, you should probably say 'Y' here.
491 tristate "Aspeed AST 2500 SoC"
492 depends on MACH_ASPEED_G5
494 Support for error detection and correction on the Aspeed AST 2500 SoC.
496 First, ECC must be configured in the bootloader. Then, this driver
497 will expose error counters via the EDAC kernel framework.