drivers/edac/altera_edac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
   4  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
   5  *  Copyright 2011-2012 Calxeda, Inc.
   6  */
   7
   8 #include <asm/cacheflush.h>
   9 #include <linux/ctype.h>
  10 #include <linux/delay.h>
  11 #include <linux/edac.h>
  12 #include <linux/genalloc.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip/chained_irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/notifier.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/types.h>
  24 #include <linux/uaccess.h>
  25
  26 #include "altera_edac.h"
  27 #include "edac_module.h"
  28
  29 #define EDAC_MOD_STR            "altera_edac"
  30 #define EDAC_DEVICE             "Altera"
  31
  32 #ifdef CONFIG_EDAC_ALTERA_SDRAM
  33 static const struct altr_sdram_prv_data c5_data = {
  34         .ecc_ctrl_offset    = CV_CTLCFG_OFST,
  35         .ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
  36         .ecc_stat_offset    = CV_DRAMSTS_OFST,
  37         .ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
  38         .ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
  39         .ecc_saddr_offset   = CV_ERRADDR_OFST,
  40         .ecc_daddr_offset   = CV_ERRADDR_OFST,
  41         .ecc_cecnt_offset   = CV_SBECOUNT_OFST,
  42         .ecc_uecnt_offset   = CV_DBECOUNT_OFST,
  43         .ecc_irq_en_offset  = CV_DRAMINTR_OFST,
  44         .ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
  45         .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  46         .ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  47         .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  48         .ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
  49         .ce_ue_trgr_offset  = CV_CTLCFG_OFST,
  50         .ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
  51         .ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
  52 };
  53
  54 static const struct altr_sdram_prv_data a10_data = {
  55         .ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
  56         .ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
  57         .ecc_stat_offset    = A10_INTSTAT_OFST,
  58         .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
  59         .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
  60         .ecc_saddr_offset   = A10_SERRADDR_OFST,
  61         .ecc_daddr_offset   = A10_DERRADDR_OFST,
  62         .ecc_irq_en_offset  = A10_ERRINTEN_OFST,
  63         .ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
  64         .ecc_irq_clr_offset = A10_INTSTAT_OFST,
  65         .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  66         .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  67         .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
  68         .ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
  69         .ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
  70         .ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
  71 };
  72
  73 /*********************** EDAC Memory Controller Functions ****************/
  74
  75 /* The SDRAM controller uses the EDAC Memory Controller framework.       */
  76
  77 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  78 {
  79         struct mem_ctl_info *mci = dev_id;
  80         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  81         const struct altr_sdram_prv_data *priv = drvdata->data;
  82         u32 status, err_count = 1, err_addr;
  83
  84         regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  85
  86         if (status & priv->ecc_stat_ue_mask) {
  87                 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  88                             &err_addr);
  89                 if (priv->ecc_uecnt_offset)
  90                         regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  91                                     &err_count);
  92                 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  93                       err_count, err_addr);
  94         }
  95         if (status & priv->ecc_stat_ce_mask) {
  96                 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
  97                             &err_addr);
  98                 if (priv->ecc_uecnt_offset)
  99                         regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
 100                                     &err_count);
 101                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 102                                      err_addr >> PAGE_SHIFT,
 103                                      err_addr & ~PAGE_MASK, 0,
 104                                      0, 0, -1, mci->ctl_name, "");
 105                 /* Clear IRQ to resume */
 106                 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
 107                              priv->ecc_irq_clr_mask);
 108
 109                 return IRQ_HANDLED;
 110         }
 111         return IRQ_NONE;
 112 }
 113
 114 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
 115                                             const char __user *data,
 116                                             size_t count, loff_t *ppos)
 117 {
 118         struct mem_ctl_info *mci = file->private_data;
 119         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
 120         const struct altr_sdram_prv_data *priv = drvdata->data;
 121         u32 *ptemp;
 122         dma_addr_t dma_handle;
 123         u32 reg, read_reg;
 124
 125         ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
 126         if (!ptemp) {
 127                 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 128                 edac_printk(KERN_ERR, EDAC_MC,
 129                             "Inject: Buffer Allocation error\n");
 130                 return -ENOMEM;
 131         }
 132
 133         regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 134                     &read_reg);
 135         read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
 136
 137         /* Error are injected by writing a word while the SBE or DBE
 138          * bit in the CTLCFG register is set. Reading the word will
 139          * trigger the SBE or DBE error and the corresponding IRQ.
 140          */
 141         if (count == 3) {
 142                 edac_printk(KERN_ALERT, EDAC_MC,
 143                             "Inject Double bit error\n");
 144                 local_irq_disable();
 145                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 146                              (read_reg | priv->ue_set_mask));
 147                 local_irq_enable();
 148         } else {
 149                 edac_printk(KERN_ALERT, EDAC_MC,
 150                             "Inject Single bit error\n");
 151                 local_irq_disable();
 152                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 153                              (read_reg | priv->ce_set_mask));
 154                 local_irq_enable();
 155         }
 156
 157         ptemp[0] = 0x5A5A5A5A;
 158         ptemp[1] = 0xA5A5A5A5;
 159
 160         /* Clear the error injection bits */
 161         regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
 162         /* Ensure it has been written out */
 163         wmb();
 164
 165         /*
 166          * To trigger the error, we need to read the data back
 167          * (the data was written with errors above).
 168          * The READ_ONCE macros and printk are used to prevent the
 169          * the compiler optimizing these reads out.
 170          */
 171         reg = READ_ONCE(ptemp[0]);
 172         read_reg = READ_ONCE(ptemp[1]);
 173         /* Force Read */
 174         rmb();
 175
 176         edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
 177                     reg, read_reg);
 178
 179         dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 180
 181         return count;
 182 }
 183
 184 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
 185         .open = simple_open,
 186         .write = altr_sdr_mc_err_inject_write,
 187         .llseek = generic_file_llseek,
 188 };
 189
 190 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 191 {
 192         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 193                 return;
 194
 195         if (!mci->debugfs)
 196                 return;
 197
 198         edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
 199                                  &altr_sdr_mc_debug_inject_fops);
 200 }
 201
 202 /* Get total memory size from Open Firmware DTB */
 203 static unsigned long get_total_mem(void)
 204 {
 205         struct device_node *np = NULL;
 206         struct resource res;
 207         int ret;
 208         unsigned long total_mem = 0;
 209
 210         for_each_node_by_type(np, "memory") {
 211                 ret = of_address_to_resource(np, 0, &res);
 212                 if (ret)
 213                         continue;
 214
 215                 total_mem += resource_size(&res);
 216         }
 217         edac_dbg(0, "total_mem 0x%lx\n", total_mem);
 218         return total_mem;
 219 }
 220
 221 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
 222         { .compatible = "altr,sdram-edac", .data = &c5_data},
 223         { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
 224         { .compatible = "altr,sdram-edac-s10", .data = &a10_data},
 225         {},
 226 };
 227 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 228
 229 static int a10_init(struct regmap *mc_vbase)
 230 {
 231         if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
 232                                A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
 233                 edac_printk(KERN_ERR, EDAC_MC,
 234                             "Error setting SB IRQ mode\n");
 235                 return -ENODEV;
 236         }
 237
 238         if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
 239                 edac_printk(KERN_ERR, EDAC_MC,
 240                             "Error setting trigger count\n");
 241                 return -ENODEV;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
 248 {
 249         void __iomem  *sm_base;
 250         int  ret = 0;
 251
 252         if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
 253                                 dev_name(&pdev->dev))) {
 254                 edac_printk(KERN_ERR, EDAC_MC,
 255                             "Unable to request mem region\n");
 256                 return -EBUSY;
 257         }
 258
 259         sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 260         if (!sm_base) {
 261                 edac_printk(KERN_ERR, EDAC_MC,
 262                             "Unable to ioremap device\n");
 263
 264                 ret = -ENOMEM;
 265                 goto release;
 266         }
 267
 268         iowrite32(mask, sm_base);
 269
 270         iounmap(sm_base);
 271
 272 release:
 273         release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 274
 275         return ret;
 276 }
 277
 278 static int socfpga_is_a10(void);
 279 static int altr_sdram_probe(struct platform_device *pdev)
 280 {
 281         const struct of_device_id *id;
 282         struct edac_mc_layer layers[2];
 283         struct mem_ctl_info *mci;
 284         struct altr_sdram_mc_data *drvdata;
 285         const struct altr_sdram_prv_data *priv;
 286         struct regmap *mc_vbase;
 287         struct dimm_info *dimm;
 288         u32 read_reg;
 289         int irq, irq2, res = 0;
 290         unsigned long mem_size, irqflags = 0;
 291
 292         id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
 293         if (!id)
 294                 return -ENODEV;
 295
 296         /* Grab the register range from the sdr controller in device tree */
 297         mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 298                                                    "altr,sdr-syscon");
 299         if (IS_ERR(mc_vbase)) {
 300                 edac_printk(KERN_ERR, EDAC_MC,
 301                             "regmap for altr,sdr-syscon lookup failed.\n");
 302                 return -ENODEV;
 303         }
 304
 305         /* Check specific dependencies for the module */
 306         priv = of_match_node(altr_sdram_ctrl_of_match,
 307                              pdev->dev.of_node)->data;
 308
 309         /* Validate the SDRAM controller has ECC enabled */
 310         if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
 311             ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
 312                 edac_printk(KERN_ERR, EDAC_MC,
 313                             "No ECC/ECC disabled [0x%08X]\n", read_reg);
 314                 return -ENODEV;
 315         }
 316
 317         /* Grab memory size from device tree. */
 318         mem_size = get_total_mem();
 319         if (!mem_size) {
 320                 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
 321                 return -ENODEV;
 322         }
 323
 324         /* Ensure the SDRAM Interrupt is disabled */
 325         if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
 326                                priv->ecc_irq_en_mask, 0)) {
 327                 edac_printk(KERN_ERR, EDAC_MC,
 328                             "Error disabling SDRAM ECC IRQ\n");
 329                 return -ENODEV;
 330         }
 331
 332         /* Toggle to clear the SDRAM Error count */
 333         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 334                                priv->ecc_cnt_rst_mask,
 335                                priv->ecc_cnt_rst_mask)) {
 336                 edac_printk(KERN_ERR, EDAC_MC,
 337                             "Error clearing SDRAM ECC count\n");
 338                 return -ENODEV;
 339         }
 340
 341         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 342                                priv->ecc_cnt_rst_mask, 0)) {
 343                 edac_printk(KERN_ERR, EDAC_MC,
 344                             "Error clearing SDRAM ECC count\n");
 345                 return -ENODEV;
 346         }
 347
 348         irq = platform_get_irq(pdev, 0);
 349         if (irq < 0) {
 350                 edac_printk(KERN_ERR, EDAC_MC,
 351                             "No irq %d in DT\n", irq);
 352                 return -ENODEV;
 353         }
 354
 355         /* Arria10 has a 2nd IRQ */
 356         irq2 = platform_get_irq(pdev, 1);
 357
 358         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 359         layers[0].size = 1;
 360         layers[0].is_virt_csrow = true;
 361         layers[1].type = EDAC_MC_LAYER_CHANNEL;
 362         layers[1].size = 1;
 363         layers[1].is_virt_csrow = false;
 364         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 365                             sizeof(struct altr_sdram_mc_data));
 366         if (!mci)
 367                 return -ENOMEM;
 368
 369         mci->pdev = &pdev->dev;
 370         drvdata = mci->pvt_info;
 371         drvdata->mc_vbase = mc_vbase;
 372         drvdata->data = priv;
 373         platform_set_drvdata(pdev, mci);
 374
 375         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 376                 edac_printk(KERN_ERR, EDAC_MC,
 377                             "Unable to get managed device resource\n");
 378                 res = -ENOMEM;
 379                 goto free;
 380         }
 381
 382         mci->mtype_cap = MEM_FLAG_DDR3;
 383         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 384         mci->edac_cap = EDAC_FLAG_SECDED;
 385         mci->mod_name = EDAC_MOD_STR;
 386         mci->ctl_name = dev_name(&pdev->dev);
 387         mci->scrub_mode = SCRUB_SW_SRC;
 388         mci->dev_name = dev_name(&pdev->dev);
 389
 390         dimm = *mci->dimms;
 391         dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
 392         dimm->grain = 8;
 393         dimm->dtype = DEV_X8;
 394         dimm->mtype = MEM_DDR3;
 395         dimm->edac_mode = EDAC_SECDED;
 396
 397         res = edac_mc_add_mc(mci);
 398         if (res < 0)
 399                 goto err;
 400
 401         /* Only the Arria10 has separate IRQs */
 402         if (socfpga_is_a10()) {
 403                 /* Arria10 specific initialization */
 404                 res = a10_init(mc_vbase);
 405                 if (res < 0)
 406                         goto err2;
 407
 408                 res = devm_request_irq(&pdev->dev, irq2,
 409                                        altr_sdram_mc_err_handler,
 410                                        IRQF_SHARED, dev_name(&pdev->dev), mci);
 411                 if (res < 0) {
 412                         edac_mc_printk(mci, KERN_ERR,
 413                                        "Unable to request irq %d\n", irq2);
 414                         res = -ENODEV;
 415                         goto err2;
 416                 }
 417
 418                 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
 419                 if (res < 0)
 420                         goto err2;
 421
 422                 irqflags = IRQF_SHARED;
 423         }
 424
 425         res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
 426                                irqflags, dev_name(&pdev->dev), mci);
 427         if (res < 0) {
 428                 edac_mc_printk(mci, KERN_ERR,
 429                                "Unable to request irq %d\n", irq);
 430                 res = -ENODEV;
 431                 goto err2;
 432         }
 433
 434         /* Infrastructure ready - enable the IRQ */
 435         if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
 436                                priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
 437                 edac_mc_printk(mci, KERN_ERR,
 438                                "Error enabling SDRAM ECC IRQ\n");
 439                 res = -ENODEV;
 440                 goto err2;
 441         }
 442
 443         altr_sdr_mc_create_debugfs_nodes(mci);
 444
 445         devres_close_group(&pdev->dev, NULL);
 446
 447         return 0;
 448
 449 err2:
 450         edac_mc_del_mc(&pdev->dev);
 451 err:
 452         devres_release_group(&pdev->dev, NULL);
 453 free:
 454         edac_mc_free(mci);
 455         edac_printk(KERN_ERR, EDAC_MC,
 456                     "EDAC Probe Failed; Error %d\n", res);
 457
 458         return res;
 459 }
 460
 461 static int altr_sdram_remove(struct platform_device *pdev)
 462 {
 463         struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 464
 465         edac_mc_del_mc(&pdev->dev);
 466         edac_mc_free(mci);
 467         platform_set_drvdata(pdev, NULL);
 468
 469         return 0;
 470 }
 471
 472 /*
 473  * If you want to suspend, need to disable EDAC by removing it
 474  * from the device tree or defconfig.
 475  */
 476 #ifdef CONFIG_PM
 477 static int altr_sdram_prepare(struct device *dev)
 478 {
 479         pr_err("Suspend not allowed when EDAC is enabled.\n");
 480
 481         return -EPERM;
 482 }
 483
 484 static const struct dev_pm_ops altr_sdram_pm_ops = {
 485         .prepare = altr_sdram_prepare,
 486 };
 487 #endif
 488
 489 static struct platform_driver altr_sdram_edac_driver = {
 490         .probe = altr_sdram_probe,
 491         .remove = altr_sdram_remove,
 492         .driver = {
 493                 .name = "altr_sdram_edac",
 494 #ifdef CONFIG_PM
 495                 .pm = &altr_sdram_pm_ops,
 496 #endif
 497                 .of_match_table = altr_sdram_ctrl_of_match,
 498         },
 499 };
 500
 501 module_platform_driver(altr_sdram_edac_driver);
 502
 503 #endif  /* CONFIG_EDAC_ALTERA_SDRAM */
 504
 505 /**************** Stratix 10 EDAC Memory Controller Functions ************/
 506
 507 /**
 508  * s10_protected_reg_write
 509  * Write to a protected SMC register.
 510  * @context: Not used.
 511  * @reg: Address of register
 512  * @value: Value to write
 513  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 514  *         INTEL_SIP_SMC_REG_ERROR on error
 515  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 516  */
 517 static int s10_protected_reg_write(void *context, unsigned int reg,
 518                                    unsigned int val)
 519 {
 520         struct arm_smccc_res result;
 521         unsigned long offset = (unsigned long)context;
 522
 523         arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
 524                       0, 0, 0, &result);
 525
 526         return (int)result.a0;
 527 }
 528
 529 /**
 530  * s10_protected_reg_read
 531  * Read the status of a protected SMC register
 532  * @context: Not used.
 533  * @reg: Address of register
 534  * @value: Value read.
 535  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 536  *         INTEL_SIP_SMC_REG_ERROR on error
 537  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 538  */
 539 static int s10_protected_reg_read(void *context, unsigned int reg,
 540                                   unsigned int *val)
 541 {
 542         struct arm_smccc_res result;
 543         unsigned long offset = (unsigned long)context;
 544
 545         arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
 546                       0, 0, 0, &result);
 547
 548         *val = (unsigned int)result.a1;
 549
 550         return (int)result.a0;
 551 }
 552
 553 static const struct regmap_config s10_sdram_regmap_cfg = {
 554         .name = "s10_ddr",
 555         .reg_bits = 32,
 556         .reg_stride = 4,
 557         .val_bits = 32,
 558         .max_register = 0xffd12228,
 559         .reg_read = s10_protected_reg_read,
 560         .reg_write = s10_protected_reg_write,
 561         .use_single_read = true,
 562         .use_single_write = true,
 563 };
 564
 565 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
 566
 567 /************************* EDAC Parent Probe *************************/
 568
 569 static const struct of_device_id altr_edac_device_of_match[];
 570
 571 static const struct of_device_id altr_edac_of_match[] = {
 572         { .compatible = "altr,socfpga-ecc-manager" },
 573         {},
 574 };
 575 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
 576
 577 static int altr_edac_probe(struct platform_device *pdev)
 578 {
 579         of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
 580                              NULL, &pdev->dev);
 581         return 0;
 582 }
 583
 584 static struct platform_driver altr_edac_driver = {
 585         .probe =  altr_edac_probe,
 586         .driver = {
 587                 .name = "socfpga_ecc_manager",
 588                 .of_match_table = altr_edac_of_match,
 589         },
 590 };
 591 module_platform_driver(altr_edac_driver);
 592
 593 /************************* EDAC Device Functions *************************/
 594
 595 /*
 596  * EDAC Device Functions (shared between various IPs).
 597  * The discrete memories use the EDAC Device framework. The probe
 598  * and error handling functions are very similar between memories
 599  * so they are shared. The memory allocation and freeing for EDAC
 600  * trigger testing are different for each memory.
 601  */
 602
 603 static const struct edac_device_prv_data ocramecc_data;
 604 static const struct edac_device_prv_data l2ecc_data;
 605 static const struct edac_device_prv_data a10_ocramecc_data;
 606 static const struct edac_device_prv_data a10_l2ecc_data;
 607
 608 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 609 {
 610         irqreturn_t ret_value = IRQ_NONE;
 611         struct edac_device_ctl_info *dci = dev_id;
 612         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 613         const struct edac_device_prv_data *priv = drvdata->data;
 614
 615         if (irq == drvdata->sb_irq) {
 616                 if (priv->ce_clear_mask)
 617                         writel(priv->ce_clear_mask, drvdata->base);
 618                 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
 619                 ret_value = IRQ_HANDLED;
 620         } else if (irq == drvdata->db_irq) {
 621                 if (priv->ue_clear_mask)
 622                         writel(priv->ue_clear_mask, drvdata->base);
 623                 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
 624                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 625                 ret_value = IRQ_HANDLED;
 626         } else {
 627                 WARN_ON(1);
 628         }
 629
 630         return ret_value;
 631 }
 632
 633 static ssize_t altr_edac_device_trig(struct file *file,
 634                                      const char __user *user_buf,
 635                                      size_t count, loff_t *ppos)
 636
 637 {
 638         u32 *ptemp, i, error_mask;
 639         int result = 0;
 640         u8 trig_type;
 641         unsigned long flags;
 642         struct edac_device_ctl_info *edac_dci = file->private_data;
 643         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 644         const struct edac_device_prv_data *priv = drvdata->data;
 645         void *generic_ptr = edac_dci->dev;
 646
 647         if (!user_buf || get_user(trig_type, user_buf))
 648                 return -EFAULT;
 649
 650         if (!priv->alloc_mem)
 651                 return -ENOMEM;
 652
 653         /*
 654          * Note that generic_ptr is initialized to the device * but in
 655          * some alloc_functions, this is overridden and returns data.
 656          */
 657         ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
 658         if (!ptemp) {
 659                 edac_printk(KERN_ERR, EDAC_DEVICE,
 660                             "Inject: Buffer Allocation error\n");
 661                 return -ENOMEM;
 662         }
 663
 664         if (trig_type == ALTR_UE_TRIGGER_CHAR)
 665                 error_mask = priv->ue_set_mask;
 666         else
 667                 error_mask = priv->ce_set_mask;
 668
 669         edac_printk(KERN_ALERT, EDAC_DEVICE,
 670                     "Trigger Error Mask (0x%X)\n", error_mask);
 671
 672         local_irq_save(flags);
 673         /* write ECC corrupted data out. */
 674         for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
 675                 /* Read data so we're in the correct state */
 676                 rmb();
 677                 if (READ_ONCE(ptemp[i]))
 678                         result = -1;
 679                 /* Toggle Error bit (it is latched), leave ECC enabled */
 680                 writel(error_mask, (drvdata->base + priv->set_err_ofst));
 681                 writel(priv->ecc_enable_mask, (drvdata->base +
 682                                                priv->set_err_ofst));
 683                 ptemp[i] = i;
 684         }
 685         /* Ensure it has been written out */
 686         wmb();
 687         local_irq_restore(flags);
 688
 689         if (result)
 690                 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
 691
 692         /* Read out written data. ECC error caused here */
 693         for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
 694                 if (READ_ONCE(ptemp[i]) != i)
 695                         edac_printk(KERN_ERR, EDAC_DEVICE,
 696                                     "Read doesn't match written data\n");
 697
 698         if (priv->free_mem)
 699                 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
 700
 701         return count;
 702 }
 703
 704 static const struct file_operations altr_edac_device_inject_fops = {
 705         .open = simple_open,
 706         .write = altr_edac_device_trig,
 707         .llseek = generic_file_llseek,
 708 };
 709
 710 static ssize_t altr_edac_a10_device_trig(struct file *file,
 711                                          const char __user *user_buf,
 712                                          size_t count, loff_t *ppos);
 713
 714 static const struct file_operations altr_edac_a10_device_inject_fops = {
 715         .open = simple_open,
 716         .write = altr_edac_a10_device_trig,
 717         .llseek = generic_file_llseek,
 718 };
 719
 720 static ssize_t altr_edac_a10_device_trig2(struct file *file,
 721                                           const char __user *user_buf,
 722                                           size_t count, loff_t *ppos);
 723
 724 static const struct file_operations altr_edac_a10_device_inject2_fops = {
 725         .open = simple_open,
 726         .write = altr_edac_a10_device_trig2,
 727         .llseek = generic_file_llseek,
 728 };
 729
 730 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
 731                                       const struct edac_device_prv_data *priv)
 732 {
 733         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 734
 735         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 736                 return;
 737
 738         drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
 739         if (!drvdata->debugfs_dir)
 740                 return;
 741
 742         if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
 743                                       drvdata->debugfs_dir, edac_dci,
 744                                       priv->inject_fops))
 745                 debugfs_remove_recursive(drvdata->debugfs_dir);
 746 }
 747
 748 static const struct of_device_id altr_edac_device_of_match[] = {
 749 #ifdef CONFIG_EDAC_ALTERA_L2C
 750         { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
 751 #endif
 752 #ifdef CONFIG_EDAC_ALTERA_OCRAM
 753         { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
 754 #endif
 755         {},
 756 };
 757 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
 758
 759 /*
 760  * altr_edac_device_probe()
 761  *      This is a generic EDAC device driver that will support
 762  *      various Altera memory devices such as the L2 cache ECC and
 763  *      OCRAM ECC as well as the memories for other peripherals.
 764  *      Module specific initialization is done by passing the
 765  *      function index in the device tree.
 766  */
 767 static int altr_edac_device_probe(struct platform_device *pdev)
 768 {
 769         struct edac_device_ctl_info *dci;
 770         struct altr_edac_device_dev *drvdata;
 771         struct resource *r;
 772         int res = 0;
 773         struct device_node *np = pdev->dev.of_node;
 774         char *ecc_name = (char *)np->name;
 775         static int dev_instance;
 776
 777         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 778                 edac_printk(KERN_ERR, EDAC_DEVICE,
 779                             "Unable to open devm\n");
 780                 return -ENOMEM;
 781         }
 782
 783         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 784         if (!r) {
 785                 edac_printk(KERN_ERR, EDAC_DEVICE,
 786                             "Unable to get mem resource\n");
 787                 res = -ENODEV;
 788                 goto fail;
 789         }
 790
 791         if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 792                                      dev_name(&pdev->dev))) {
 793                 edac_printk(KERN_ERR, EDAC_DEVICE,
 794                             "%s:Error requesting mem region\n", ecc_name);
 795                 res = -EBUSY;
 796                 goto fail;
 797         }
 798
 799         dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
 800                                          1, ecc_name, 1, 0, NULL, 0,
 801                                          dev_instance++);
 802
 803         if (!dci) {
 804                 edac_printk(KERN_ERR, EDAC_DEVICE,
 805                             "%s: Unable to allocate EDAC device\n", ecc_name);
 806                 res = -ENOMEM;
 807                 goto fail;
 808         }
 809
 810         drvdata = dci->pvt_info;
 811         dci->dev = &pdev->dev;
 812         platform_set_drvdata(pdev, dci);
 813         drvdata->edac_dev_name = ecc_name;
 814
 815         drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 816         if (!drvdata->base) {
 817                 res = -ENOMEM;
 818                 goto fail1;
 819         }
 820
 821         /* Get driver specific data for this EDAC device */
 822         drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
 823
 824         /* Check specific dependencies for the module */
 825         if (drvdata->data->setup) {
 826                 res = drvdata->data->setup(drvdata);
 827                 if (res)
 828                         goto fail1;
 829         }
 830
 831         drvdata->sb_irq = platform_get_irq(pdev, 0);
 832         res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
 833                                altr_edac_device_handler,
 834                                0, dev_name(&pdev->dev), dci);
 835         if (res)
 836                 goto fail1;
 837
 838         drvdata->db_irq = platform_get_irq(pdev, 1);
 839         res = devm_request_irq(&pdev->dev, drvdata->db_irq,
 840                                altr_edac_device_handler,
 841                                0, dev_name(&pdev->dev), dci);
 842         if (res)
 843                 goto fail1;
 844
 845         dci->mod_name = "Altera ECC Manager";
 846         dci->dev_name = drvdata->edac_dev_name;
 847
 848         res = edac_device_add_device(dci);
 849         if (res)
 850                 goto fail1;
 851
 852         altr_create_edacdev_dbgfs(dci, drvdata->data);
 853
 854         devres_close_group(&pdev->dev, NULL);
 855
 856         return 0;
 857
 858 fail1:
 859         edac_device_free_ctl_info(dci);
 860 fail:
 861         devres_release_group(&pdev->dev, NULL);
 862         edac_printk(KERN_ERR, EDAC_DEVICE,
 863                     "%s:Error setting up EDAC device: %d\n", ecc_name, res);
 864
 865         return res;
 866 }
 867
 868 static int altr_edac_device_remove(struct platform_device *pdev)
 869 {
 870         struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
 871         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 872
 873         debugfs_remove_recursive(drvdata->debugfs_dir);
 874         edac_device_del_device(&pdev->dev);
 875         edac_device_free_ctl_info(dci);
 876
 877         return 0;
 878 }
 879
 880 static struct platform_driver altr_edac_device_driver = {
 881         .probe =  altr_edac_device_probe,
 882         .remove = altr_edac_device_remove,
 883         .driver = {
 884                 .name = "altr_edac_device",
 885                 .of_match_table = altr_edac_device_of_match,
 886         },
 887 };
 888 module_platform_driver(altr_edac_device_driver);
 889
 890 /******************* Arria10 Device ECC Shared Functions *****************/
 891
 892 /*
 893  *  Test for memory's ECC dependencies upon entry because platform specific
 894  *  startup should have initialized the memory and enabled the ECC.
 895  *  Can't turn on ECC here because accessing un-initialized memory will
 896  *  cause CE/UE errors possibly causing an ABORT.
 897  */
 898 static int __maybe_unused
 899 altr_check_ecc_deps(struct altr_edac_device_dev *device)
 900 {
 901         void __iomem  *base = device->base;
 902         const struct edac_device_prv_data *prv = device->data;
 903
 904         if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
 905                 return 0;
 906
 907         edac_printk(KERN_ERR, EDAC_DEVICE,
 908                     "%s: No ECC present or ECC disabled.\n",
 909                     device->edac_dev_name);
 910         return -ENODEV;
 911 }
 912
 913 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
 914 {
 915         struct altr_edac_device_dev *dci = dev_id;
 916         void __iomem  *base = dci->base;
 917
 918         if (irq == dci->sb_irq) {
 919                 writel(ALTR_A10_ECC_SERRPENA,
 920                        base + ALTR_A10_ECC_INTSTAT_OFST);
 921                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
 922
 923                 return IRQ_HANDLED;
 924         } else if (irq == dci->db_irq) {
 925                 writel(ALTR_A10_ECC_DERRPENA,
 926                        base + ALTR_A10_ECC_INTSTAT_OFST);
 927                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
 928                 if (dci->data->panic)
 929                         panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 930
 931                 return IRQ_HANDLED;
 932         }
 933
 934         WARN_ON(1);
 935
 936         return IRQ_NONE;
 937 }
 938
 939 /******************* Arria10 Memory Buffer Functions *********************/
 940
 941 static inline int a10_get_irq_mask(struct device_node *np)
 942 {
 943         int irq;
 944         const u32 *handle = of_get_property(np, "interrupts", NULL);
 945
 946         if (!handle)
 947                 return -ENODEV;
 948         irq = be32_to_cpup(handle);
 949         return irq;
 950 }
 951
 952 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
 953 {
 954         u32 value = readl(ioaddr);
 955
 956         value |= bit_mask;
 957         writel(value, ioaddr);
 958 }
 959
 960 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
 961 {
 962         u32 value = readl(ioaddr);
 963
 964         value &= ~bit_mask;
 965         writel(value, ioaddr);
 966 }
 967
 968 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
 969 {
 970         u32 value = readl(ioaddr);
 971
 972         return (value & bit_mask) ? 1 : 0;
 973 }
 974
 975 /*
 976  * This function uses the memory initialization block in the Arria10 ECC
 977  * controller to initialize/clear the entire memory data and ECC data.
 978  */
 979 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
 980 {
 981         int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
 982         u32 init_mask, stat_mask, clear_mask;
 983         int ret = 0;
 984
 985         if (port) {
 986                 init_mask = ALTR_A10_ECC_INITB;
 987                 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
 988                 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
 989         } else {
 990                 init_mask = ALTR_A10_ECC_INITA;
 991                 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
 992                 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
 993         }
 994
 995         ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
 996         while (limit--) {
 997                 if (ecc_test_bits(stat_mask,
 998                                   (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
 999                         break;
1000                 udelay(1);
1001         }
1002         if (limit < 0)
1003                 ret = -EBUSY;
1004
1005         /* Clear any pending ECC interrupts */
1006         writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1007
1008         return ret;
1009 }
1010
1011 static int socfpga_is_a10(void)
1012 {
1013         return of_machine_is_compatible("altr,socfpga-arria10");
1014 }
1015
1016 static int socfpga_is_s10(void)
1017 {
1018         return of_machine_is_compatible("altr,socfpga-stratix10");
1019 }
1020
1021 static __init int __maybe_unused
1022 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1023                         u32 ecc_ctrl_en_mask, bool dual_port)
1024 {
1025         int ret = 0;
1026         void __iomem *ecc_block_base;
1027         struct regmap *ecc_mgr_map;
1028         char *ecc_name;
1029         struct device_node *np_eccmgr;
1030
1031         ecc_name = (char *)np->name;
1032
1033         /* Get the ECC Manager - parent of the device EDACs */
1034         np_eccmgr = of_get_parent(np);
1035
1036         if (socfpga_is_a10()) {
1037                 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1038                                                               "altr,sysmgr-syscon");
1039         } else {
1040                 struct device_node *sysmgr_np;
1041                 struct resource res;
1042                 uintptr_t base;
1043
1044                 sysmgr_np = of_parse_phandle(np_eccmgr,
1045                                              "altr,sysmgr-syscon", 0);
1046                 if (!sysmgr_np) {
1047                         edac_printk(KERN_ERR, EDAC_DEVICE,
1048                                     "Unable to find altr,sysmgr-syscon\n");
1049                         return -ENODEV;
1050                 }
1051
1052                 if (of_address_to_resource(sysmgr_np, 0, &res)) {
1053                         of_node_put(sysmgr_np);
1054                         return -ENOMEM;
1055                 }
1056
1057                 /* Need physical address for SMCC call */
1058                 base = res.start;
1059
1060                 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
1061                                           &s10_sdram_regmap_cfg);
1062                 of_node_put(sysmgr_np);
1063         }
1064         of_node_put(np_eccmgr);
1065         if (IS_ERR(ecc_mgr_map)) {
1066                 edac_printk(KERN_ERR, EDAC_DEVICE,
1067                             "Unable to get syscon altr,sysmgr-syscon\n");
1068                 return -ENODEV;
1069         }
1070
1071         /* Map the ECC Block */
1072         ecc_block_base = of_iomap(np, 0);
1073         if (!ecc_block_base) {
1074                 edac_printk(KERN_ERR, EDAC_DEVICE,
1075                             "Unable to map %s ECC block\n", ecc_name);
1076                 return -ENODEV;
1077         }
1078
1079         /* Disable ECC */
1080         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1081         writel(ALTR_A10_ECC_SERRINTEN,
1082                (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1083         ecc_clear_bits(ecc_ctrl_en_mask,
1084                        (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1085         /* Ensure all writes complete */
1086         wmb();
1087         /* Use HW initialization block to initialize memory for ECC */
1088         ret = altr_init_memory_port(ecc_block_base, 0);
1089         if (ret) {
1090                 edac_printk(KERN_ERR, EDAC_DEVICE,
1091                             "ECC: cannot init %s PORTA memory\n", ecc_name);
1092                 goto out;
1093         }
1094
1095         if (dual_port) {
1096                 ret = altr_init_memory_port(ecc_block_base, 1);
1097                 if (ret) {
1098                         edac_printk(KERN_ERR, EDAC_DEVICE,
1099                                     "ECC: cannot init %s PORTB memory\n",
1100                                     ecc_name);
1101                         goto out;
1102                 }
1103         }
1104
1105         /* Interrupt mode set to every SBERR */
1106         regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1107                      ALTR_A10_ECC_INTMODE);
1108         /* Enable ECC */
1109         ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1110                                         ALTR_A10_ECC_CTRL_OFST));
1111         writel(ALTR_A10_ECC_SERRINTEN,
1112                (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1113         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1114         /* Ensure all writes complete */
1115         wmb();
1116 out:
1117         iounmap(ecc_block_base);
1118         return ret;
1119 }
1120
1121 static int validate_parent_available(struct device_node *np);
1122 static const struct of_device_id altr_edac_a10_device_of_match[];
1123 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1124 {
1125         int irq;
1126         struct device_node *child, *np;
1127
1128         if (!socfpga_is_a10() && !socfpga_is_s10())
1129                 return -ENODEV;
1130
1131         np = of_find_compatible_node(NULL, NULL,
1132                                      "altr,socfpga-a10-ecc-manager");
1133         if (!np) {
1134                 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1135                 return -ENODEV;
1136         }
1137
1138         for_each_child_of_node(np, child) {
1139                 const struct of_device_id *pdev_id;
1140                 const struct edac_device_prv_data *prv;
1141
1142                 if (!of_device_is_available(child))
1143                         continue;
1144                 if (!of_device_is_compatible(child, compat))
1145                         continue;
1146
1147                 if (validate_parent_available(child))
1148                         continue;
1149
1150                 irq = a10_get_irq_mask(child);
1151                 if (irq < 0)
1152                         continue;
1153
1154                 /* Get matching node and check for valid result */
1155                 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1156                 if (IS_ERR_OR_NULL(pdev_id))
1157                         continue;
1158
1159                 /* Validate private data pointer before dereferencing */
1160                 prv = pdev_id->data;
1161                 if (!prv)
1162                         continue;
1163
1164                 altr_init_a10_ecc_block(child, BIT(irq),
1165                                         prv->ecc_enable_mask, 0);
1166         }
1167
1168         of_node_put(np);
1169         return 0;
1170 }
1171
1172 /*********************** OCRAM EDAC Device Functions *********************/
1173
1174 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1175
1176 static void *ocram_alloc_mem(size_t size, void **other)
1177 {
1178         struct device_node *np;
1179         struct gen_pool *gp;
1180         void *sram_addr;
1181
1182         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1183         if (!np)
1184                 return NULL;
1185
1186         gp = of_gen_pool_get(np, "iram", 0);
1187         of_node_put(np);
1188         if (!gp)
1189                 return NULL;
1190
1191         sram_addr = (void *)gen_pool_alloc(gp, size);
1192         if (!sram_addr)
1193                 return NULL;
1194
1195         memset(sram_addr, 0, size);
1196         /* Ensure data is written out */
1197         wmb();
1198
1199         /* Remember this handle for freeing  later */
1200         *other = gp;
1201
1202         return sram_addr;
1203 }
1204
1205 static void ocram_free_mem(void *p, size_t size, void *other)
1206 {
1207         gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1208 }
1209
1210 static const struct edac_device_prv_data ocramecc_data = {
1211         .setup = altr_check_ecc_deps,
1212         .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1213         .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1214         .alloc_mem = ocram_alloc_mem,
1215         .free_mem = ocram_free_mem,
1216         .ecc_enable_mask = ALTR_OCR_ECC_EN,
1217         .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1218         .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1219         .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1220         .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1221         .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1222         .inject_fops = &altr_edac_device_inject_fops,
1223 };
1224
1225 static const struct edac_device_prv_data a10_ocramecc_data = {
1226         .setup = altr_check_ecc_deps,
1227         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1228         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1229         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1230         .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1231         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1232         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1233         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1234         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1235         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1236         .inject_fops = &altr_edac_a10_device_inject_fops,
1237         /*
1238          * OCRAM panic on uncorrectable error because sleep/resume
1239          * functions and FPGA contents are stored in OCRAM. Prefer
1240          * a kernel panic over executing/loading corrupted data.
1241          */
1242         .panic = true,
1243 };
1244
1245 #endif  /* CONFIG_EDAC_ALTERA_OCRAM */
1246
1247 /********************* L2 Cache EDAC Device Functions ********************/
1248
1249 #ifdef CONFIG_EDAC_ALTERA_L2C
1250
1251 static void *l2_alloc_mem(size_t size, void **other)
1252 {
1253         struct device *dev = *other;
1254         void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1255
1256         if (!ptemp)
1257                 return NULL;
1258
1259         /* Make sure everything is written out */
1260         wmb();
1261
1262         /*
1263          * Clean all cache levels up to LoC (includes L2)
1264          * This ensures the corrupted data is written into
1265          * L2 cache for readback test (which causes ECC error).
1266          */
1267         flush_cache_all();
1268
1269         return ptemp;
1270 }
1271
1272 static void l2_free_mem(void *p, size_t size, void *other)
1273 {
1274         struct device *dev = other;
1275
1276         if (dev && p)
1277                 devm_kfree(dev, p);
1278 }
1279
1280 /*
1281  * altr_l2_check_deps()
1282  *      Test for L2 cache ECC dependencies upon entry because
1283  *      platform specific startup should have initialized the L2
1284  *      memory and enabled the ECC.
1285  *      Bail if ECC is not enabled.
1286  *      Note that L2 Cache Enable is forced at build time.
1287  */
1288 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1289 {
1290         void __iomem *base = device->base;
1291         const struct edac_device_prv_data *prv = device->data;
1292
1293         if ((readl(base) & prv->ecc_enable_mask) ==
1294              prv->ecc_enable_mask)
1295                 return 0;
1296
1297         edac_printk(KERN_ERR, EDAC_DEVICE,
1298                     "L2: No ECC present, or ECC disabled\n");
1299         return -ENODEV;
1300 }
1301
1302 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1303 {
1304         struct altr_edac_device_dev *dci = dev_id;
1305
1306         if (irq == dci->sb_irq) {
1307                 regmap_write(dci->edac->ecc_mgr_map,
1308                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1309                              A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1310                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1311
1312                 return IRQ_HANDLED;
1313         } else if (irq == dci->db_irq) {
1314                 regmap_write(dci->edac->ecc_mgr_map,
1315                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1316                              A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1317                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1318                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1319
1320                 return IRQ_HANDLED;
1321         }
1322
1323         WARN_ON(1);
1324
1325         return IRQ_NONE;
1326 }
1327
1328 static const struct edac_device_prv_data l2ecc_data = {
1329         .setup = altr_l2_check_deps,
1330         .ce_clear_mask = 0,
1331         .ue_clear_mask = 0,
1332         .alloc_mem = l2_alloc_mem,
1333         .free_mem = l2_free_mem,
1334         .ecc_enable_mask = ALTR_L2_ECC_EN,
1335         .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1336         .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1337         .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1338         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1339         .inject_fops = &altr_edac_device_inject_fops,
1340 };
1341
1342 static const struct edac_device_prv_data a10_l2ecc_data = {
1343         .setup = altr_l2_check_deps,
1344         .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1345         .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1346         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1347         .alloc_mem = l2_alloc_mem,
1348         .free_mem = l2_free_mem,
1349         .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1350         .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1351         .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1352         .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1353         .ecc_irq_handler = altr_edac_a10_l2_irq,
1354         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1355         .inject_fops = &altr_edac_device_inject_fops,
1356 };
1357
1358 #endif  /* CONFIG_EDAC_ALTERA_L2C */
1359
1360 /********************* Ethernet Device Functions ********************/
1361
1362 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1363
1364 static const struct edac_device_prv_data a10_enetecc_data = {
1365         .setup = altr_check_ecc_deps,
1366         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1367         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1368         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1369         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1370         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1371         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1372         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1373         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1374         .inject_fops = &altr_edac_a10_device_inject2_fops,
1375 };
1376
1377 static int __init socfpga_init_ethernet_ecc(void)
1378 {
1379         return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1380 }
1381
1382 early_initcall(socfpga_init_ethernet_ecc);
1383
1384 #endif  /* CONFIG_EDAC_ALTERA_ETHERNET */
1385
1386 /********************** NAND Device Functions **********************/
1387
1388 #ifdef CONFIG_EDAC_ALTERA_NAND
1389
1390 static const struct edac_device_prv_data a10_nandecc_data = {
1391         .setup = altr_check_ecc_deps,
1392         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1393         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1394         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1395         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1396         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1397         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1398         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1399         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1400         .inject_fops = &altr_edac_a10_device_inject_fops,
1401 };
1402
1403 static int __init socfpga_init_nand_ecc(void)
1404 {
1405         return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1406 }
1407
1408 early_initcall(socfpga_init_nand_ecc);
1409
1410 #endif  /* CONFIG_EDAC_ALTERA_NAND */
1411
1412 /********************** DMA Device Functions **********************/
1413
1414 #ifdef CONFIG_EDAC_ALTERA_DMA
1415
1416 static const struct edac_device_prv_data a10_dmaecc_data = {
1417         .setup = altr_check_ecc_deps,
1418         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1419         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1420         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1421         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1422         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1423         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1424         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1425         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1426         .inject_fops = &altr_edac_a10_device_inject_fops,
1427 };
1428
1429 static int __init socfpga_init_dma_ecc(void)
1430 {
1431         return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1432 }
1433
1434 early_initcall(socfpga_init_dma_ecc);
1435
1436 #endif  /* CONFIG_EDAC_ALTERA_DMA */
1437
1438 /********************** USB Device Functions **********************/
1439
1440 #ifdef CONFIG_EDAC_ALTERA_USB
1441
1442 static const struct edac_device_prv_data a10_usbecc_data = {
1443         .setup = altr_check_ecc_deps,
1444         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1445         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1446         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1447         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1448         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1449         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1450         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1451         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1452         .inject_fops = &altr_edac_a10_device_inject2_fops,
1453 };
1454
1455 static int __init socfpga_init_usb_ecc(void)
1456 {
1457         return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1458 }
1459
1460 early_initcall(socfpga_init_usb_ecc);
1461
1462 #endif  /* CONFIG_EDAC_ALTERA_USB */
1463
1464 /********************** QSPI Device Functions **********************/
1465
1466 #ifdef CONFIG_EDAC_ALTERA_QSPI
1467
1468 static const struct edac_device_prv_data a10_qspiecc_data = {
1469         .setup = altr_check_ecc_deps,
1470         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1471         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1472         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1473         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1474         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1475         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1476         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1477         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1478         .inject_fops = &altr_edac_a10_device_inject_fops,
1479 };
1480
1481 static int __init socfpga_init_qspi_ecc(void)
1482 {
1483         return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1484 }
1485
1486 early_initcall(socfpga_init_qspi_ecc);
1487
1488 #endif  /* CONFIG_EDAC_ALTERA_QSPI */
1489
1490 /********************* SDMMC Device Functions **********************/
1491
1492 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1493
1494 static const struct edac_device_prv_data a10_sdmmceccb_data;
1495 static int altr_portb_setup(struct altr_edac_device_dev *device)
1496 {
1497         struct edac_device_ctl_info *dci;
1498         struct altr_edac_device_dev *altdev;
1499         char *ecc_name = "sdmmcb-ecc";
1500         int edac_idx, rc;
1501         struct device_node *np;
1502         const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1503
1504         rc = altr_check_ecc_deps(device);
1505         if (rc)
1506                 return rc;
1507
1508         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1509         if (!np) {
1510                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1511                 return -ENODEV;
1512         }
1513
1514         /* Create the PortB EDAC device */
1515         edac_idx = edac_device_alloc_index();
1516         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1517                                          ecc_name, 1, 0, NULL, 0, edac_idx);
1518         if (!dci) {
1519                 edac_printk(KERN_ERR, EDAC_DEVICE,
1520                             "%s: Unable to allocate PortB EDAC device\n",
1521                             ecc_name);
1522                 return -ENOMEM;
1523         }
1524
1525         /* Initialize the PortB EDAC device structure from PortA structure */
1526         altdev = dci->pvt_info;
1527         *altdev = *device;
1528
1529         if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1530                 return -ENOMEM;
1531
1532         /* Update PortB specific values */
1533         altdev->edac_dev_name = ecc_name;
1534         altdev->edac_idx = edac_idx;
1535         altdev->edac_dev = dci;
1536         altdev->data = prv;
1537         dci->dev = &altdev->ddev;
1538         dci->ctl_name = "Altera ECC Manager";
1539         dci->mod_name = ecc_name;
1540         dci->dev_name = ecc_name;
1541
1542         /* Update the IRQs for PortB */
1543         altdev->sb_irq = irq_of_parse_and_map(np, 2);
1544         if (!altdev->sb_irq) {
1545                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1546                 rc = -ENODEV;
1547                 goto err_release_group_1;
1548         }
1549         rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1550                               prv->ecc_irq_handler,
1551                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1552                               ecc_name, altdev);
1553         if (rc) {
1554                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1555                 goto err_release_group_1;
1556         }
1557
1558         altdev->db_irq = irq_of_parse_and_map(np, 3);
1559         if (!altdev->db_irq) {
1560                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1561                 rc = -ENODEV;
1562                 goto err_release_group_1;
1563         }
1564         rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1565                               prv->ecc_irq_handler,
1566                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1567                               ecc_name, altdev);
1568         if (rc) {
1569                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1570                 goto err_release_group_1;
1571         }
1572
1573         rc = edac_device_add_device(dci);
1574         if (rc) {
1575                 edac_printk(KERN_ERR, EDAC_DEVICE,
1576                             "edac_device_add_device portB failed\n");
1577                 rc = -ENOMEM;
1578                 goto err_release_group_1;
1579         }
1580         altr_create_edacdev_dbgfs(dci, prv);
1581
1582         list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1583
1584         devres_remove_group(&altdev->ddev, altr_portb_setup);
1585
1586         return 0;
1587
1588 err_release_group_1:
1589         edac_device_free_ctl_info(dci);
1590         devres_release_group(&altdev->ddev, altr_portb_setup);
1591         edac_printk(KERN_ERR, EDAC_DEVICE,
1592                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1593         return rc;
1594 }
1595
1596 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1597 {
1598         struct altr_edac_device_dev *ad = dev_id;
1599         void __iomem  *base = ad->base;
1600         const struct edac_device_prv_data *priv = ad->data;
1601
1602         if (irq == ad->sb_irq) {
1603                 writel(priv->ce_clear_mask,
1604                        base + ALTR_A10_ECC_INTSTAT_OFST);
1605                 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1606                 return IRQ_HANDLED;
1607         } else if (irq == ad->db_irq) {
1608                 writel(priv->ue_clear_mask,
1609                        base + ALTR_A10_ECC_INTSTAT_OFST);
1610                 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1611                 return IRQ_HANDLED;
1612         }
1613
1614         WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1615
1616         return IRQ_NONE;
1617 }
1618
1619 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1620         .setup = altr_portb_setup,
1621         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1622         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1623         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1624         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1625         .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1626         .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1627         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1628         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1629         .inject_fops = &altr_edac_a10_device_inject_fops,
1630 };
1631
1632 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1633         .setup = altr_portb_setup,
1634         .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1635         .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1636         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1637         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1638         .ce_set_mask = ALTR_A10_ECC_TSERRB,
1639         .ue_set_mask = ALTR_A10_ECC_TDERRB,
1640         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1641         .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1642         .inject_fops = &altr_edac_a10_device_inject_fops,
1643 };
1644
1645 static int __init socfpga_init_sdmmc_ecc(void)
1646 {
1647         int rc = -ENODEV;
1648         struct device_node *child;
1649
1650         if (!socfpga_is_a10() && !socfpga_is_s10())
1651                 return -ENODEV;
1652
1653         child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1654         if (!child) {
1655                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1656                 return -ENODEV;
1657         }
1658
1659         if (!of_device_is_available(child))
1660                 goto exit;
1661
1662         if (validate_parent_available(child))
1663                 goto exit;
1664
1665         rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1666                                      a10_sdmmcecca_data.ecc_enable_mask, 1);
1667 exit:
1668         of_node_put(child);
1669         return rc;
1670 }
1671
1672 early_initcall(socfpga_init_sdmmc_ecc);
1673
1674 #endif  /* CONFIG_EDAC_ALTERA_SDMMC */
1675
1676 /********************* Arria10 EDAC Device Functions *************************/
1677 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1678 #ifdef CONFIG_EDAC_ALTERA_L2C
1679         { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1680 #endif
1681 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1682         { .compatible = "altr,socfpga-a10-ocram-ecc",
1683           .data = &a10_ocramecc_data },
1684 #endif
1685 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1686         { .compatible = "altr,socfpga-eth-mac-ecc",
1687           .data = &a10_enetecc_data },
1688 #endif
1689 #ifdef CONFIG_EDAC_ALTERA_NAND
1690         { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1691 #endif
1692 #ifdef CONFIG_EDAC_ALTERA_DMA
1693         { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1694 #endif
1695 #ifdef CONFIG_EDAC_ALTERA_USB
1696         { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1697 #endif
1698 #ifdef CONFIG_EDAC_ALTERA_QSPI
1699         { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1700 #endif
1701 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1702         { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1703 #endif
1704         {},
1705 };
1706 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1707
1708 /*
1709  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1710  * because 2 IRQs are shared among the all ECC peripherals. The ECC
1711  * manager manages the IRQs and the children.
1712  * Based on xgene_edac.c peripheral code.
1713  */
1714
1715 static ssize_t altr_edac_a10_device_trig(struct file *file,
1716                                          const char __user *user_buf,
1717                                          size_t count, loff_t *ppos)
1718 {
1719         struct edac_device_ctl_info *edac_dci = file->private_data;
1720         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1721         const struct edac_device_prv_data *priv = drvdata->data;
1722         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1723         unsigned long flags;
1724         u8 trig_type;
1725
1726         if (!user_buf || get_user(trig_type, user_buf))
1727                 return -EFAULT;
1728
1729         local_irq_save(flags);
1730         if (trig_type == ALTR_UE_TRIGGER_CHAR)
1731                 writel(priv->ue_set_mask, set_addr);
1732         else
1733                 writel(priv->ce_set_mask, set_addr);
1734
1735         /* Ensure the interrupt test bits are set */
1736         wmb();
1737         local_irq_restore(flags);
1738
1739         return count;
1740 }
1741
1742 /*
1743  * The Stratix10 EDAC Error Injection Functions differ from Arria10
1744  * slightly. A few Arria10 peripherals can use this injection function.
1745  * Inject the error into the memory and then readback to trigger the IRQ.
1746  */
1747 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1748                                           const char __user *user_buf,
1749                                           size_t count, loff_t *ppos)
1750 {
1751         struct edac_device_ctl_info *edac_dci = file->private_data;
1752         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1753         const struct edac_device_prv_data *priv = drvdata->data;
1754         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1755         unsigned long flags;
1756         u8 trig_type;
1757
1758         if (!user_buf || get_user(trig_type, user_buf))
1759                 return -EFAULT;
1760
1761         local_irq_save(flags);
1762         if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1763                 writel(priv->ue_set_mask, set_addr);
1764         } else {
1765                 /* Setup write of 0 to first 4 bytes */
1766                 writel(0x0, drvdata->base + ECC_BLK_WDATA0_OFST);
1767                 writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
1768                 writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
1769                 writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
1770                 /* Setup write of 4 bytes */
1771                 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1772                 /* Setup Address to 0 */
1773                 writel(0x0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1774                 /* Setup accctrl to write & data override */
1775                 writel(ECC_WRITE_DOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1776                 /* Kick it. */
1777                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1778                 /* Setup accctrl to read & ecc override */
1779                 writel(ECC_READ_EOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1780                 /* Kick it. */
1781                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1782                 /* Setup write for single bit change */
1783                 writel(0x1, drvdata->base + ECC_BLK_WDATA0_OFST);
1784                 writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
1785                 writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
1786                 writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
1787                 /* Copy Read ECC to Write ECC */
1788                 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1789                        drvdata->base + ECC_BLK_WECC0_OFST);
1790                 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1791                        drvdata->base + ECC_BLK_WECC1_OFST);
1792                 /* Setup accctrl to write & ecc override & data override */
1793                 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1794                 /* Kick it. */
1795                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1796                 /* Setup accctrl to read & ecc overwrite & data overwrite */
1797                 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1798                 /* Kick it. */
1799                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1800         }
1801
1802         /* Ensure the interrupt test bits are set */
1803         wmb();
1804         local_irq_restore(flags);
1805
1806         return count;
1807 }
1808
1809 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1810 {
1811         int dberr, bit, sm_offset, irq_status;
1812         struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1813         struct irq_chip *chip = irq_desc_get_chip(desc);
1814         int irq = irq_desc_get_irq(desc);
1815
1816         dberr = (irq == edac->db_irq) ? 1 : 0;
1817         sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1818                             A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1819
1820         chained_irq_enter(chip, desc);
1821
1822         regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1823
1824         for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1825                 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1826                 if (irq)
1827                         generic_handle_irq(irq);
1828         }
1829
1830         chained_irq_exit(chip, desc);
1831 }
1832
1833 static int validate_parent_available(struct device_node *np)
1834 {
1835         struct device_node *parent;
1836         int ret = 0;
1837
1838         /* Ensure parent device is enabled if parent node exists */
1839         parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1840         if (parent && !of_device_is_available(parent))
1841                 ret = -ENODEV;
1842
1843         of_node_put(parent);
1844         return ret;
1845 }
1846
1847 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1848                                     struct device_node *np)
1849 {
1850         struct edac_device_ctl_info *dci;
1851         struct altr_edac_device_dev *altdev;
1852         char *ecc_name = (char *)np->name;
1853         struct resource res;
1854         int edac_idx;
1855         int rc = 0;
1856         const struct edac_device_prv_data *prv;
1857         /* Get matching node and check for valid result */
1858         const struct of_device_id *pdev_id =
1859                 of_match_node(altr_edac_a10_device_of_match, np);
1860         if (IS_ERR_OR_NULL(pdev_id))
1861                 return -ENODEV;
1862
1863         /* Get driver specific data for this EDAC device */
1864         prv = pdev_id->data;
1865         if (IS_ERR_OR_NULL(prv))
1866                 return -ENODEV;
1867
1868         if (validate_parent_available(np))
1869                 return -ENODEV;
1870
1871         if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1872                 return -ENOMEM;
1873
1874         rc = of_address_to_resource(np, 0, &res);
1875         if (rc < 0) {
1876                 edac_printk(KERN_ERR, EDAC_DEVICE,
1877                             "%s: no resource address\n", ecc_name);
1878                 goto err_release_group;
1879         }
1880
1881         edac_idx = edac_device_alloc_index();
1882         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1883                                          1, ecc_name, 1, 0, NULL, 0,
1884                                          edac_idx);
1885
1886         if (!dci) {
1887                 edac_printk(KERN_ERR, EDAC_DEVICE,
1888                             "%s: Unable to allocate EDAC device\n", ecc_name);
1889                 rc = -ENOMEM;
1890                 goto err_release_group;
1891         }
1892
1893         altdev = dci->pvt_info;
1894         dci->dev = edac->dev;
1895         altdev->edac_dev_name = ecc_name;
1896         altdev->edac_idx = edac_idx;
1897         altdev->edac = edac;
1898         altdev->edac_dev = dci;
1899         altdev->data = prv;
1900         altdev->ddev = *edac->dev;
1901         dci->dev = &altdev->ddev;
1902         dci->ctl_name = "Altera ECC Manager";
1903         dci->mod_name = ecc_name;
1904         dci->dev_name = ecc_name;
1905
1906         altdev->base = devm_ioremap_resource(edac->dev, &res);
1907         if (IS_ERR(altdev->base)) {
1908                 rc = PTR_ERR(altdev->base);
1909                 goto err_release_group1;
1910         }
1911
1912         /* Check specific dependencies for the module */
1913         if (altdev->data->setup) {
1914                 rc = altdev->data->setup(altdev);
1915                 if (rc)
1916                         goto err_release_group1;
1917         }
1918
1919         altdev->sb_irq = irq_of_parse_and_map(np, 0);
1920         if (!altdev->sb_irq) {
1921                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1922                 rc = -ENODEV;
1923                 goto err_release_group1;
1924         }
1925         rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1926                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1927                               ecc_name, altdev);
1928         if (rc) {
1929                 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1930                 goto err_release_group1;
1931         }
1932
1933         altdev->db_irq = irq_of_parse_and_map(np, 1);
1934         if (!altdev->db_irq) {
1935                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1936                 rc = -ENODEV;
1937                 goto err_release_group1;
1938         }
1939         rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1940                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1941                               ecc_name, altdev);
1942         if (rc) {
1943                 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1944                 goto err_release_group1;
1945         }
1946
1947         rc = edac_device_add_device(dci);
1948         if (rc) {
1949                 dev_err(edac->dev, "edac_device_add_device failed\n");
1950                 rc = -ENOMEM;
1951                 goto err_release_group1;
1952         }
1953
1954         altr_create_edacdev_dbgfs(dci, prv);
1955
1956         list_add(&altdev->next, &edac->a10_ecc_devices);
1957
1958         devres_remove_group(edac->dev, altr_edac_a10_device_add);
1959
1960         return 0;
1961
1962 err_release_group1:
1963         edac_device_free_ctl_info(dci);
1964 err_release_group:
1965         devres_release_group(edac->dev, NULL);
1966         edac_printk(KERN_ERR, EDAC_DEVICE,
1967                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1968
1969         return rc;
1970 }
1971
1972 static void a10_eccmgr_irq_mask(struct irq_data *d)
1973 {
1974         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1975
1976         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1977                      BIT(d->hwirq));
1978 }
1979
1980 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1981 {
1982         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1983
1984         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
1985                      BIT(d->hwirq));
1986 }
1987
1988 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
1989                                     irq_hw_number_t hwirq)
1990 {
1991         struct altr_arria10_edac *edac = d->host_data;
1992
1993         irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
1994         irq_set_chip_data(irq, edac);
1995         irq_set_noprobe(irq);
1996
1997         return 0;
1998 }
1999
2000 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2001         .map = a10_eccmgr_irqdomain_map,
2002         .xlate = irq_domain_xlate_twocell,
2003 };
2004
2005 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2006 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2007
2008 /*
2009  * The double bit error is handled through SError which is fatal. This is
2010  * called as a panic notifier to printout ECC error info as part of the panic.
2011  */
2012 static int s10_edac_dberr_handler(struct notifier_block *this,
2013                                   unsigned long event, void *ptr)
2014 {
2015         struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2016         int err_addr, dberror;
2017
2018         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2019                     &dberror);
2020         regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2021         if (dberror & S10_DDR0_IRQ_MASK) {
2022                 regmap_read(edac->ecc_mgr_map, A10_DERRADDR_OFST, &err_addr);
2023                 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2024                              err_addr);
2025                 edac_printk(KERN_ERR, EDAC_MC,
2026                             "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
2027                             err_addr);
2028         }
2029
2030         return NOTIFY_DONE;
2031 }
2032
2033 /****************** Arria 10 EDAC Probe Function *********************/
2034 static int altr_edac_a10_probe(struct platform_device *pdev)
2035 {
2036         struct altr_arria10_edac *edac;
2037         struct device_node *child;
2038
2039         edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2040         if (!edac)
2041                 return -ENOMEM;
2042
2043         edac->dev = &pdev->dev;
2044         platform_set_drvdata(pdev, edac);
2045         INIT_LIST_HEAD(&edac->a10_ecc_devices);
2046
2047         if (socfpga_is_a10()) {
2048                 edac->ecc_mgr_map =
2049                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2050                                                         "altr,sysmgr-syscon");
2051         } else {
2052                 struct device_node *sysmgr_np;
2053                 struct resource res;
2054                 uintptr_t base;
2055
2056                 sysmgr_np = of_parse_phandle(pdev->dev.of_node,
2057                                              "altr,sysmgr-syscon", 0);
2058                 if (!sysmgr_np) {
2059                         edac_printk(KERN_ERR, EDAC_DEVICE,
2060                                     "Unable to find altr,sysmgr-syscon\n");
2061                         return -ENODEV;
2062                 }
2063
2064                 if (of_address_to_resource(sysmgr_np, 0, &res))
2065                         return -ENOMEM;
2066
2067                 /* Need physical address for SMCC call */
2068                 base = res.start;
2069
2070                 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
2071                                                      (void *)base,
2072                                                      &s10_sdram_regmap_cfg);
2073         }
2074
2075         if (IS_ERR(edac->ecc_mgr_map)) {
2076                 edac_printk(KERN_ERR, EDAC_DEVICE,
2077                             "Unable to get syscon altr,sysmgr-syscon\n");
2078                 return PTR_ERR(edac->ecc_mgr_map);
2079         }
2080
2081         edac->irq_chip.name = pdev->dev.of_node->name;
2082         edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2083         edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2084         edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2085                                              &a10_eccmgr_ic_ops, edac);
2086         if (!edac->domain) {
2087                 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2088                 return -ENOMEM;
2089         }
2090
2091         edac->sb_irq = platform_get_irq(pdev, 0);
2092         if (edac->sb_irq < 0) {
2093                 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2094                 return edac->sb_irq;
2095         }
2096
2097         irq_set_chained_handler_and_data(edac->sb_irq,
2098                                          altr_edac_a10_irq_handler,
2099                                          edac);
2100
2101         if (socfpga_is_a10()) {
2102                 edac->db_irq = platform_get_irq(pdev, 1);
2103                 if (edac->db_irq < 0) {
2104                         dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2105                         return edac->db_irq;
2106                 }
2107                 irq_set_chained_handler_and_data(edac->db_irq,
2108                                                  altr_edac_a10_irq_handler,
2109                                                  edac);
2110         } else {
2111                 int dberror, err_addr;
2112
2113                 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2114                 atomic_notifier_chain_register(&panic_notifier_list,
2115                                                &edac->panic_notifier);
2116
2117                 /* Printout a message if uncorrectable error previously. */
2118                 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2119                             &dberror);
2120                 if (dberror) {
2121                         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2122                                     &err_addr);
2123                         edac_printk(KERN_ERR, EDAC_DEVICE,
2124                                     "Previous Boot UE detected[0x%X] @ 0x%X\n",
2125                                     dberror, err_addr);
2126                         /* Reset the sticky registers */
2127                         regmap_write(edac->ecc_mgr_map,
2128                                      S10_SYSMGR_UE_VAL_OFST, 0);
2129                         regmap_write(edac->ecc_mgr_map,
2130                                      S10_SYSMGR_UE_ADDR_OFST, 0);
2131                 }
2132         }
2133
2134         for_each_child_of_node(pdev->dev.of_node, child) {
2135                 if (!of_device_is_available(child))
2136                         continue;
2137
2138                 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2139                     of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2140                     of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2141                     of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2142                     of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2143                     of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2144                     of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2145                     of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2146
2147                         altr_edac_a10_device_add(edac, child);
2148
2149 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2150                 else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) ||
2151                          (of_device_is_compatible(child, "altr,sdram-edac-s10")))
2152                         of_platform_populate(pdev->dev.of_node,
2153                                              altr_sdram_ctrl_of_match,
2154                                              NULL, &pdev->dev);
2155 #endif
2156         }
2157
2158         return 0;
2159 }
2160
2161 static const struct of_device_id altr_edac_a10_of_match[] = {
2162         { .compatible = "altr,socfpga-a10-ecc-manager" },
2163         { .compatible = "altr,socfpga-s10-ecc-manager" },
2164         {},
2165 };
2166 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2167
2168 static struct platform_driver altr_edac_a10_driver = {
2169         .probe =  altr_edac_a10_probe,
2170         .driver = {
2171                 .name = "socfpga_a10_ecc_manager",
2172                 .of_match_table = altr_edac_a10_of_match,
2173         },
2174 };
2175 module_platform_driver(altr_edac_a10_driver);
2176
2177 MODULE_LICENSE("GPL v2");
2178 MODULE_AUTHOR("Thor Thayer");
2179 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");