1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/genalloc.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/notifier.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/types.h>
24 #include <linux/uaccess.h>
26 #include "altera_edac.h"
27 #include "edac_module.h"
29 #define EDAC_MOD_STR "altera_edac"
30 #define EDAC_DEVICE "Altera"
32 static const struct altr_sdram_prv_data c5_data = {
33 .ecc_ctrl_offset = CV_CTLCFG_OFST,
34 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
35 .ecc_stat_offset = CV_DRAMSTS_OFST,
36 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
37 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
38 .ecc_saddr_offset = CV_ERRADDR_OFST,
39 .ecc_daddr_offset = CV_ERRADDR_OFST,
40 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
41 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
42 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
43 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
44 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
45 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
46 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
47 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
48 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
49 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
50 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
53 static const struct altr_sdram_prv_data a10_data = {
54 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
55 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
56 .ecc_stat_offset = A10_INTSTAT_OFST,
57 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
58 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
59 .ecc_saddr_offset = A10_SERRADDR_OFST,
60 .ecc_daddr_offset = A10_DERRADDR_OFST,
61 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
62 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
63 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
64 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
65 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
66 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
67 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
68 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
69 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
72 static const struct altr_sdram_prv_data s10_data = {
73 .ecc_ctrl_offset = S10_ECCCTRL1_OFST,
74 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
75 .ecc_stat_offset = S10_INTSTAT_OFST,
76 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
77 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
78 .ecc_saddr_offset = S10_SERRADDR_OFST,
79 .ecc_daddr_offset = S10_DERRADDR_OFST,
80 .ecc_irq_en_offset = S10_ERRINTEN_OFST,
81 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
82 .ecc_irq_clr_offset = S10_INTSTAT_OFST,
83 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
84 .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
85 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
86 .ce_ue_trgr_offset = S10_DIAGINTTEST_OFST,
87 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
88 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
91 /*********************** EDAC Memory Controller Functions ****************/
93 /* The SDRAM controller uses the EDAC Memory Controller framework. */
95 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
97 struct mem_ctl_info *mci = dev_id;
98 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
99 const struct altr_sdram_prv_data *priv = drvdata->data;
100 u32 status, err_count = 1, err_addr;
102 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
104 if (status & priv->ecc_stat_ue_mask) {
105 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
107 if (priv->ecc_uecnt_offset)
108 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
110 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
111 err_count, err_addr);
113 if (status & priv->ecc_stat_ce_mask) {
114 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
116 if (priv->ecc_uecnt_offset)
117 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
119 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
120 err_addr >> PAGE_SHIFT,
121 err_addr & ~PAGE_MASK, 0,
122 0, 0, -1, mci->ctl_name, "");
123 /* Clear IRQ to resume */
124 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
125 priv->ecc_irq_clr_mask);
132 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
133 const char __user *data,
134 size_t count, loff_t *ppos)
136 struct mem_ctl_info *mci = file->private_data;
137 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
138 const struct altr_sdram_prv_data *priv = drvdata->data;
140 dma_addr_t dma_handle;
143 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
145 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
146 edac_printk(KERN_ERR, EDAC_MC,
147 "Inject: Buffer Allocation error\n");
151 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
153 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
155 /* Error are injected by writing a word while the SBE or DBE
156 * bit in the CTLCFG register is set. Reading the word will
157 * trigger the SBE or DBE error and the corresponding IRQ.
160 edac_printk(KERN_ALERT, EDAC_MC,
161 "Inject Double bit error\n");
163 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
164 (read_reg | priv->ue_set_mask));
167 edac_printk(KERN_ALERT, EDAC_MC,
168 "Inject Single bit error\n");
170 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
171 (read_reg | priv->ce_set_mask));
175 ptemp[0] = 0x5A5A5A5A;
176 ptemp[1] = 0xA5A5A5A5;
178 /* Clear the error injection bits */
179 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
180 /* Ensure it has been written out */
184 * To trigger the error, we need to read the data back
185 * (the data was written with errors above).
186 * The READ_ONCE macros and printk are used to prevent the
187 * the compiler optimizing these reads out.
189 reg = READ_ONCE(ptemp[0]);
190 read_reg = READ_ONCE(ptemp[1]);
194 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
197 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
202 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
204 .write = altr_sdr_mc_err_inject_write,
205 .llseek = generic_file_llseek,
208 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
210 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
216 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
217 &altr_sdr_mc_debug_inject_fops);
220 /* Get total memory size from Open Firmware DTB */
221 static unsigned long get_total_mem(void)
223 struct device_node *np = NULL;
226 unsigned long total_mem = 0;
228 for_each_node_by_type(np, "memory") {
229 ret = of_address_to_resource(np, 0, &res);
233 total_mem += resource_size(&res);
235 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
239 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
240 { .compatible = "altr,sdram-edac", .data = &c5_data},
241 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
242 { .compatible = "altr,sdram-edac-s10", .data = &s10_data},
245 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
247 static int a10_init(struct regmap *mc_vbase)
249 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
250 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
251 edac_printk(KERN_ERR, EDAC_MC,
252 "Error setting SB IRQ mode\n");
256 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
257 edac_printk(KERN_ERR, EDAC_MC,
258 "Error setting trigger count\n");
265 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
267 void __iomem *sm_base;
270 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
271 dev_name(&pdev->dev))) {
272 edac_printk(KERN_ERR, EDAC_MC,
273 "Unable to request mem region\n");
277 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
279 edac_printk(KERN_ERR, EDAC_MC,
280 "Unable to ioremap device\n");
286 iowrite32(mask, sm_base);
291 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
296 static int altr_sdram_probe(struct platform_device *pdev)
298 const struct of_device_id *id;
299 struct edac_mc_layer layers[2];
300 struct mem_ctl_info *mci;
301 struct altr_sdram_mc_data *drvdata;
302 const struct altr_sdram_prv_data *priv;
303 struct regmap *mc_vbase;
304 struct dimm_info *dimm;
306 int irq, irq2, res = 0;
307 unsigned long mem_size, irqflags = 0;
309 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
313 /* Grab the register range from the sdr controller in device tree */
314 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
316 if (IS_ERR(mc_vbase)) {
317 edac_printk(KERN_ERR, EDAC_MC,
318 "regmap for altr,sdr-syscon lookup failed.\n");
322 /* Check specific dependencies for the module */
323 priv = of_match_node(altr_sdram_ctrl_of_match,
324 pdev->dev.of_node)->data;
326 /* Validate the SDRAM controller has ECC enabled */
327 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
328 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
329 edac_printk(KERN_ERR, EDAC_MC,
330 "No ECC/ECC disabled [0x%08X]\n", read_reg);
334 /* Grab memory size from device tree. */
335 mem_size = get_total_mem();
337 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
341 /* Ensure the SDRAM Interrupt is disabled */
342 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
343 priv->ecc_irq_en_mask, 0)) {
344 edac_printk(KERN_ERR, EDAC_MC,
345 "Error disabling SDRAM ECC IRQ\n");
349 /* Toggle to clear the SDRAM Error count */
350 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
351 priv->ecc_cnt_rst_mask,
352 priv->ecc_cnt_rst_mask)) {
353 edac_printk(KERN_ERR, EDAC_MC,
354 "Error clearing SDRAM ECC count\n");
358 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
359 priv->ecc_cnt_rst_mask, 0)) {
360 edac_printk(KERN_ERR, EDAC_MC,
361 "Error clearing SDRAM ECC count\n");
365 irq = platform_get_irq(pdev, 0);
367 edac_printk(KERN_ERR, EDAC_MC,
368 "No irq %d in DT\n", irq);
372 /* Arria10 has a 2nd IRQ */
373 irq2 = platform_get_irq(pdev, 1);
375 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
377 layers[0].is_virt_csrow = true;
378 layers[1].type = EDAC_MC_LAYER_CHANNEL;
380 layers[1].is_virt_csrow = false;
381 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
382 sizeof(struct altr_sdram_mc_data));
386 mci->pdev = &pdev->dev;
387 drvdata = mci->pvt_info;
388 drvdata->mc_vbase = mc_vbase;
389 drvdata->data = priv;
390 platform_set_drvdata(pdev, mci);
392 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
393 edac_printk(KERN_ERR, EDAC_MC,
394 "Unable to get managed device resource\n");
399 mci->mtype_cap = MEM_FLAG_DDR3;
400 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
401 mci->edac_cap = EDAC_FLAG_SECDED;
402 mci->mod_name = EDAC_MOD_STR;
403 mci->ctl_name = dev_name(&pdev->dev);
404 mci->scrub_mode = SCRUB_SW_SRC;
405 mci->dev_name = dev_name(&pdev->dev);
408 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
410 dimm->dtype = DEV_X8;
411 dimm->mtype = MEM_DDR3;
412 dimm->edac_mode = EDAC_SECDED;
414 res = edac_mc_add_mc(mci);
418 /* Only the Arria10 has separate IRQs */
420 /* Arria10 specific initialization */
421 res = a10_init(mc_vbase);
425 res = devm_request_irq(&pdev->dev, irq2,
426 altr_sdram_mc_err_handler,
427 IRQF_SHARED, dev_name(&pdev->dev), mci);
429 edac_mc_printk(mci, KERN_ERR,
430 "Unable to request irq %d\n", irq2);
435 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
439 irqflags = IRQF_SHARED;
442 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
443 irqflags, dev_name(&pdev->dev), mci);
445 edac_mc_printk(mci, KERN_ERR,
446 "Unable to request irq %d\n", irq);
451 /* Infrastructure ready - enable the IRQ */
452 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
453 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
454 edac_mc_printk(mci, KERN_ERR,
455 "Error enabling SDRAM ECC IRQ\n");
460 altr_sdr_mc_create_debugfs_nodes(mci);
462 devres_close_group(&pdev->dev, NULL);
467 edac_mc_del_mc(&pdev->dev);
469 devres_release_group(&pdev->dev, NULL);
472 edac_printk(KERN_ERR, EDAC_MC,
473 "EDAC Probe Failed; Error %d\n", res);
478 static int altr_sdram_remove(struct platform_device *pdev)
480 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
482 edac_mc_del_mc(&pdev->dev);
484 platform_set_drvdata(pdev, NULL);
489 /**************** Stratix 10 EDAC Memory Controller Functions ************/
492 * s10_protected_reg_write
493 * Write to a protected SMC register.
494 * @context: Not used.
495 * @reg: Address of register
496 * @value: Value to write
497 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
498 * INTEL_SIP_SMC_REG_ERROR on error
499 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
501 static int s10_protected_reg_write(void *context, unsigned int reg,
504 struct arm_smccc_res result;
506 arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
509 return (int)result.a0;
513 * s10_protected_reg_read
514 * Read the status of a protected SMC register
515 * @context: Not used.
516 * @reg: Address of register
517 * @value: Value read.
518 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
519 * INTEL_SIP_SMC_REG_ERROR on error
520 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
522 static int s10_protected_reg_read(void *context, unsigned int reg,
525 struct arm_smccc_res result;
527 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
530 *val = (unsigned int)result.a1;
532 return (int)result.a0;
535 static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg)
538 case S10_ECCCTRL1_OFST:
539 case S10_ERRINTEN_OFST:
540 case S10_INTMODE_OFST:
541 case S10_INTSTAT_OFST:
542 case S10_DIAGINTTEST_OFST:
543 case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
544 case S10_SYSMGR_ECC_INTMASK_SET_OFST:
545 case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
551 static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg)
554 case S10_ECCCTRL1_OFST:
555 case S10_ERRINTEN_OFST:
556 case S10_INTMODE_OFST:
557 case S10_INTSTAT_OFST:
558 case S10_DERRADDR_OFST:
559 case S10_SERRADDR_OFST:
560 case S10_DIAGINTTEST_OFST:
561 case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
562 case S10_SYSMGR_ECC_INTMASK_SET_OFST:
563 case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
564 case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
565 case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
571 static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg)
574 case S10_ECCCTRL1_OFST:
575 case S10_ERRINTEN_OFST:
576 case S10_INTMODE_OFST:
577 case S10_INTSTAT_OFST:
578 case S10_DERRADDR_OFST:
579 case S10_SERRADDR_OFST:
580 case S10_DIAGINTTEST_OFST:
581 case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
582 case S10_SYSMGR_ECC_INTMASK_SET_OFST:
583 case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
584 case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
585 case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
591 static const struct regmap_config s10_sdram_regmap_cfg = {
596 .max_register = 0xffffffff,
597 .writeable_reg = s10_sdram_writeable_reg,
598 .readable_reg = s10_sdram_readable_reg,
599 .volatile_reg = s10_sdram_volatile_reg,
600 .reg_read = s10_protected_reg_read,
601 .reg_write = s10_protected_reg_write,
602 .use_single_read = true,
603 .use_single_write = true,
606 static int altr_s10_sdram_probe(struct platform_device *pdev)
608 const struct of_device_id *id;
609 struct edac_mc_layer layers[2];
610 struct mem_ctl_info *mci;
611 struct altr_sdram_mc_data *drvdata;
612 const struct altr_sdram_prv_data *priv;
613 struct regmap *regmap;
614 struct dimm_info *dimm;
617 unsigned long mem_size;
619 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
623 /* Grab specific offsets and masks for Stratix10 */
624 priv = of_match_node(altr_sdram_ctrl_of_match,
625 pdev->dev.of_node)->data;
627 regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv,
628 &s10_sdram_regmap_cfg);
630 return PTR_ERR(regmap);
632 /* Validate the SDRAM controller has ECC enabled */
633 if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) ||
634 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
635 edac_printk(KERN_ERR, EDAC_MC,
636 "No ECC/ECC disabled [0x%08X]\n", read_reg);
640 /* Grab memory size from device tree. */
641 mem_size = get_total_mem();
643 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
647 /* Ensure the SDRAM Interrupt is disabled */
648 if (regmap_update_bits(regmap, priv->ecc_irq_en_offset,
649 priv->ecc_irq_en_mask, 0)) {
650 edac_printk(KERN_ERR, EDAC_MC,
651 "Error disabling SDRAM ECC IRQ\n");
655 /* Toggle to clear the SDRAM Error count */
656 if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
657 priv->ecc_cnt_rst_mask,
658 priv->ecc_cnt_rst_mask)) {
659 edac_printk(KERN_ERR, EDAC_MC,
660 "Error clearing SDRAM ECC count\n");
664 if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
665 priv->ecc_cnt_rst_mask, 0)) {
666 edac_printk(KERN_ERR, EDAC_MC,
667 "Error clearing SDRAM ECC count\n");
671 irq = platform_get_irq(pdev, 0);
673 edac_printk(KERN_ERR, EDAC_MC,
674 "No irq %d in DT\n", irq);
678 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
680 layers[0].is_virt_csrow = true;
681 layers[1].type = EDAC_MC_LAYER_CHANNEL;
683 layers[1].is_virt_csrow = false;
684 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
685 sizeof(struct altr_sdram_mc_data));
689 mci->pdev = &pdev->dev;
690 drvdata = mci->pvt_info;
691 drvdata->mc_vbase = regmap;
692 drvdata->data = priv;
693 platform_set_drvdata(pdev, mci);
695 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
696 edac_printk(KERN_ERR, EDAC_MC,
697 "Unable to get managed device resource\n");
702 mci->mtype_cap = MEM_FLAG_DDR3;
703 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
704 mci->edac_cap = EDAC_FLAG_SECDED;
705 mci->mod_name = EDAC_MOD_STR;
706 mci->ctl_name = dev_name(&pdev->dev);
707 mci->scrub_mode = SCRUB_SW_SRC;
708 mci->dev_name = dev_name(&pdev->dev);
711 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
713 dimm->dtype = DEV_X8;
714 dimm->mtype = MEM_DDR3;
715 dimm->edac_mode = EDAC_SECDED;
717 ret = edac_mc_add_mc(mci);
721 ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
722 IRQF_SHARED, dev_name(&pdev->dev), mci);
724 edac_mc_printk(mci, KERN_ERR,
725 "Unable to request irq %d\n", irq);
730 if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
731 S10_DDR0_IRQ_MASK)) {
732 edac_printk(KERN_ERR, EDAC_MC,
733 "Error clearing SDRAM ECC count\n");
738 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
739 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
740 edac_mc_printk(mci, KERN_ERR,
741 "Error enabling SDRAM ECC IRQ\n");
746 altr_sdr_mc_create_debugfs_nodes(mci);
748 devres_close_group(&pdev->dev, NULL);
753 edac_mc_del_mc(&pdev->dev);
755 devres_release_group(&pdev->dev, NULL);
758 edac_printk(KERN_ERR, EDAC_MC,
759 "EDAC Probe Failed; Error %d\n", ret);
764 static int altr_s10_sdram_remove(struct platform_device *pdev)
766 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
768 edac_mc_del_mc(&pdev->dev);
770 platform_set_drvdata(pdev, NULL);
775 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
778 * If you want to suspend, need to disable EDAC by removing it
779 * from the device tree or defconfig.
782 static int altr_sdram_prepare(struct device *dev)
784 pr_err("Suspend not allowed when EDAC is enabled.\n");
789 static const struct dev_pm_ops altr_sdram_pm_ops = {
790 .prepare = altr_sdram_prepare,
794 static struct platform_driver altr_sdram_edac_driver = {
795 .probe = altr_sdram_probe,
796 .remove = altr_sdram_remove,
798 .name = "altr_sdram_edac",
800 .pm = &altr_sdram_pm_ops,
802 .of_match_table = altr_sdram_ctrl_of_match,
806 module_platform_driver(altr_sdram_edac_driver);
808 static struct platform_driver altr_s10_sdram_edac_driver = {
809 .probe = altr_s10_sdram_probe,
810 .remove = altr_s10_sdram_remove,
812 .name = "altr_s10_sdram_edac",
814 .pm = &altr_sdram_pm_ops,
816 .of_match_table = altr_sdram_ctrl_of_match,
820 module_platform_driver(altr_s10_sdram_edac_driver);
822 /************************* EDAC Parent Probe *************************/
824 static const struct of_device_id altr_edac_device_of_match[];
826 static const struct of_device_id altr_edac_of_match[] = {
827 { .compatible = "altr,socfpga-ecc-manager" },
830 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
832 static int altr_edac_probe(struct platform_device *pdev)
834 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
839 static struct platform_driver altr_edac_driver = {
840 .probe = altr_edac_probe,
842 .name = "socfpga_ecc_manager",
843 .of_match_table = altr_edac_of_match,
846 module_platform_driver(altr_edac_driver);
848 /************************* EDAC Device Functions *************************/
851 * EDAC Device Functions (shared between various IPs).
852 * The discrete memories use the EDAC Device framework. The probe
853 * and error handling functions are very similar between memories
854 * so they are shared. The memory allocation and freeing for EDAC
855 * trigger testing are different for each memory.
858 static const struct edac_device_prv_data ocramecc_data;
859 static const struct edac_device_prv_data l2ecc_data;
860 static const struct edac_device_prv_data a10_ocramecc_data;
861 static const struct edac_device_prv_data a10_l2ecc_data;
863 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
865 irqreturn_t ret_value = IRQ_NONE;
866 struct edac_device_ctl_info *dci = dev_id;
867 struct altr_edac_device_dev *drvdata = dci->pvt_info;
868 const struct edac_device_prv_data *priv = drvdata->data;
870 if (irq == drvdata->sb_irq) {
871 if (priv->ce_clear_mask)
872 writel(priv->ce_clear_mask, drvdata->base);
873 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
874 ret_value = IRQ_HANDLED;
875 } else if (irq == drvdata->db_irq) {
876 if (priv->ue_clear_mask)
877 writel(priv->ue_clear_mask, drvdata->base);
878 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
879 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
880 ret_value = IRQ_HANDLED;
888 static ssize_t altr_edac_device_trig(struct file *file,
889 const char __user *user_buf,
890 size_t count, loff_t *ppos)
893 u32 *ptemp, i, error_mask;
897 struct edac_device_ctl_info *edac_dci = file->private_data;
898 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
899 const struct edac_device_prv_data *priv = drvdata->data;
900 void *generic_ptr = edac_dci->dev;
902 if (!user_buf || get_user(trig_type, user_buf))
905 if (!priv->alloc_mem)
909 * Note that generic_ptr is initialized to the device * but in
910 * some alloc_functions, this is overridden and returns data.
912 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
914 edac_printk(KERN_ERR, EDAC_DEVICE,
915 "Inject: Buffer Allocation error\n");
919 if (trig_type == ALTR_UE_TRIGGER_CHAR)
920 error_mask = priv->ue_set_mask;
922 error_mask = priv->ce_set_mask;
924 edac_printk(KERN_ALERT, EDAC_DEVICE,
925 "Trigger Error Mask (0x%X)\n", error_mask);
927 local_irq_save(flags);
928 /* write ECC corrupted data out. */
929 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
930 /* Read data so we're in the correct state */
932 if (READ_ONCE(ptemp[i]))
934 /* Toggle Error bit (it is latched), leave ECC enabled */
935 writel(error_mask, (drvdata->base + priv->set_err_ofst));
936 writel(priv->ecc_enable_mask, (drvdata->base +
937 priv->set_err_ofst));
940 /* Ensure it has been written out */
942 local_irq_restore(flags);
945 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
947 /* Read out written data. ECC error caused here */
948 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
949 if (READ_ONCE(ptemp[i]) != i)
950 edac_printk(KERN_ERR, EDAC_DEVICE,
951 "Read doesn't match written data\n");
954 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
959 static const struct file_operations altr_edac_device_inject_fops = {
961 .write = altr_edac_device_trig,
962 .llseek = generic_file_llseek,
965 static ssize_t altr_edac_a10_device_trig(struct file *file,
966 const char __user *user_buf,
967 size_t count, loff_t *ppos);
969 static const struct file_operations altr_edac_a10_device_inject_fops = {
971 .write = altr_edac_a10_device_trig,
972 .llseek = generic_file_llseek,
975 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
976 const struct edac_device_prv_data *priv)
978 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
980 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
983 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
984 if (!drvdata->debugfs_dir)
987 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
988 drvdata->debugfs_dir, edac_dci,
990 debugfs_remove_recursive(drvdata->debugfs_dir);
993 static const struct of_device_id altr_edac_device_of_match[] = {
994 #ifdef CONFIG_EDAC_ALTERA_L2C
995 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
997 #ifdef CONFIG_EDAC_ALTERA_OCRAM
998 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
1002 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
1005 * altr_edac_device_probe()
1006 * This is a generic EDAC device driver that will support
1007 * various Altera memory devices such as the L2 cache ECC and
1008 * OCRAM ECC as well as the memories for other peripherals.
1009 * Module specific initialization is done by passing the
1010 * function index in the device tree.
1012 static int altr_edac_device_probe(struct platform_device *pdev)
1014 struct edac_device_ctl_info *dci;
1015 struct altr_edac_device_dev *drvdata;
1018 struct device_node *np = pdev->dev.of_node;
1019 char *ecc_name = (char *)np->name;
1020 static int dev_instance;
1022 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
1023 edac_printk(KERN_ERR, EDAC_DEVICE,
1024 "Unable to open devm\n");
1028 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 edac_printk(KERN_ERR, EDAC_DEVICE,
1031 "Unable to get mem resource\n");
1036 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
1037 dev_name(&pdev->dev))) {
1038 edac_printk(KERN_ERR, EDAC_DEVICE,
1039 "%s:Error requesting mem region\n", ecc_name);
1044 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
1045 1, ecc_name, 1, 0, NULL, 0,
1049 edac_printk(KERN_ERR, EDAC_DEVICE,
1050 "%s: Unable to allocate EDAC device\n", ecc_name);
1055 drvdata = dci->pvt_info;
1056 dci->dev = &pdev->dev;
1057 platform_set_drvdata(pdev, dci);
1058 drvdata->edac_dev_name = ecc_name;
1060 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
1061 if (!drvdata->base) {
1066 /* Get driver specific data for this EDAC device */
1067 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
1069 /* Check specific dependencies for the module */
1070 if (drvdata->data->setup) {
1071 res = drvdata->data->setup(drvdata);
1076 drvdata->sb_irq = platform_get_irq(pdev, 0);
1077 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
1078 altr_edac_device_handler,
1079 0, dev_name(&pdev->dev), dci);
1083 drvdata->db_irq = platform_get_irq(pdev, 1);
1084 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
1085 altr_edac_device_handler,
1086 0, dev_name(&pdev->dev), dci);
1090 dci->mod_name = "Altera ECC Manager";
1091 dci->dev_name = drvdata->edac_dev_name;
1093 res = edac_device_add_device(dci);
1097 altr_create_edacdev_dbgfs(dci, drvdata->data);
1099 devres_close_group(&pdev->dev, NULL);
1104 edac_device_free_ctl_info(dci);
1106 devres_release_group(&pdev->dev, NULL);
1107 edac_printk(KERN_ERR, EDAC_DEVICE,
1108 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
1113 static int altr_edac_device_remove(struct platform_device *pdev)
1115 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
1116 struct altr_edac_device_dev *drvdata = dci->pvt_info;
1118 debugfs_remove_recursive(drvdata->debugfs_dir);
1119 edac_device_del_device(&pdev->dev);
1120 edac_device_free_ctl_info(dci);
1125 static struct platform_driver altr_edac_device_driver = {
1126 .probe = altr_edac_device_probe,
1127 .remove = altr_edac_device_remove,
1129 .name = "altr_edac_device",
1130 .of_match_table = altr_edac_device_of_match,
1133 module_platform_driver(altr_edac_device_driver);
1135 /******************* Arria10 Device ECC Shared Functions *****************/
1138 * Test for memory's ECC dependencies upon entry because platform specific
1139 * startup should have initialized the memory and enabled the ECC.
1140 * Can't turn on ECC here because accessing un-initialized memory will
1141 * cause CE/UE errors possibly causing an ABORT.
1143 static int __maybe_unused
1144 altr_check_ecc_deps(struct altr_edac_device_dev *device)
1146 void __iomem *base = device->base;
1147 const struct edac_device_prv_data *prv = device->data;
1149 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
1152 edac_printk(KERN_ERR, EDAC_DEVICE,
1153 "%s: No ECC present or ECC disabled.\n",
1154 device->edac_dev_name);
1158 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
1160 struct altr_edac_device_dev *dci = dev_id;
1161 void __iomem *base = dci->base;
1163 if (irq == dci->sb_irq) {
1164 writel(ALTR_A10_ECC_SERRPENA,
1165 base + ALTR_A10_ECC_INTSTAT_OFST);
1166 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1169 } else if (irq == dci->db_irq) {
1170 writel(ALTR_A10_ECC_DERRPENA,
1171 base + ALTR_A10_ECC_INTSTAT_OFST);
1172 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1173 if (dci->data->panic)
1174 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1184 /******************* Arria10 Memory Buffer Functions *********************/
1186 static inline int a10_get_irq_mask(struct device_node *np)
1189 const u32 *handle = of_get_property(np, "interrupts", NULL);
1193 irq = be32_to_cpup(handle);
1197 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
1199 u32 value = readl(ioaddr);
1202 writel(value, ioaddr);
1205 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
1207 u32 value = readl(ioaddr);
1210 writel(value, ioaddr);
1213 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
1215 u32 value = readl(ioaddr);
1217 return (value & bit_mask) ? 1 : 0;
1221 * This function uses the memory initialization block in the Arria10 ECC
1222 * controller to initialize/clear the entire memory data and ECC data.
1224 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
1226 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
1227 u32 init_mask, stat_mask, clear_mask;
1231 init_mask = ALTR_A10_ECC_INITB;
1232 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
1233 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
1235 init_mask = ALTR_A10_ECC_INITA;
1236 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
1237 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
1240 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
1242 if (ecc_test_bits(stat_mask,
1243 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
1250 /* Clear any pending ECC interrupts */
1251 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1256 static __init int __maybe_unused
1257 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1258 u32 ecc_ctrl_en_mask, bool dual_port)
1261 void __iomem *ecc_block_base;
1262 struct regmap *ecc_mgr_map;
1264 struct device_node *np_eccmgr;
1266 ecc_name = (char *)np->name;
1268 /* Get the ECC Manager - parent of the device EDACs */
1269 np_eccmgr = of_get_parent(np);
1270 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1271 "altr,sysmgr-syscon");
1272 of_node_put(np_eccmgr);
1273 if (IS_ERR(ecc_mgr_map)) {
1274 edac_printk(KERN_ERR, EDAC_DEVICE,
1275 "Unable to get syscon altr,sysmgr-syscon\n");
1279 /* Map the ECC Block */
1280 ecc_block_base = of_iomap(np, 0);
1281 if (!ecc_block_base) {
1282 edac_printk(KERN_ERR, EDAC_DEVICE,
1283 "Unable to map %s ECC block\n", ecc_name);
1288 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1289 writel(ALTR_A10_ECC_SERRINTEN,
1290 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1291 ecc_clear_bits(ecc_ctrl_en_mask,
1292 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1293 /* Ensure all writes complete */
1295 /* Use HW initialization block to initialize memory for ECC */
1296 ret = altr_init_memory_port(ecc_block_base, 0);
1298 edac_printk(KERN_ERR, EDAC_DEVICE,
1299 "ECC: cannot init %s PORTA memory\n", ecc_name);
1304 ret = altr_init_memory_port(ecc_block_base, 1);
1306 edac_printk(KERN_ERR, EDAC_DEVICE,
1307 "ECC: cannot init %s PORTB memory\n",
1313 /* Interrupt mode set to every SBERR */
1314 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1315 ALTR_A10_ECC_INTMODE);
1317 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1318 ALTR_A10_ECC_CTRL_OFST));
1319 writel(ALTR_A10_ECC_SERRINTEN,
1320 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1321 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1322 /* Ensure all writes complete */
1325 iounmap(ecc_block_base);
1329 static int socfpga_is_a10(void)
1331 return of_machine_is_compatible("altr,socfpga-arria10");
1334 static int validate_parent_available(struct device_node *np);
1335 static const struct of_device_id altr_edac_a10_device_of_match[];
1336 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1339 struct device_node *child, *np;
1341 if (!socfpga_is_a10())
1344 np = of_find_compatible_node(NULL, NULL,
1345 "altr,socfpga-a10-ecc-manager");
1347 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1351 for_each_child_of_node(np, child) {
1352 const struct of_device_id *pdev_id;
1353 const struct edac_device_prv_data *prv;
1355 if (!of_device_is_available(child))
1357 if (!of_device_is_compatible(child, compat))
1360 if (validate_parent_available(child))
1363 irq = a10_get_irq_mask(child);
1367 /* Get matching node and check for valid result */
1368 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1369 if (IS_ERR_OR_NULL(pdev_id))
1372 /* Validate private data pointer before dereferencing */
1373 prv = pdev_id->data;
1377 altr_init_a10_ecc_block(child, BIT(irq),
1378 prv->ecc_enable_mask, 0);
1385 /*********************** OCRAM EDAC Device Functions *********************/
1387 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1389 static void *ocram_alloc_mem(size_t size, void **other)
1391 struct device_node *np;
1392 struct gen_pool *gp;
1395 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1399 gp = of_gen_pool_get(np, "iram", 0);
1404 sram_addr = (void *)gen_pool_alloc(gp, size);
1408 memset(sram_addr, 0, size);
1409 /* Ensure data is written out */
1412 /* Remember this handle for freeing later */
1418 static void ocram_free_mem(void *p, size_t size, void *other)
1420 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1423 static const struct edac_device_prv_data ocramecc_data = {
1424 .setup = altr_check_ecc_deps,
1425 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1426 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1427 .alloc_mem = ocram_alloc_mem,
1428 .free_mem = ocram_free_mem,
1429 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1430 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1431 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1432 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1433 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1434 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1435 .inject_fops = &altr_edac_device_inject_fops,
1438 static const struct edac_device_prv_data a10_ocramecc_data = {
1439 .setup = altr_check_ecc_deps,
1440 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1441 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1442 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1443 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1444 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1445 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1446 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1447 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1448 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1449 .inject_fops = &altr_edac_a10_device_inject_fops,
1451 * OCRAM panic on uncorrectable error because sleep/resume
1452 * functions and FPGA contents are stored in OCRAM. Prefer
1453 * a kernel panic over executing/loading corrupted data.
1458 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1460 /********************* L2 Cache EDAC Device Functions ********************/
1462 #ifdef CONFIG_EDAC_ALTERA_L2C
1464 static void *l2_alloc_mem(size_t size, void **other)
1466 struct device *dev = *other;
1467 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1472 /* Make sure everything is written out */
1476 * Clean all cache levels up to LoC (includes L2)
1477 * This ensures the corrupted data is written into
1478 * L2 cache for readback test (which causes ECC error).
1485 static void l2_free_mem(void *p, size_t size, void *other)
1487 struct device *dev = other;
1494 * altr_l2_check_deps()
1495 * Test for L2 cache ECC dependencies upon entry because
1496 * platform specific startup should have initialized the L2
1497 * memory and enabled the ECC.
1498 * Bail if ECC is not enabled.
1499 * Note that L2 Cache Enable is forced at build time.
1501 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1503 void __iomem *base = device->base;
1504 const struct edac_device_prv_data *prv = device->data;
1506 if ((readl(base) & prv->ecc_enable_mask) ==
1507 prv->ecc_enable_mask)
1510 edac_printk(KERN_ERR, EDAC_DEVICE,
1511 "L2: No ECC present, or ECC disabled\n");
1515 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1517 struct altr_edac_device_dev *dci = dev_id;
1519 if (irq == dci->sb_irq) {
1520 regmap_write(dci->edac->ecc_mgr_map,
1521 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1522 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1523 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1526 } else if (irq == dci->db_irq) {
1527 regmap_write(dci->edac->ecc_mgr_map,
1528 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1529 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1530 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1531 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1541 static const struct edac_device_prv_data l2ecc_data = {
1542 .setup = altr_l2_check_deps,
1545 .alloc_mem = l2_alloc_mem,
1546 .free_mem = l2_free_mem,
1547 .ecc_enable_mask = ALTR_L2_ECC_EN,
1548 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1549 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1550 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1551 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1552 .inject_fops = &altr_edac_device_inject_fops,
1555 static const struct edac_device_prv_data a10_l2ecc_data = {
1556 .setup = altr_l2_check_deps,
1557 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1558 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1559 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1560 .alloc_mem = l2_alloc_mem,
1561 .free_mem = l2_free_mem,
1562 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1563 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1564 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1565 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1566 .ecc_irq_handler = altr_edac_a10_l2_irq,
1567 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1568 .inject_fops = &altr_edac_device_inject_fops,
1571 #endif /* CONFIG_EDAC_ALTERA_L2C */
1573 /********************* Ethernet Device Functions ********************/
1575 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1577 static const struct edac_device_prv_data a10_enetecc_data = {
1578 .setup = altr_check_ecc_deps,
1579 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1580 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1581 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1582 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1583 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1584 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1585 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1586 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1587 .inject_fops = &altr_edac_a10_device_inject_fops,
1590 static int __init socfpga_init_ethernet_ecc(void)
1592 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1595 early_initcall(socfpga_init_ethernet_ecc);
1597 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1599 /********************** NAND Device Functions **********************/
1601 #ifdef CONFIG_EDAC_ALTERA_NAND
1603 static const struct edac_device_prv_data a10_nandecc_data = {
1604 .setup = altr_check_ecc_deps,
1605 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1606 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1607 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1608 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1609 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1610 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1611 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1612 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1613 .inject_fops = &altr_edac_a10_device_inject_fops,
1616 static int __init socfpga_init_nand_ecc(void)
1618 return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1621 early_initcall(socfpga_init_nand_ecc);
1623 #endif /* CONFIG_EDAC_ALTERA_NAND */
1625 /********************** DMA Device Functions **********************/
1627 #ifdef CONFIG_EDAC_ALTERA_DMA
1629 static const struct edac_device_prv_data a10_dmaecc_data = {
1630 .setup = altr_check_ecc_deps,
1631 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1632 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1633 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1634 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1635 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1636 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1637 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1638 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1639 .inject_fops = &altr_edac_a10_device_inject_fops,
1642 static int __init socfpga_init_dma_ecc(void)
1644 return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1647 early_initcall(socfpga_init_dma_ecc);
1649 #endif /* CONFIG_EDAC_ALTERA_DMA */
1651 /********************** USB Device Functions **********************/
1653 #ifdef CONFIG_EDAC_ALTERA_USB
1655 static const struct edac_device_prv_data a10_usbecc_data = {
1656 .setup = altr_check_ecc_deps,
1657 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1658 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1659 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1660 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1661 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1662 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1663 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1664 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1665 .inject_fops = &altr_edac_a10_device_inject_fops,
1668 static int __init socfpga_init_usb_ecc(void)
1670 return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1673 early_initcall(socfpga_init_usb_ecc);
1675 #endif /* CONFIG_EDAC_ALTERA_USB */
1677 /********************** QSPI Device Functions **********************/
1679 #ifdef CONFIG_EDAC_ALTERA_QSPI
1681 static const struct edac_device_prv_data a10_qspiecc_data = {
1682 .setup = altr_check_ecc_deps,
1683 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1684 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1685 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1686 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1687 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1688 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1689 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1690 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1691 .inject_fops = &altr_edac_a10_device_inject_fops,
1694 static int __init socfpga_init_qspi_ecc(void)
1696 return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1699 early_initcall(socfpga_init_qspi_ecc);
1701 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1703 /********************* SDMMC Device Functions **********************/
1705 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1707 static const struct edac_device_prv_data a10_sdmmceccb_data;
1708 static int altr_portb_setup(struct altr_edac_device_dev *device)
1710 struct edac_device_ctl_info *dci;
1711 struct altr_edac_device_dev *altdev;
1712 char *ecc_name = "sdmmcb-ecc";
1714 struct device_node *np;
1715 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1717 rc = altr_check_ecc_deps(device);
1721 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1723 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1727 /* Create the PortB EDAC device */
1728 edac_idx = edac_device_alloc_index();
1729 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1730 ecc_name, 1, 0, NULL, 0, edac_idx);
1732 edac_printk(KERN_ERR, EDAC_DEVICE,
1733 "%s: Unable to allocate PortB EDAC device\n",
1738 /* Initialize the PortB EDAC device structure from PortA structure */
1739 altdev = dci->pvt_info;
1742 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1745 /* Update PortB specific values */
1746 altdev->edac_dev_name = ecc_name;
1747 altdev->edac_idx = edac_idx;
1748 altdev->edac_dev = dci;
1750 dci->dev = &altdev->ddev;
1751 dci->ctl_name = "Altera ECC Manager";
1752 dci->mod_name = ecc_name;
1753 dci->dev_name = ecc_name;
1755 /* Update the IRQs for PortB */
1756 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1757 if (!altdev->sb_irq) {
1758 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1760 goto err_release_group_1;
1762 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1763 prv->ecc_irq_handler,
1764 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1767 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1768 goto err_release_group_1;
1771 altdev->db_irq = irq_of_parse_and_map(np, 3);
1772 if (!altdev->db_irq) {
1773 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1775 goto err_release_group_1;
1777 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1778 prv->ecc_irq_handler,
1779 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1782 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1783 goto err_release_group_1;
1786 rc = edac_device_add_device(dci);
1788 edac_printk(KERN_ERR, EDAC_DEVICE,
1789 "edac_device_add_device portB failed\n");
1791 goto err_release_group_1;
1793 altr_create_edacdev_dbgfs(dci, prv);
1795 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1797 devres_remove_group(&altdev->ddev, altr_portb_setup);
1801 err_release_group_1:
1802 edac_device_free_ctl_info(dci);
1803 devres_release_group(&altdev->ddev, altr_portb_setup);
1804 edac_printk(KERN_ERR, EDAC_DEVICE,
1805 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1809 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1811 struct altr_edac_device_dev *ad = dev_id;
1812 void __iomem *base = ad->base;
1813 const struct edac_device_prv_data *priv = ad->data;
1815 if (irq == ad->sb_irq) {
1816 writel(priv->ce_clear_mask,
1817 base + ALTR_A10_ECC_INTSTAT_OFST);
1818 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1820 } else if (irq == ad->db_irq) {
1821 writel(priv->ue_clear_mask,
1822 base + ALTR_A10_ECC_INTSTAT_OFST);
1823 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1827 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1832 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1833 .setup = altr_portb_setup,
1834 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1835 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1836 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1837 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1838 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1839 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1840 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1841 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1842 .inject_fops = &altr_edac_a10_device_inject_fops,
1845 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1846 .setup = altr_portb_setup,
1847 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1848 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1849 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1850 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1851 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1852 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1853 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1854 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1855 .inject_fops = &altr_edac_a10_device_inject_fops,
1858 static int __init socfpga_init_sdmmc_ecc(void)
1861 struct device_node *child;
1863 if (!socfpga_is_a10())
1866 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1868 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1872 if (!of_device_is_available(child))
1875 if (validate_parent_available(child))
1878 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1879 a10_sdmmcecca_data.ecc_enable_mask, 1);
1885 early_initcall(socfpga_init_sdmmc_ecc);
1887 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1889 /********************* Arria10 EDAC Device Functions *************************/
1890 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1891 #ifdef CONFIG_EDAC_ALTERA_L2C
1892 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1894 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1895 { .compatible = "altr,socfpga-a10-ocram-ecc",
1896 .data = &a10_ocramecc_data },
1898 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1899 { .compatible = "altr,socfpga-eth-mac-ecc",
1900 .data = &a10_enetecc_data },
1902 #ifdef CONFIG_EDAC_ALTERA_NAND
1903 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1905 #ifdef CONFIG_EDAC_ALTERA_DMA
1906 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1908 #ifdef CONFIG_EDAC_ALTERA_USB
1909 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1911 #ifdef CONFIG_EDAC_ALTERA_QSPI
1912 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1914 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1915 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1919 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1922 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1923 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1924 * manager manages the IRQs and the children.
1925 * Based on xgene_edac.c peripheral code.
1928 static ssize_t altr_edac_a10_device_trig(struct file *file,
1929 const char __user *user_buf,
1930 size_t count, loff_t *ppos)
1932 struct edac_device_ctl_info *edac_dci = file->private_data;
1933 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1934 const struct edac_device_prv_data *priv = drvdata->data;
1935 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1936 unsigned long flags;
1939 if (!user_buf || get_user(trig_type, user_buf))
1942 local_irq_save(flags);
1943 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1944 writel(priv->ue_set_mask, set_addr);
1946 writel(priv->ce_set_mask, set_addr);
1947 /* Ensure the interrupt test bits are set */
1949 local_irq_restore(flags);
1954 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1956 int dberr, bit, sm_offset, irq_status;
1957 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1958 struct irq_chip *chip = irq_desc_get_chip(desc);
1959 int irq = irq_desc_get_irq(desc);
1961 dberr = (irq == edac->db_irq) ? 1 : 0;
1962 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1963 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1965 chained_irq_enter(chip, desc);
1967 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1969 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1970 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1972 generic_handle_irq(irq);
1975 chained_irq_exit(chip, desc);
1978 static int validate_parent_available(struct device_node *np)
1980 struct device_node *parent;
1983 /* Ensure parent device is enabled if parent node exists */
1984 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1985 if (parent && !of_device_is_available(parent))
1988 of_node_put(parent);
1992 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1993 struct device_node *np)
1995 struct edac_device_ctl_info *dci;
1996 struct altr_edac_device_dev *altdev;
1997 char *ecc_name = (char *)np->name;
1998 struct resource res;
2001 const struct edac_device_prv_data *prv;
2002 /* Get matching node and check for valid result */
2003 const struct of_device_id *pdev_id =
2004 of_match_node(altr_edac_a10_device_of_match, np);
2005 if (IS_ERR_OR_NULL(pdev_id))
2008 /* Get driver specific data for this EDAC device */
2009 prv = pdev_id->data;
2010 if (IS_ERR_OR_NULL(prv))
2013 if (validate_parent_available(np))
2016 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
2019 rc = of_address_to_resource(np, 0, &res);
2021 edac_printk(KERN_ERR, EDAC_DEVICE,
2022 "%s: no resource address\n", ecc_name);
2023 goto err_release_group;
2026 edac_idx = edac_device_alloc_index();
2027 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
2028 1, ecc_name, 1, 0, NULL, 0,
2032 edac_printk(KERN_ERR, EDAC_DEVICE,
2033 "%s: Unable to allocate EDAC device\n", ecc_name);
2035 goto err_release_group;
2038 altdev = dci->pvt_info;
2039 dci->dev = edac->dev;
2040 altdev->edac_dev_name = ecc_name;
2041 altdev->edac_idx = edac_idx;
2042 altdev->edac = edac;
2043 altdev->edac_dev = dci;
2045 altdev->ddev = *edac->dev;
2046 dci->dev = &altdev->ddev;
2047 dci->ctl_name = "Altera ECC Manager";
2048 dci->mod_name = ecc_name;
2049 dci->dev_name = ecc_name;
2051 altdev->base = devm_ioremap_resource(edac->dev, &res);
2052 if (IS_ERR(altdev->base)) {
2053 rc = PTR_ERR(altdev->base);
2054 goto err_release_group1;
2057 /* Check specific dependencies for the module */
2058 if (altdev->data->setup) {
2059 rc = altdev->data->setup(altdev);
2061 goto err_release_group1;
2064 altdev->sb_irq = irq_of_parse_and_map(np, 0);
2065 if (!altdev->sb_irq) {
2066 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
2068 goto err_release_group1;
2070 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
2071 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2074 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
2075 goto err_release_group1;
2078 altdev->db_irq = irq_of_parse_and_map(np, 1);
2079 if (!altdev->db_irq) {
2080 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
2082 goto err_release_group1;
2084 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
2085 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2088 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
2089 goto err_release_group1;
2092 rc = edac_device_add_device(dci);
2094 dev_err(edac->dev, "edac_device_add_device failed\n");
2096 goto err_release_group1;
2099 altr_create_edacdev_dbgfs(dci, prv);
2101 list_add(&altdev->next, &edac->a10_ecc_devices);
2103 devres_remove_group(edac->dev, altr_edac_a10_device_add);
2108 edac_device_free_ctl_info(dci);
2110 devres_release_group(edac->dev, NULL);
2111 edac_printk(KERN_ERR, EDAC_DEVICE,
2112 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2117 static void a10_eccmgr_irq_mask(struct irq_data *d)
2119 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2121 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2125 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2127 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2129 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2133 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2134 irq_hw_number_t hwirq)
2136 struct altr_arria10_edac *edac = d->host_data;
2138 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2139 irq_set_chip_data(irq, edac);
2140 irq_set_noprobe(irq);
2145 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2146 .map = a10_eccmgr_irqdomain_map,
2147 .xlate = irq_domain_xlate_twocell,
2150 static int altr_edac_a10_probe(struct platform_device *pdev)
2152 struct altr_arria10_edac *edac;
2153 struct device_node *child;
2155 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2159 edac->dev = &pdev->dev;
2160 platform_set_drvdata(pdev, edac);
2161 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2163 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2164 "altr,sysmgr-syscon");
2165 if (IS_ERR(edac->ecc_mgr_map)) {
2166 edac_printk(KERN_ERR, EDAC_DEVICE,
2167 "Unable to get syscon altr,sysmgr-syscon\n");
2168 return PTR_ERR(edac->ecc_mgr_map);
2171 edac->irq_chip.name = pdev->dev.of_node->name;
2172 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2173 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2174 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2175 &a10_eccmgr_ic_ops, edac);
2176 if (!edac->domain) {
2177 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2181 edac->sb_irq = platform_get_irq(pdev, 0);
2182 if (edac->sb_irq < 0) {
2183 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2184 return edac->sb_irq;
2187 irq_set_chained_handler_and_data(edac->sb_irq,
2188 altr_edac_a10_irq_handler,
2191 edac->db_irq = platform_get_irq(pdev, 1);
2192 if (edac->db_irq < 0) {
2193 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2194 return edac->db_irq;
2196 irq_set_chained_handler_and_data(edac->db_irq,
2197 altr_edac_a10_irq_handler,
2200 for_each_child_of_node(pdev->dev.of_node, child) {
2201 if (!of_device_is_available(child))
2204 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2205 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2206 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2207 of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2208 of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2209 of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2210 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2211 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2213 altr_edac_a10_device_add(edac, child);
2215 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2216 of_platform_populate(pdev->dev.of_node,
2217 altr_sdram_ctrl_of_match,
2224 static const struct of_device_id altr_edac_a10_of_match[] = {
2225 { .compatible = "altr,socfpga-a10-ecc-manager" },
2228 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2230 static struct platform_driver altr_edac_a10_driver = {
2231 .probe = altr_edac_a10_probe,
2233 .name = "socfpga_a10_ecc_manager",
2234 .of_match_table = altr_edac_a10_of_match,
2237 module_platform_driver(altr_edac_a10_driver);
2239 /************** Stratix 10 EDAC Device Controller Functions> ************/
2241 #define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m)
2244 * The double bit error is handled through SError which is fatal. This is
2245 * called as a panic notifier to printout ECC error info as part of the panic.
2247 static int s10_edac_dberr_handler(struct notifier_block *this,
2248 unsigned long event, void *ptr)
2250 struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier);
2251 int err_addr, dberror;
2253 s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2255 /* Remember the UE Errors for a reboot */
2256 s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror);
2257 if (dberror & S10_DDR0_IRQ_MASK) {
2258 s10_protected_reg_read(edac, S10_DERRADDR_OFST, &err_addr);
2259 /* Remember the UE Error address */
2260 s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST,
2262 edac_printk(KERN_ERR, EDAC_MC,
2263 "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
2270 static void altr_edac_s10_irq_handler(struct irq_desc *desc)
2272 struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc);
2273 struct irq_chip *chip = irq_desc_get_chip(desc);
2274 int irq = irq_desc_get_irq(desc);
2275 int bit, sm_offset, irq_status;
2277 sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
2279 chained_irq_enter(chip, desc);
2281 s10_protected_reg_read(NULL, sm_offset, &irq_status);
2283 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
2284 irq = irq_linear_revmap(edac->domain, bit);
2286 generic_handle_irq(irq);
2289 chained_irq_exit(chip, desc);
2292 static void s10_eccmgr_irq_mask(struct irq_data *d)
2294 struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
2296 s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_SET_OFST,
2300 static void s10_eccmgr_irq_unmask(struct irq_data *d)
2302 struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
2304 s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
2308 static int s10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2309 irq_hw_number_t hwirq)
2311 struct altr_stratix10_edac *edac = d->host_data;
2313 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2314 irq_set_chip_data(irq, edac);
2315 irq_set_noprobe(irq);
2320 static const struct irq_domain_ops s10_eccmgr_ic_ops = {
2321 .map = s10_eccmgr_irqdomain_map,
2322 .xlate = irq_domain_xlate_twocell,
2325 static int altr_edac_s10_probe(struct platform_device *pdev)
2327 struct altr_stratix10_edac *edac;
2328 struct device_node *child;
2329 int dberror, err_addr;
2331 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2335 edac->dev = &pdev->dev;
2336 platform_set_drvdata(pdev, edac);
2337 INIT_LIST_HEAD(&edac->s10_ecc_devices);
2339 edac->irq_chip.name = pdev->dev.of_node->name;
2340 edac->irq_chip.irq_mask = s10_eccmgr_irq_mask;
2341 edac->irq_chip.irq_unmask = s10_eccmgr_irq_unmask;
2342 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2343 &s10_eccmgr_ic_ops, edac);
2344 if (!edac->domain) {
2345 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2349 edac->sb_irq = platform_get_irq(pdev, 0);
2350 if (edac->sb_irq < 0) {
2351 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2352 return edac->sb_irq;
2355 irq_set_chained_handler_and_data(edac->sb_irq,
2356 altr_edac_s10_irq_handler,
2359 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2360 atomic_notifier_chain_register(&panic_notifier_list,
2361 &edac->panic_notifier);
2363 /* Printout a message if uncorrectable error previously. */
2364 s10_protected_reg_read(edac, S10_SYSMGR_UE_VAL_OFST, &dberror);
2366 s10_protected_reg_read(edac, S10_SYSMGR_UE_ADDR_OFST,
2368 edac_printk(KERN_ERR, EDAC_DEVICE,
2369 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2371 /* Reset the sticky registers */
2372 s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, 0);
2373 s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, 0);
2376 for_each_child_of_node(pdev->dev.of_node, child) {
2377 if (!of_device_is_available(child))
2380 if (of_device_is_compatible(child, "altr,sdram-edac-s10"))
2381 of_platform_populate(pdev->dev.of_node,
2382 altr_sdram_ctrl_of_match,
2389 static const struct of_device_id altr_edac_s10_of_match[] = {
2390 { .compatible = "altr,socfpga-s10-ecc-manager" },
2393 MODULE_DEVICE_TABLE(of, altr_edac_s10_of_match);
2395 static struct platform_driver altr_edac_s10_driver = {
2396 .probe = altr_edac_s10_probe,
2398 .name = "socfpga_s10_ecc_manager",
2399 .of_match_table = altr_edac_s10_of_match,
2402 module_platform_driver(altr_edac_s10_driver);
2404 MODULE_LICENSE("GPL v2");
2405 MODULE_AUTHOR("Thor Thayer");
2406 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");