1 // SPDX-License-Identifier: GPL-2.0-only
3 * GHES/EDAC Linux driver
5 * Copyright (c) 2013 by Mauro Carvalho Chehab
7 * Red Hat Inc. http://www.redhat.com
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <acpi/ghes.h>
13 #include <linux/edac.h>
14 #include <linux/dmi.h>
15 #include "edac_module.h"
16 #include <ras/ras_event.h>
18 struct ghes_edac_pvt {
19 struct list_head list;
21 struct mem_ctl_info *mci;
23 /* Buffers for the error handling routine */
24 char detail_location[240];
25 char other_detail[160];
29 static atomic_t ghes_init = ATOMIC_INIT(0);
30 static struct ghes_edac_pvt *ghes_pvt;
33 * Sync with other, potentially concurrent callers of
34 * ghes_edac_report_mem_error(). We don't know what the
35 * "inventive" firmware would do.
37 static DEFINE_SPINLOCK(ghes_lock);
39 /* "ghes_edac.force_load=1" skips the platform check */
40 static bool __read_mostly force_load;
41 module_param(force_load, bool, 0);
43 /* Memory Device - Type 17 of SMBIOS spec */
44 struct memdev_dmi_entry {
48 u16 phys_mem_array_handle;
49 u16 mem_err_info_handle;
66 u16 conf_mem_clk_speed;
67 } __attribute__((__packed__));
69 struct ghes_edac_dimm_fill {
70 struct mem_ctl_info *mci;
74 static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
78 if (dh->type == DMI_ENTRY_MEM_DEVICE)
82 static int get_dimm_smbios_index(u16 handle)
84 struct mem_ctl_info *mci = ghes_pvt->mci;
87 for (i = 0; i < mci->tot_dimms; i++) {
88 if (mci->dimms[i]->smbios_handle == handle)
94 static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
96 struct ghes_edac_dimm_fill *dimm_fill = arg;
97 struct mem_ctl_info *mci = dimm_fill->mci;
99 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
100 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
101 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
103 dimm_fill->count, 0, 0);
104 u16 rdr_mask = BIT(7) | BIT(13);
106 if (entry->size == 0xffff) {
107 pr_info("Can't get DIMM%i size\n",
109 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
110 } else if (entry->size == 0x7fff) {
111 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
113 if (entry->size & BIT(15))
114 dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
116 dimm->nr_pages = MiB_TO_PAGES(entry->size);
119 switch (entry->memory_type) {
121 if (entry->type_detail & BIT(13))
122 dimm->mtype = MEM_RDDR;
124 dimm->mtype = MEM_DDR;
127 if (entry->type_detail & BIT(13))
128 dimm->mtype = MEM_RDDR2;
130 dimm->mtype = MEM_DDR2;
133 dimm->mtype = MEM_FB_DDR2;
136 if (entry->type_detail & BIT(12))
137 dimm->mtype = MEM_NVDIMM;
138 else if (entry->type_detail & BIT(13))
139 dimm->mtype = MEM_RDDR3;
141 dimm->mtype = MEM_DDR3;
144 if (entry->type_detail & BIT(12))
145 dimm->mtype = MEM_NVDIMM;
146 else if (entry->type_detail & BIT(13))
147 dimm->mtype = MEM_RDDR4;
149 dimm->mtype = MEM_DDR4;
152 if (entry->type_detail & BIT(6))
153 dimm->mtype = MEM_RMBS;
154 else if ((entry->type_detail & rdr_mask) == rdr_mask)
155 dimm->mtype = MEM_RDR;
156 else if (entry->type_detail & BIT(7))
157 dimm->mtype = MEM_SDR;
158 else if (entry->type_detail & BIT(9))
159 dimm->mtype = MEM_EDO;
161 dimm->mtype = MEM_UNKNOWN;
165 * Actually, we can only detect if the memory has bits for
168 if (entry->total_width == entry->data_width)
169 dimm->edac_mode = EDAC_NONE;
171 dimm->edac_mode = EDAC_SECDED;
173 dimm->dtype = DEV_UNKNOWN;
174 dimm->grain = 128; /* Likely, worse case */
177 * FIXME: It shouldn't be hard to also fill the DIMM labels
180 if (dimm->nr_pages) {
181 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
182 dimm_fill->count, edac_mem_types[dimm->mtype],
183 PAGES_TO_MiB(dimm->nr_pages),
184 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
185 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
186 entry->memory_type, entry->type_detail,
187 entry->total_width, entry->data_width);
190 dimm->smbios_handle = entry->handle;
196 void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
198 enum hw_event_mc_err_type type;
199 struct edac_raw_error_desc *e;
200 struct mem_ctl_info *mci;
201 struct ghes_edac_pvt *pvt = ghes_pvt;
210 * We can do the locking below because GHES defers error processing
211 * from NMI to IRQ context. Whenever that changes, we'd at least
214 if (WARN_ON_ONCE(in_nmi()))
217 spin_lock_irqsave(&ghes_lock, flags);
220 e = &mci->error_desc;
222 /* Cleans the error report buffer */
223 memset(e, 0, sizeof (*e));
225 strcpy(e->label, "unknown label");
227 e->other_detail = pvt->other_detail;
231 *pvt->other_detail = '\0';
235 case GHES_SEV_CORRECTED:
236 type = HW_EVENT_ERR_CORRECTED;
238 case GHES_SEV_RECOVERABLE:
239 type = HW_EVENT_ERR_UNCORRECTED;
242 type = HW_EVENT_ERR_FATAL;
246 type = HW_EVENT_ERR_INFO;
249 edac_dbg(1, "error validation_bits: 0x%08llx\n",
250 (long long)mem_err->validation_bits);
252 /* Error type, mapped on e->msg */
253 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
255 switch (mem_err->error_type) {
257 p += sprintf(p, "Unknown");
260 p += sprintf(p, "No error");
263 p += sprintf(p, "Single-bit ECC");
266 p += sprintf(p, "Multi-bit ECC");
269 p += sprintf(p, "Single-symbol ChipKill ECC");
272 p += sprintf(p, "Multi-symbol ChipKill ECC");
275 p += sprintf(p, "Master abort");
278 p += sprintf(p, "Target abort");
281 p += sprintf(p, "Parity Error");
284 p += sprintf(p, "Watchdog timeout");
287 p += sprintf(p, "Invalid address");
290 p += sprintf(p, "Mirror Broken");
293 p += sprintf(p, "Memory Sparing");
296 p += sprintf(p, "Scrub corrected error");
299 p += sprintf(p, "Scrub uncorrected error");
302 p += sprintf(p, "Physical Memory Map-out event");
305 p += sprintf(p, "reserved error (%d)",
306 mem_err->error_type);
309 strcpy(pvt->msg, "unknown error");
313 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
314 e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
315 e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
319 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
320 e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
322 /* Memory error location, mapped on e->location */
324 if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
325 p += sprintf(p, "node:%d ", mem_err->node);
326 if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
327 p += sprintf(p, "card:%d ", mem_err->card);
328 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
329 p += sprintf(p, "module:%d ", mem_err->module);
330 if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
331 p += sprintf(p, "rank:%d ", mem_err->rank);
332 if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
333 p += sprintf(p, "bank:%d ", mem_err->bank);
334 if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
335 p += sprintf(p, "row:%d ", mem_err->row);
336 if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
337 p += sprintf(p, "col:%d ", mem_err->column);
338 if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
339 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
340 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
341 const char *bank = NULL, *device = NULL;
344 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
345 if (bank != NULL && device != NULL)
346 p += sprintf(p, "DIMM location:%s %s ", bank, device);
348 p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
349 mem_err->mem_dev_handle);
351 index = get_dimm_smbios_index(mem_err->mem_dev_handle);
353 e->top_layer = index;
354 e->enable_per_layer_report = true;
361 /* All other fields are mapped on e->other_detail */
362 p = pvt->other_detail;
363 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
364 u64 status = mem_err->error_status;
366 p += sprintf(p, "status(0x%016llx): ", (long long)status);
367 switch ((status >> 8) & 0xff) {
369 p += sprintf(p, "Error detected internal to the component ");
372 p += sprintf(p, "Error detected in the bus ");
375 p += sprintf(p, "Storage error in DRAM memory ");
378 p += sprintf(p, "Storage error in TLB ");
381 p += sprintf(p, "Storage error in cache ");
384 p += sprintf(p, "Error in one or more functional units ");
387 p += sprintf(p, "component failed self test ");
390 p += sprintf(p, "Overflow or undervalue of internal queue ");
393 p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
396 p += sprintf(p, "Improper access error ");
399 p += sprintf(p, "Access to a memory address which is not mapped to any component ");
402 p += sprintf(p, "Loss of Lockstep ");
405 p += sprintf(p, "Response not associated with a request ");
408 p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
411 p += sprintf(p, "Detection of a PATH_ERROR ");
414 p += sprintf(p, "Bus operation timeout ");
417 p += sprintf(p, "A read was issued to data that has been poisoned ");
420 p += sprintf(p, "reserved ");
424 if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
425 p += sprintf(p, "requestorID: 0x%016llx ",
426 (long long)mem_err->requestor_id);
427 if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
428 p += sprintf(p, "responderID: 0x%016llx ",
429 (long long)mem_err->responder_id);
430 if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
431 p += sprintf(p, "targetID: 0x%016llx ",
432 (long long)mem_err->responder_id);
433 if (p > pvt->other_detail)
436 /* Generate the trace event */
437 grain_bits = fls_long(e->grain);
438 snprintf(pvt->detail_location, sizeof(pvt->detail_location),
439 "APEI location: %s %s", e->location, e->other_detail);
440 trace_mc_event(type, e->msg, e->label, e->error_count,
441 mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
442 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
443 grain_bits, e->syndrome, pvt->detail_location);
445 edac_raw_mc_handle_error(type, mci, e);
446 spin_unlock_irqrestore(&ghes_lock, flags);
450 * Known systems that are safe to enable this module.
452 static struct acpi_platform_list plat_list[] = {
453 {"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
457 int ghes_edac_register(struct ghes *ghes, struct device *dev)
460 int rc, num_dimm = 0;
461 struct mem_ctl_info *mci;
462 struct edac_mc_layer layers[1];
463 struct ghes_edac_dimm_fill dimm_fill;
466 if (IS_ENABLED(CONFIG_X86)) {
467 /* Check if safe to enable on this system */
468 idx = acpi_match_platform_list(plat_list);
469 if (!force_load && idx < 0)
476 * We have only one logical memory controller to which all DIMMs belong.
478 if (atomic_inc_return(&ghes_init) > 1)
481 /* Get the number of DIMMs */
482 dmi_walk(ghes_edac_count_dimms, &num_dimm);
484 /* Check if we've got a bogus BIOS */
490 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
491 layers[0].size = num_dimm;
492 layers[0].is_virt_csrow = true;
494 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
496 pr_info("Can't allocate memory for EDAC data\n");
500 ghes_pvt = mci->pvt_info;
501 ghes_pvt->ghes = ghes;
505 mci->mtype_cap = MEM_FLAG_EMPTY;
506 mci->edac_ctl_cap = EDAC_FLAG_NONE;
507 mci->edac_cap = EDAC_FLAG_NONE;
508 mci->mod_name = "ghes_edac.c";
509 mci->ctl_name = "ghes_edac";
510 mci->dev_name = "ghes";
513 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
514 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
515 pr_info("work on such system. Use this driver with caution\n");
516 } else if (idx < 0) {
517 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
518 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
519 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
520 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
521 pr_info("to correct its BIOS.\n");
522 pr_info("This system has %d DIMM sockets.\n", num_dimm);
528 dmi_walk(ghes_edac_dmidecode, &dimm_fill);
530 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
531 mci->n_layers, 0, 0, 0);
535 dimm->mtype = MEM_UNKNOWN;
536 dimm->dtype = DEV_UNKNOWN;
537 dimm->edac_mode = EDAC_SECDED;
540 rc = edac_mc_add_mc(mci);
542 pr_info("Can't register at EDAC core\n");
549 void ghes_edac_unregister(struct ghes *ghes)
551 struct mem_ctl_info *mci;
557 edac_mc_del_mc(mci->pdev);