drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <linux/mod_devicetable.h>
  25 #include <asm/cpu_device_id.h>
  26 #include <asm/intel-family.h>
  27 #include <asm/processor.h>
  28 #include <asm/mce.h>
  29
  30 #include "edac_module.h"
  31
  32 /* Static vars */
  33 static LIST_HEAD(sbridge_edac_list);
  34
  35 /*
  36  * Alter this version for the module when modifications are made
  37  */
  38 #define SBRIDGE_REVISION    " Ver: 1.1.1 "
  39 #define EDAC_MOD_STR      "sbridge_edac"
  40
  41 /*
  42  * Debug macros
  43  */
  44 #define sbridge_printk(level, fmt, arg...)                      \
  45         edac_printk(level, "sbridge", fmt, ##arg)
  46
  47 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  48         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  49
  50 /*
  51  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  52  */
  53 #define GET_BITFIELD(v, lo, hi) \
  54         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  55
  56 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  57 static const u32 sbridge_dram_rule[] = {
  58         0x80, 0x88, 0x90, 0x98, 0xa0,
  59         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  60 };
  61
  62 static const u32 ibridge_dram_rule[] = {
  63         0x60, 0x68, 0x70, 0x78, 0x80,
  64         0x88, 0x90, 0x98, 0xa0, 0xa8,
  65         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  66         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  67 };
  68
  69 static const u32 knl_dram_rule[] = {
  70         0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
  71         0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
  72         0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
  73         0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
  74         0x100, 0x108, 0x110, 0x118,   /* 20-23 */
  75 };
  76
  77 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
  78 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
  79
  80 static char *show_dram_attr(u32 attr)
  81 {
  82         switch (attr) {
  83                 case 0:
  84                         return "DRAM";
  85                 case 1:
  86                         return "MMCFG";
  87                 case 2:
  88                         return "NXM";
  89                 default:
  90                         return "unknown";
  91         }
  92 }
  93
  94 static const u32 sbridge_interleave_list[] = {
  95         0x84, 0x8c, 0x94, 0x9c, 0xa4,
  96         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
  97 };
  98
  99 static const u32 ibridge_interleave_list[] = {
 100         0x64, 0x6c, 0x74, 0x7c, 0x84,
 101         0x8c, 0x94, 0x9c, 0xa4, 0xac,
 102         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
 103         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
 104 };
 105
 106 static const u32 knl_interleave_list[] = {
 107         0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
 108         0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
 109         0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
 110         0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
 111         0x104, 0x10c, 0x114, 0x11c,   /* 20-23 */
 112 };
 113
 114 struct interleave_pkg {
 115         unsigned char start;
 116         unsigned char end;
 117 };
 118
 119 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 120         { 0, 2 },
 121         { 3, 5 },
 122         { 8, 10 },
 123         { 11, 13 },
 124         { 16, 18 },
 125         { 19, 21 },
 126         { 24, 26 },
 127         { 27, 29 },
 128 };
 129
 130 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 131         { 0, 3 },
 132         { 4, 7 },
 133         { 8, 11 },
 134         { 12, 15 },
 135         { 16, 19 },
 136         { 20, 23 },
 137         { 24, 27 },
 138         { 28, 31 },
 139 };
 140
 141 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 142                           int interleave)
 143 {
 144         return GET_BITFIELD(reg, table[interleave].start,
 145                             table[interleave].end);
 146 }
 147
 148 /* Devices 12 Function 7 */
 149
 150 #define TOLM            0x80
 151 #define TOHM            0x84
 152 #define HASWELL_TOLM    0xd0
 153 #define HASWELL_TOHM_0  0xd4
 154 #define HASWELL_TOHM_1  0xd8
 155 #define KNL_TOLM        0xd0
 156 #define KNL_TOHM_0      0xd4
 157 #define KNL_TOHM_1      0xd8
 158
 159 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 160 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 161
 162 /* Device 13 Function 6 */
 163
 164 #define SAD_TARGET      0xf0
 165
 166 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 167
 168 #define SOURCE_ID_KNL(reg)      GET_BITFIELD(reg, 12, 14)
 169
 170 #define SAD_CONTROL     0xf4
 171
 172 /* Device 14 function 0 */
 173
 174 static const u32 tad_dram_rule[] = {
 175         0x40, 0x44, 0x48, 0x4c,
 176         0x50, 0x54, 0x58, 0x5c,
 177         0x60, 0x64, 0x68, 0x6c,
 178 };
 179 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 180
 181 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 182 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 183 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 184 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 185 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 186 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 187 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 188
 189 /* Device 15, function 0 */
 190
 191 #define MCMTR                   0x7c
 192 #define KNL_MCMTR               0x624
 193
 194 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 195 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 196 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 197
 198 /* Device 15, function 1 */
 199
 200 #define RASENABLES              0xac
 201 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 202
 203 /* Device 15, functions 2-5 */
 204
 205 static const int mtr_regs[] = {
 206         0x80, 0x84, 0x88,
 207 };
 208
 209 static const int knl_mtr_reg = 0xb60;
 210
 211 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 212 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 213 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 214 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 215 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 216
 217 static const u32 tad_ch_nilv_offset[] = {
 218         0x90, 0x94, 0x98, 0x9c,
 219         0xa0, 0xa4, 0xa8, 0xac,
 220         0xb0, 0xb4, 0xb8, 0xbc,
 221 };
 222 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 223 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 224
 225 static const u32 rir_way_limit[] = {
 226         0x108, 0x10c, 0x110, 0x114, 0x118,
 227 };
 228 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 229
 230 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 231 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 232
 233 #define MAX_RIR_WAY     8
 234
 235 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 236         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 237         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 238         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 239         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 240         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 241 };
 242
 243 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
 244         GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
 245
 246 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
 247         GET_BITFIELD(reg,  2, 15) : GET_BITFIELD(reg,  2, 14))
 248
 249 /* Device 16, functions 2-7 */
 250
 251 /*
 252  * FIXME: Implement the error count reads directly
 253  */
 254
 255 static const u32 correrrcnt[] = {
 256         0x104, 0x108, 0x10c, 0x110,
 257 };
 258
 259 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 260 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 261 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 262 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 263
 264 static const u32 correrrthrsld[] = {
 265         0x11c, 0x120, 0x124, 0x128,
 266 };
 267
 268 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 269 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 270
 271
 272 /* Device 17, function 0 */
 273
 274 #define SB_RANK_CFG_A           0x0328
 275
 276 #define IB_RANK_CFG_A           0x0320
 277
 278 /*
 279  * sbridge structs
 280  */
 281
 282 #define NUM_CHANNELS            8       /* 2MC per socket, four chan per MC */
 283 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 284 #define KNL_MAX_CHAS            38      /* KNL max num. of Cache Home Agents */
 285 #define KNL_MAX_CHANNELS        6       /* KNL max num. of PCI channels */
 286 #define KNL_MAX_EDCS            8       /* Embedded DRAM controllers */
 287 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 288
 289 enum type {
 290         SANDY_BRIDGE,
 291         IVY_BRIDGE,
 292         HASWELL,
 293         BROADWELL,
 294         KNIGHTS_LANDING,
 295 };
 296
 297 struct sbridge_pvt;
 298 struct sbridge_info {
 299         enum type       type;
 300         u32             mcmtr;
 301         u32             rankcfgr;
 302         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 303         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 304         u64             (*rir_limit)(u32 reg);
 305         u64             (*sad_limit)(u32 reg);
 306         u32             (*interleave_mode)(u32 reg);
 307         char*           (*show_interleave_mode)(u32 reg);
 308         u32             (*dram_attr)(u32 reg);
 309         const u32       *dram_rule;
 310         const u32       *interleave_list;
 311         const struct interleave_pkg *interleave_pkg;
 312         u8              max_sad;
 313         u8              max_interleave;
 314         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 315         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 316         enum dev_type   (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
 317         struct pci_dev  *pci_vtd;
 318 };
 319
 320 struct sbridge_channel {
 321         u32             ranks;
 322         u32             dimms;
 323 };
 324
 325 struct pci_id_descr {
 326         int                     dev_id;
 327         int                     optional;
 328 };
 329
 330 struct pci_id_table {
 331         const struct pci_id_descr       *descr;
 332         int                             n_devs;
 333         enum type                       type;
 334 };
 335
 336 struct sbridge_dev {
 337         struct list_head        list;
 338         u8                      bus, mc;
 339         u8                      node_id, source_id;
 340         struct pci_dev          **pdev;
 341         int                     n_devs;
 342         struct mem_ctl_info     *mci;
 343 };
 344
 345 struct knl_pvt {
 346         struct pci_dev          *pci_cha[KNL_MAX_CHAS];
 347         struct pci_dev          *pci_channel[KNL_MAX_CHANNELS];
 348         struct pci_dev          *pci_mc0;
 349         struct pci_dev          *pci_mc1;
 350         struct pci_dev          *pci_mc0_misc;
 351         struct pci_dev          *pci_mc1_misc;
 352         struct pci_dev          *pci_mc_info; /* tolm, tohm */
 353 };
 354
 355 struct sbridge_pvt {
 356         struct pci_dev          *pci_ta, *pci_ddrio, *pci_ras;
 357         struct pci_dev          *pci_sad0, *pci_sad1;
 358         struct pci_dev          *pci_ha0, *pci_ha1;
 359         struct pci_dev          *pci_br0, *pci_br1;
 360         struct pci_dev          *pci_ha1_ta;
 361         struct pci_dev          *pci_tad[NUM_CHANNELS];
 362
 363         struct sbridge_dev      *sbridge_dev;
 364
 365         struct sbridge_info     info;
 366         struct sbridge_channel  channel[NUM_CHANNELS];
 367
 368         /* Memory type detection */
 369         bool                    is_mirrored, is_lockstep, is_close_pg;
 370         bool                    is_chan_hash;
 371
 372         /* Memory description */
 373         u64                     tolm, tohm;
 374         struct knl_pvt knl;
 375 };
 376
 377 #define PCI_DESCR(device_id, opt)       \
 378         .dev_id = (device_id),          \
 379         .optional = opt
 380
 381 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 382                 /* Processor Home Agent */
 383         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0)     },
 384
 385                 /* Memory controller */
 386         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0)      },
 387         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0)     },
 388         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0)    },
 389         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0)    },
 390         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0)    },
 391         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0)    },
 392         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1)   },
 393
 394                 /* System Address Decoder */
 395         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0)        },
 396         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0)        },
 397
 398                 /* Broadcast Registers */
 399         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0)          },
 400 };
 401
 402 #define PCI_ID_TABLE_ENTRY(A, T) {      \
 403         .descr = A,                     \
 404         .n_devs = ARRAY_SIZE(A),        \
 405         .type = T                       \
 406 }
 407
 408 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 409         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, SANDY_BRIDGE),
 410         {0,}                    /* 0 terminated list. */
 411 };
 412
 413 /* This changes depending if 1HA or 2HA:
 414  * 1HA:
 415  *      0x0eb8 (17.0) is DDRIO0
 416  * 2HA:
 417  *      0x0ebc (17.4) is DDRIO0
 418  */
 419 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 420 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 421
 422 /* pci ids */
 423 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 424 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 425 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 426 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 427 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 428 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 429 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 430 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 431 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 432 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 433 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 434 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 435 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 436 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 437 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 438 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2        0x0e6c
 439 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3        0x0e6d
 440
 441 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 442                 /* Processor Home Agent */
 443         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0)             },
 444
 445                 /* Memory controller */
 446         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0)          },
 447         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0)         },
 448         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0)        },
 449         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0)        },
 450         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0)        },
 451         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0)        },
 452
 453                 /* System Address Decoder */
 454         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0)                 },
 455
 456                 /* Broadcast Registers */
 457         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1)                 },
 458         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0)                 },
 459
 460                 /* Optional, mode 2HA */
 461         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1)             },
 462 #if 0
 463         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1)  },
 464         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
 465 #endif
 466         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1)        },
 467         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1)        },
 468         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1)        },
 469         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1)        },
 470
 471         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1)      },
 472         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1)      },
 473 };
 474
 475 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 476         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, IVY_BRIDGE),
 477         {0,}                    /* 0 terminated list. */
 478 };
 479
 480 /* Haswell support */
 481 /* EN processor:
 482  *      - 1 IMC
 483  *      - 3 DDR3 channels, 2 DPC per channel
 484  * EP processor:
 485  *      - 1 or 2 IMC
 486  *      - 4 DDR4 channels, 3 DPC per channel
 487  * EP 4S processor:
 488  *      - 2 IMC
 489  *      - 4 DDR4 channels, 3 DPC per channel
 490  * EX processor:
 491  *      - 2 IMC
 492  *      - each IMC interfaces with a SMI 2 channel
 493  *      - each SMI channel interfaces with a scalable memory buffer
 494  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 495  */
 496 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
 497 #define HASWELL_HASYSDEFEATURE2 0x84
 498 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 499 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 500 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 501 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 502 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
 503 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 504 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
 505 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 506 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 507 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 508 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 509 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 510 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 511 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 512 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 513 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 514 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 515 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 516 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
 517 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
 518 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
 519 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 520         /* first item must be the HA */
 521         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0)             },
 522
 523         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0)        },
 524         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0)        },
 525
 526         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1)             },
 527
 528         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0)          },
 529         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0)     },
 530         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0)        },
 531         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0)        },
 532         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1)        },
 533         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1)        },
 534
 535         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1)          },
 536         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1)          },
 537         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1)          },
 538         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1)          },
 539
 540         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1)          },
 541         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1)     },
 542         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1)        },
 543         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1)        },
 544         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1)        },
 545         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1)        },
 546 };
 547
 548 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 549         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, HASWELL),
 550         {0,}                    /* 0 terminated list. */
 551 };
 552
 553 /* Knight's Landing Support */
 554 /*
 555  * KNL's memory channels are swizzled between memory controllers.
 556  * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
 557  */
 558 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
 559
 560 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
 561 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC       0x7840
 562 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
 563 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL  0x7843
 564 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
 565 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA       0x7844
 566 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
 567 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0     0x782a
 568 /* SAD target - 1-29-1 (1 of these) */
 569 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1     0x782b
 570 /* Caching / Home Agent */
 571 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA      0x782c
 572 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
 573 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM    0x7810
 574
 575 /*
 576  * KNL differs from SB, IB, and Haswell in that it has multiple
 577  * instances of the same device with the same device ID, so we handle that
 578  * by creating as many copies in the table as we expect to find.
 579  * (Like device ID must be grouped together.)
 580  */
 581
 582 static const struct pci_id_descr pci_dev_descr_knl[] = {
 583         [0]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) },
 584         [1]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) },
 585         [2 ... 3]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)},
 586         [4 ... 41]  = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) },
 587         [42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) },
 588         [48]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) },
 589         [49]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) },
 590 };
 591
 592 static const struct pci_id_table pci_dev_descr_knl_table[] = {
 593         PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, KNIGHTS_LANDING),
 594         {0,}
 595 };
 596
 597 /*
 598  * Broadwell support
 599  *
 600  * DE processor:
 601  *      - 1 IMC
 602  *      - 2 DDR3 channels, 2 DPC per channel
 603  * EP processor:
 604  *      - 1 or 2 IMC
 605  *      - 4 DDR4 channels, 3 DPC per channel
 606  * EP 4S processor:
 607  *      - 2 IMC
 608  *      - 4 DDR4 channels, 3 DPC per channel
 609  * EX processor:
 610  *      - 2 IMC
 611  *      - each IMC interfaces with a SMI 2 channel
 612  *      - each SMI channel interfaces with a scalable memory buffer
 613  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 614  */
 615 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
 616 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0   0x6fa0
 617 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1   0x6f60
 618 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA        0x6fa8
 619 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
 620 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA        0x6f68
 621 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
 622 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
 623 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
 624 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
 625 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
 626 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
 627 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
 628 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
 629 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
 630 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
 631 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
 632 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
 633
 634 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
 635         /* first item must be the HA */
 636         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0)           },
 637
 638         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0)      },
 639         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0)      },
 640
 641         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1)           },
 642
 643         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0)        },
 644         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0)   },
 645         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0)      },
 646         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0)      },
 647         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1)      },
 648         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1)      },
 649
 650         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1)        },
 651
 652         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1)        },
 653         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1)   },
 654         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1)      },
 655         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1)      },
 656         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1)      },
 657         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1)      },
 658 };
 659
 660 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
 661         PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, BROADWELL),
 662         {0,}                    /* 0 terminated list. */
 663 };
 664
 665
 666 /****************************************************************************
 667                         Ancillary status routines
 668  ****************************************************************************/
 669
 670 static inline int numrank(enum type type, u32 mtr)
 671 {
 672         int ranks = (1 << RANK_CNT_BITS(mtr));
 673         int max = 4;
 674
 675         if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
 676                 max = 8;
 677
 678         if (ranks > max) {
 679                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 680                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 681                 return -EINVAL;
 682         }
 683
 684         return ranks;
 685 }
 686
 687 static inline int numrow(u32 mtr)
 688 {
 689         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 690
 691         if (rows < 13 || rows > 18) {
 692                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 693                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 694                 return -EINVAL;
 695         }
 696
 697         return 1 << rows;
 698 }
 699
 700 static inline int numcol(u32 mtr)
 701 {
 702         int cols = (COL_WIDTH_BITS(mtr) + 10);
 703
 704         if (cols > 12) {
 705                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 706                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 707                 return -EINVAL;
 708         }
 709
 710         return 1 << cols;
 711 }
 712
 713 static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
 714 {
 715         struct sbridge_dev *sbridge_dev;
 716
 717         /*
 718          * If we have devices scattered across several busses that pertain
 719          * to the same memory controller, we'll lump them all together.
 720          */
 721         if (multi_bus) {
 722                 return list_first_entry_or_null(&sbridge_edac_list,
 723                                 struct sbridge_dev, list);
 724         }
 725
 726         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
 727                 if (sbridge_dev->bus == bus)
 728                         return sbridge_dev;
 729         }
 730
 731         return NULL;
 732 }
 733
 734 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
 735                                            const struct pci_id_table *table)
 736 {
 737         struct sbridge_dev *sbridge_dev;
 738
 739         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 740         if (!sbridge_dev)
 741                 return NULL;
 742
 743         sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
 744                                    GFP_KERNEL);
 745         if (!sbridge_dev->pdev) {
 746                 kfree(sbridge_dev);
 747                 return NULL;
 748         }
 749
 750         sbridge_dev->bus = bus;
 751         sbridge_dev->n_devs = table->n_devs;
 752         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 753
 754         return sbridge_dev;
 755 }
 756
 757 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 758 {
 759         list_del(&sbridge_dev->list);
 760         kfree(sbridge_dev->pdev);
 761         kfree(sbridge_dev);
 762 }
 763
 764 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 765 {
 766         u32 reg;
 767
 768         /* Address range is 32:28 */
 769         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 770         return GET_TOLM(reg);
 771 }
 772
 773 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 774 {
 775         u32 reg;
 776
 777         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 778         return GET_TOHM(reg);
 779 }
 780
 781 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 782 {
 783         u32 reg;
 784
 785         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 786
 787         return GET_TOLM(reg);
 788 }
 789
 790 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 791 {
 792         u32 reg;
 793
 794         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 795
 796         return GET_TOHM(reg);
 797 }
 798
 799 static u64 rir_limit(u32 reg)
 800 {
 801         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 802 }
 803
 804 static u64 sad_limit(u32 reg)
 805 {
 806         return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
 807 }
 808
 809 static u32 interleave_mode(u32 reg)
 810 {
 811         return GET_BITFIELD(reg, 1, 1);
 812 }
 813
 814 char *show_interleave_mode(u32 reg)
 815 {
 816         return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]";
 817 }
 818
 819 static u32 dram_attr(u32 reg)
 820 {
 821         return GET_BITFIELD(reg, 2, 3);
 822 }
 823
 824 static u64 knl_sad_limit(u32 reg)
 825 {
 826         return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
 827 }
 828
 829 static u32 knl_interleave_mode(u32 reg)
 830 {
 831         return GET_BITFIELD(reg, 1, 2);
 832 }
 833
 834 static char *knl_show_interleave_mode(u32 reg)
 835 {
 836         char *s;
 837
 838         switch (knl_interleave_mode(reg)) {
 839         case 0:
 840                 s = "use address bits [8:6]";
 841                 break;
 842         case 1:
 843                 s = "use address bits [10:8]";
 844                 break;
 845         case 2:
 846                 s = "use address bits [14:12]";
 847                 break;
 848         case 3:
 849                 s = "use address bits [32:30]";
 850                 break;
 851         default:
 852                 WARN_ON(1);
 853                 break;
 854         }
 855
 856         return s;
 857 }
 858
 859 static u32 dram_attr_knl(u32 reg)
 860 {
 861         return GET_BITFIELD(reg, 3, 4);
 862 }
 863
 864
 865 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 866 {
 867         u32 reg;
 868         enum mem_type mtype;
 869
 870         if (pvt->pci_ddrio) {
 871                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 872                                       &reg);
 873                 if (GET_BITFIELD(reg, 11, 11))
 874                         /* FIXME: Can also be LRDIMM */
 875                         mtype = MEM_RDDR3;
 876                 else
 877                         mtype = MEM_DDR3;
 878         } else
 879                 mtype = MEM_UNKNOWN;
 880
 881         return mtype;
 882 }
 883
 884 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 885 {
 886         u32 reg;
 887         bool registered = false;
 888         enum mem_type mtype = MEM_UNKNOWN;
 889
 890         if (!pvt->pci_ddrio)
 891                 goto out;
 892
 893         pci_read_config_dword(pvt->pci_ddrio,
 894                               HASWELL_DDRCRCLKCONTROLS, &reg);
 895         /* Is_Rdimm */
 896         if (GET_BITFIELD(reg, 16, 16))
 897                 registered = true;
 898
 899         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 900         if (GET_BITFIELD(reg, 14, 14)) {
 901                 if (registered)
 902                         mtype = MEM_RDDR4;
 903                 else
 904                         mtype = MEM_DDR4;
 905         } else {
 906                 if (registered)
 907                         mtype = MEM_RDDR3;
 908                 else
 909                         mtype = MEM_DDR3;
 910         }
 911
 912 out:
 913         return mtype;
 914 }
 915
 916 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
 917 {
 918         /* for KNL value is fixed */
 919         return DEV_X16;
 920 }
 921
 922 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 923 {
 924         /* there's no way to figure out */
 925         return DEV_UNKNOWN;
 926 }
 927
 928 static enum dev_type __ibridge_get_width(u32 mtr)
 929 {
 930         enum dev_type type;
 931
 932         switch (mtr) {
 933         case 3:
 934                 type = DEV_UNKNOWN;
 935                 break;
 936         case 2:
 937                 type = DEV_X16;
 938                 break;
 939         case 1:
 940                 type = DEV_X8;
 941                 break;
 942         case 0:
 943                 type = DEV_X4;
 944                 break;
 945         }
 946
 947         return type;
 948 }
 949
 950 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 951 {
 952         /*
 953          * ddr3_width on the documentation but also valid for DDR4 on
 954          * Haswell
 955          */
 956         return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
 957 }
 958
 959 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
 960 {
 961         /* ddr3_width on the documentation but also valid for DDR4 */
 962         return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
 963 }
 964
 965 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
 966 {
 967         /* DDR4 RDIMMS and LRDIMMS are supported */
 968         return MEM_RDDR4;
 969 }
 970
 971 static u8 get_node_id(struct sbridge_pvt *pvt)
 972 {
 973         u32 reg;
 974         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 975         return GET_BITFIELD(reg, 0, 2);
 976 }
 977
 978 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 979 {
 980         u32 reg;
 981
 982         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 983         return GET_BITFIELD(reg, 0, 3);
 984 }
 985
 986 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
 987 {
 988         u32 reg;
 989
 990         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 991         return GET_BITFIELD(reg, 0, 2);
 992 }
 993
 994
 995 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
 996 {
 997         u32 reg;
 998
 999         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
1000         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1001 }
1002
1003 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1004 {
1005         u64 rc;
1006         u32 reg;
1007
1008         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1009         rc = GET_BITFIELD(reg, 26, 31);
1010         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1011         rc = ((reg << 6) | rc) << 26;
1012
1013         return rc | 0x1ffffff;
1014 }
1015
1016 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1017 {
1018         u32 reg;
1019
1020         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1021         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1022 }
1023
1024 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1025 {
1026         u64 rc;
1027         u32 reg_lo, reg_hi;
1028
1029         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1030         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1031         rc = ((u64)reg_hi << 32) | reg_lo;
1032         return rc | 0x3ffffff;
1033 }
1034
1035
1036 static u64 haswell_rir_limit(u32 reg)
1037 {
1038         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
1039 }
1040
1041 static inline u8 sad_pkg_socket(u8 pkg)
1042 {
1043         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1044         return ((pkg >> 3) << 2) | (pkg & 0x3);
1045 }
1046
1047 static inline u8 sad_pkg_ha(u8 pkg)
1048 {
1049         return (pkg >> 2) & 0x1;
1050 }
1051
1052 static int haswell_chan_hash(int idx, u64 addr)
1053 {
1054         int i;
1055
1056         /*
1057          * XOR even bits from 12:26 to bit0 of idx,
1058          *     odd bits from 13:27 to bit1
1059          */
1060         for (i = 12; i < 28; i += 2)
1061                 idx ^= (addr >> i) & 3;
1062
1063         return idx;
1064 }
1065
1066 /****************************************************************************
1067                         Memory check routines
1068  ****************************************************************************/
1069 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
1070 {
1071         struct pci_dev *pdev = NULL;
1072
1073         do {
1074                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
1075                 if (pdev && pdev->bus->number == bus)
1076                         break;
1077         } while (pdev);
1078
1079         return pdev;
1080 }
1081
1082 /**
1083  * check_if_ecc_is_active() - Checks if ECC is active
1084  * @bus:        Device bus
1085  * @type:       Memory controller type
1086  * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
1087  *          disabled
1088  */
1089 static int check_if_ecc_is_active(const u8 bus, enum type type)
1090 {
1091         struct pci_dev *pdev = NULL;
1092         u32 mcmtr, id;
1093
1094         switch (type) {
1095         case IVY_BRIDGE:
1096                 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
1097                 break;
1098         case HASWELL:
1099                 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
1100                 break;
1101         case SANDY_BRIDGE:
1102                 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
1103                 break;
1104         case BROADWELL:
1105                 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
1106                 break;
1107         case KNIGHTS_LANDING:
1108                 /*
1109                  * KNL doesn't group things by bus the same way
1110                  * SB/IB/Haswell does.
1111                  */
1112                 id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA;
1113                 break;
1114         default:
1115                 return -ENODEV;
1116         }
1117
1118         if (type != KNIGHTS_LANDING)
1119                 pdev = get_pdev_same_bus(bus, id);
1120         else
1121                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0);
1122
1123         if (!pdev) {
1124                 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
1125                                         "%04x:%04x! on bus %02d\n",
1126                                         PCI_VENDOR_ID_INTEL, id, bus);
1127                 return -ENODEV;
1128         }
1129
1130         pci_read_config_dword(pdev,
1131                         type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr);
1132         if (!IS_ECC_ENABLED(mcmtr)) {
1133                 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
1134                 return -ENODEV;
1135         }
1136         return 0;
1137 }
1138
1139 /* Low bits of TAD limit, and some metadata. */
1140 static const u32 knl_tad_dram_limit_lo[] = {
1141         0x400, 0x500, 0x600, 0x700,
1142         0x800, 0x900, 0xa00, 0xb00,
1143 };
1144
1145 /* Low bits of TAD offset. */
1146 static const u32 knl_tad_dram_offset_lo[] = {
1147         0x404, 0x504, 0x604, 0x704,
1148         0x804, 0x904, 0xa04, 0xb04,
1149 };
1150
1151 /* High 16 bits of TAD limit and offset. */
1152 static const u32 knl_tad_dram_hi[] = {
1153         0x408, 0x508, 0x608, 0x708,
1154         0x808, 0x908, 0xa08, 0xb08,
1155 };
1156
1157 /* Number of ways a tad entry is interleaved. */
1158 static const u32 knl_tad_ways[] = {
1159         8, 6, 4, 3, 2, 1,
1160 };
1161
1162 /*
1163  * Retrieve the n'th Target Address Decode table entry
1164  * from the memory controller's TAD table.
1165  *
1166  * @pvt:        driver private data
1167  * @entry:      which entry you want to retrieve
1168  * @mc:         which memory controller (0 or 1)
1169  * @offset:     output tad range offset
1170  * @limit:      output address of first byte above tad range
1171  * @ways:       output number of interleave ways
1172  *
1173  * The offset value has curious semantics.  It's a sort of running total
1174  * of the sizes of all the memory regions that aren't mapped in this
1175  * tad table.
1176  */
1177 static int knl_get_tad(const struct sbridge_pvt *pvt,
1178                 const int entry,
1179                 const int mc,
1180                 u64 *offset,
1181                 u64 *limit,
1182                 int *ways)
1183 {
1184         u32 reg_limit_lo, reg_offset_lo, reg_hi;
1185         struct pci_dev *pci_mc;
1186         int way_id;
1187
1188         switch (mc) {
1189         case 0:
1190                 pci_mc = pvt->knl.pci_mc0;
1191                 break;
1192         case 1:
1193                 pci_mc = pvt->knl.pci_mc1;
1194                 break;
1195         default:
1196                 WARN_ON(1);
1197                 return -EINVAL;
1198         }
1199
1200         pci_read_config_dword(pci_mc,
1201                         knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1202         pci_read_config_dword(pci_mc,
1203                         knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1204         pci_read_config_dword(pci_mc,
1205                         knl_tad_dram_hi[entry], &reg_hi);
1206
1207         /* Is this TAD entry enabled? */
1208         if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1209                 return -ENODEV;
1210
1211         way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1212
1213         if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1214                 *ways = knl_tad_ways[way_id];
1215         } else {
1216                 *ways = 0;
1217                 sbridge_printk(KERN_ERR,
1218                                 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1219                                 way_id);
1220                 return -ENODEV;
1221         }
1222
1223         /*
1224          * The least significant 6 bits of base and limit are truncated.
1225          * For limit, we fill the missing bits with 1s.
1226          */
1227         *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1228                                 ((u64) GET_BITFIELD(reg_hi, 0,  15) << 32);
1229         *limit = ((u64) GET_BITFIELD(reg_limit_lo,  6, 31) << 6) | 63 |
1230                                 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1231
1232         return 0;
1233 }
1234
1235 /* Determine which memory controller is responsible for a given channel. */
1236 static int knl_channel_mc(int channel)
1237 {
1238         WARN_ON(channel < 0 || channel >= 6);
1239
1240         return channel < 3 ? 1 : 0;
1241 }
1242
1243 /*
1244  * Get the Nth entry from EDC_ROUTE_TABLE register.
1245  * (This is the per-tile mapping of logical interleave targets to
1246  *  physical EDC modules.)
1247  *
1248  * entry 0: 0:2
1249  *       1: 3:5
1250  *       2: 6:8
1251  *       3: 9:11
1252  *       4: 12:14
1253  *       5: 15:17
1254  *       6: 18:20
1255  *       7: 21:23
1256  * reserved: 24:31
1257  */
1258 static u32 knl_get_edc_route(int entry, u32 reg)
1259 {
1260         WARN_ON(entry >= KNL_MAX_EDCS);
1261         return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1262 }
1263
1264 /*
1265  * Get the Nth entry from MC_ROUTE_TABLE register.
1266  * (This is the per-tile mapping of logical interleave targets to
1267  *  physical DRAM channels modules.)
1268  *
1269  * entry 0: mc 0:2   channel 18:19
1270  *       1: mc 3:5   channel 20:21
1271  *       2: mc 6:8   channel 22:23
1272  *       3: mc 9:11  channel 24:25
1273  *       4: mc 12:14 channel 26:27
1274  *       5: mc 15:17 channel 28:29
1275  * reserved: 30:31
1276  *
1277  * Though we have 3 bits to identify the MC, we should only see
1278  * the values 0 or 1.
1279  */
1280
1281 static u32 knl_get_mc_route(int entry, u32 reg)
1282 {
1283         int mc, chan;
1284
1285         WARN_ON(entry >= KNL_MAX_CHANNELS);
1286
1287         mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1288         chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1289
1290         return knl_channel_remap(mc, chan);
1291 }
1292
1293 /*
1294  * Render the EDC_ROUTE register in human-readable form.
1295  * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1296  */
1297 static void knl_show_edc_route(u32 reg, char *s)
1298 {
1299         int i;
1300
1301         for (i = 0; i < KNL_MAX_EDCS; i++) {
1302                 s[i*2] = knl_get_edc_route(i, reg) + '0';
1303                 s[i*2+1] = '-';
1304         }
1305
1306         s[KNL_MAX_EDCS*2 - 1] = '\0';
1307 }
1308
1309 /*
1310  * Render the MC_ROUTE register in human-readable form.
1311  * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1312  */
1313 static void knl_show_mc_route(u32 reg, char *s)
1314 {
1315         int i;
1316
1317         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1318                 s[i*2] = knl_get_mc_route(i, reg) + '0';
1319                 s[i*2+1] = '-';
1320         }
1321
1322         s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1323 }
1324
1325 #define KNL_EDC_ROUTE 0xb8
1326 #define KNL_MC_ROUTE 0xb4
1327
1328 /* Is this dram rule backed by regular DRAM in flat mode? */
1329 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1330
1331 /* Is this dram rule cached? */
1332 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1333
1334 /* Is this rule backed by edc ? */
1335 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1336
1337 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1338 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1339
1340 /* Is this rule mod3? */
1341 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1342
1343 /*
1344  * Figure out how big our RAM modules are.
1345  *
1346  * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1347  * have to figure this out from the SAD rules, interleave lists, route tables,
1348  * and TAD rules.
1349  *
1350  * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1351  * inspect the TAD rules to figure out how large the SAD regions really are.
1352  *
1353  * When we know the real size of a SAD region and how many ways it's
1354  * interleaved, we know the individual contribution of each channel to
1355  * TAD is size/ways.
1356  *
1357  * Finally, we have to check whether each channel participates in each SAD
1358  * region.
1359  *
1360  * Fortunately, KNL only supports one DIMM per channel, so once we know how
1361  * much memory the channel uses, we know the DIMM is at least that large.
1362  * (The BIOS might possibly choose not to map all available memory, in which
1363  * case we will underreport the size of the DIMM.)
1364  *
1365  * In theory, we could try to determine the EDC sizes as well, but that would
1366  * only work in flat mode, not in cache mode.
1367  *
1368  * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1369  *            elements)
1370  */
1371 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1372 {
1373         u64 sad_base, sad_size, sad_limit = 0;
1374         u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1375         int sad_rule = 0;
1376         int tad_rule = 0;
1377         int intrlv_ways, tad_ways;
1378         u32 first_pkg, pkg;
1379         int i;
1380         u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1381         u32 dram_rule, interleave_reg;
1382         u32 mc_route_reg[KNL_MAX_CHAS];
1383         u32 edc_route_reg[KNL_MAX_CHAS];
1384         int edram_only;
1385         char edc_route_string[KNL_MAX_EDCS*2];
1386         char mc_route_string[KNL_MAX_CHANNELS*2];
1387         int cur_reg_start;
1388         int mc;
1389         int channel;
1390         int way;
1391         int participants[KNL_MAX_CHANNELS];
1392         int participant_count = 0;
1393
1394         for (i = 0; i < KNL_MAX_CHANNELS; i++)
1395                 mc_sizes[i] = 0;
1396
1397         /* Read the EDC route table in each CHA. */
1398         cur_reg_start = 0;
1399         for (i = 0; i < KNL_MAX_CHAS; i++) {
1400                 pci_read_config_dword(pvt->knl.pci_cha[i],
1401                                 KNL_EDC_ROUTE, &edc_route_reg[i]);
1402
1403                 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1404                         knl_show_edc_route(edc_route_reg[i-1],
1405                                         edc_route_string);
1406                         if (cur_reg_start == i-1)
1407                                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1408                                         cur_reg_start, edc_route_string);
1409                         else
1410                                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1411                                         cur_reg_start, i-1, edc_route_string);
1412                         cur_reg_start = i;
1413                 }
1414         }
1415         knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1416         if (cur_reg_start == i-1)
1417                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1418                         cur_reg_start, edc_route_string);
1419         else
1420                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1421                         cur_reg_start, i-1, edc_route_string);
1422
1423         /* Read the MC route table in each CHA. */
1424         cur_reg_start = 0;
1425         for (i = 0; i < KNL_MAX_CHAS; i++) {
1426                 pci_read_config_dword(pvt->knl.pci_cha[i],
1427                         KNL_MC_ROUTE, &mc_route_reg[i]);
1428
1429                 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1430                         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1431                         if (cur_reg_start == i-1)
1432                                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1433                                         cur_reg_start, mc_route_string);
1434                         else
1435                                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1436                                         cur_reg_start, i-1, mc_route_string);
1437                         cur_reg_start = i;
1438                 }
1439         }
1440         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1441         if (cur_reg_start == i-1)
1442                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1443                         cur_reg_start, mc_route_string);
1444         else
1445                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1446                         cur_reg_start, i-1, mc_route_string);
1447
1448         /* Process DRAM rules */
1449         for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1450                 /* previous limit becomes the new base */
1451                 sad_base = sad_limit;
1452
1453                 pci_read_config_dword(pvt->pci_sad0,
1454                         pvt->info.dram_rule[sad_rule], &dram_rule);
1455
1456                 if (!DRAM_RULE_ENABLE(dram_rule))
1457                         break;
1458
1459                 edram_only = KNL_EDRAM_ONLY(dram_rule);
1460
1461                 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1462                 sad_size = sad_limit - sad_base;
1463
1464                 pci_read_config_dword(pvt->pci_sad0,
1465                         pvt->info.interleave_list[sad_rule], &interleave_reg);
1466
1467                 /*
1468                  * Find out how many ways this dram rule is interleaved.
1469                  * We stop when we see the first channel again.
1470                  */
1471                 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1472                                                 interleave_reg, 0);
1473                 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1474                         pkg = sad_pkg(pvt->info.interleave_pkg,
1475                                                 interleave_reg, intrlv_ways);
1476
1477                         if ((pkg & 0x8) == 0) {
1478                                 /*
1479                                  * 0 bit means memory is non-local,
1480                                  * which KNL doesn't support
1481                                  */
1482                                 edac_dbg(0, "Unexpected interleave target %d\n",
1483                                         pkg);
1484                                 return -1;
1485                         }
1486
1487                         if (pkg == first_pkg)
1488                                 break;
1489                 }
1490                 if (KNL_MOD3(dram_rule))
1491                         intrlv_ways *= 3;
1492
1493                 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1494                         sad_rule,
1495                         sad_base,
1496                         sad_limit,
1497                         intrlv_ways,
1498                         edram_only ? ", EDRAM" : "");
1499
1500                 /*
1501                  * Find out how big the SAD region really is by iterating
1502                  * over TAD tables (SAD regions may contain holes).
1503                  * Each memory controller might have a different TAD table, so
1504                  * we have to look at both.
1505                  *
1506                  * Livespace is the memory that's mapped in this TAD table,
1507                  * deadspace is the holes (this could be the MMIO hole, or it
1508                  * could be memory that's mapped by the other TAD table but
1509                  * not this one).
1510                  */
1511                 for (mc = 0; mc < 2; mc++) {
1512                         sad_actual_size[mc] = 0;
1513                         tad_livespace = 0;
1514                         for (tad_rule = 0;
1515                                         tad_rule < ARRAY_SIZE(
1516                                                 knl_tad_dram_limit_lo);
1517                                         tad_rule++) {
1518                                 if (knl_get_tad(pvt,
1519                                                 tad_rule,
1520                                                 mc,
1521                                                 &tad_deadspace,
1522                                                 &tad_limit,
1523                                                 &tad_ways))
1524                                         break;
1525
1526                                 tad_size = (tad_limit+1) -
1527                                         (tad_livespace + tad_deadspace);
1528                                 tad_livespace += tad_size;
1529                                 tad_base = (tad_limit+1) - tad_size;
1530
1531                                 if (tad_base < sad_base) {
1532                                         if (tad_limit > sad_base)
1533                                                 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1534                                 } else if (tad_base < sad_limit) {
1535                                         if (tad_limit+1 > sad_limit) {
1536                                                 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1537                                         } else {
1538                                                 /* TAD region is completely inside SAD region */
1539                                                 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1540                                                         tad_rule, tad_base,
1541                                                         tad_limit, tad_size,
1542                                                         mc);
1543                                                 sad_actual_size[mc] += tad_size;
1544                                         }
1545                                 }
1546                                 tad_base = tad_limit+1;
1547                         }
1548                 }
1549
1550                 for (mc = 0; mc < 2; mc++) {
1551                         edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1552                                 mc, sad_actual_size[mc], sad_actual_size[mc]);
1553                 }
1554
1555                 /* Ignore EDRAM rule */
1556                 if (edram_only)
1557                         continue;
1558
1559                 /* Figure out which channels participate in interleave. */
1560                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1561                         participants[channel] = 0;
1562
1563                 /* For each channel, does at least one CHA have
1564                  * this channel mapped to the given target?
1565                  */
1566                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1567                         for (way = 0; way < intrlv_ways; way++) {
1568                                 int target;
1569                                 int cha;
1570
1571                                 if (KNL_MOD3(dram_rule))
1572                                         target = way;
1573                                 else
1574                                         target = 0x7 & sad_pkg(
1575                                 pvt->info.interleave_pkg, interleave_reg, way);
1576
1577                                 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1578                                         if (knl_get_mc_route(target,
1579                                                 mc_route_reg[cha]) == channel
1580                                                 && !participants[channel]) {
1581                                                 participant_count++;
1582                                                 participants[channel] = 1;
1583                                                 break;
1584                                         }
1585                                 }
1586                         }
1587                 }
1588
1589                 if (participant_count != intrlv_ways)
1590                         edac_dbg(0, "participant_count (%d) != interleave_ways (%d): DIMM size may be incorrect\n",
1591                                 participant_count, intrlv_ways);
1592
1593                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1594                         mc = knl_channel_mc(channel);
1595                         if (participants[channel]) {
1596                                 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1597                                         channel,
1598                                         sad_actual_size[mc]/intrlv_ways,
1599                                         sad_rule);
1600                                 mc_sizes[channel] +=
1601                                         sad_actual_size[mc]/intrlv_ways;
1602                         }
1603                 }
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int get_dimm_config(struct mem_ctl_info *mci)
1610 {
1611         struct sbridge_pvt *pvt = mci->pvt_info;
1612         struct dimm_info *dimm;
1613         unsigned i, j, banks, ranks, rows, cols, npages;
1614         u64 size;
1615         u32 reg;
1616         enum edac_type mode;
1617         enum mem_type mtype;
1618         int channels = pvt->info.type == KNIGHTS_LANDING ?
1619                 KNL_MAX_CHANNELS : NUM_CHANNELS;
1620         u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1621
1622         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1623                 pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, &reg);
1624                 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1625         }
1626         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1627                         pvt->info.type == KNIGHTS_LANDING)
1628                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1629         else
1630                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1631
1632         if (pvt->info.type == KNIGHTS_LANDING)
1633                 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1634         else
1635                 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1636
1637         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1638         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1639                  pvt->sbridge_dev->mc,
1640                  pvt->sbridge_dev->node_id,
1641                  pvt->sbridge_dev->source_id);
1642
1643         /* KNL doesn't support mirroring or lockstep,
1644          * and is always closed page
1645          */
1646         if (pvt->info.type == KNIGHTS_LANDING) {
1647                 mode = EDAC_S4ECD4ED;
1648                 pvt->is_mirrored = false;
1649
1650                 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1651                         return -1;
1652         } else {
1653                 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
1654                 if (IS_MIRROR_ENABLED(reg)) {
1655                         edac_dbg(0, "Memory mirror is enabled\n");
1656                         pvt->is_mirrored = true;
1657                 } else {
1658                         edac_dbg(0, "Memory mirror is disabled\n");
1659                         pvt->is_mirrored = false;
1660                 }
1661
1662                 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
1663                 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1664                         edac_dbg(0, "Lockstep is enabled\n");
1665                         mode = EDAC_S8ECD8ED;
1666                         pvt->is_lockstep = true;
1667                 } else {
1668                         edac_dbg(0, "Lockstep is disabled\n");
1669                         mode = EDAC_S4ECD4ED;
1670                         pvt->is_lockstep = false;
1671                 }
1672                 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1673                         edac_dbg(0, "address map is on closed page mode\n");
1674                         pvt->is_close_pg = true;
1675                 } else {
1676                         edac_dbg(0, "address map is on open page mode\n");
1677                         pvt->is_close_pg = false;
1678                 }
1679         }
1680
1681         mtype = pvt->info.get_memory_type(pvt);
1682         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1683                 edac_dbg(0, "Memory is registered\n");
1684         else if (mtype == MEM_UNKNOWN)
1685                 edac_dbg(0, "Cannot determine memory type\n");
1686         else
1687                 edac_dbg(0, "Memory is unregistered\n");
1688
1689         if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1690                 banks = 16;
1691         else
1692                 banks = 8;
1693
1694         for (i = 0; i < channels; i++) {
1695                 u32 mtr;
1696
1697                 int max_dimms_per_channel;
1698
1699                 if (pvt->info.type == KNIGHTS_LANDING) {
1700                         max_dimms_per_channel = 1;
1701                         if (!pvt->knl.pci_channel[i])
1702                                 continue;
1703                 } else {
1704                         max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1705                         if (!pvt->pci_tad[i])
1706                                 continue;
1707                 }
1708
1709                 for (j = 0; j < max_dimms_per_channel; j++) {
1710                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1711                                        i, j, 0);
1712                         if (pvt->info.type == KNIGHTS_LANDING) {
1713                                 pci_read_config_dword(pvt->knl.pci_channel[i],
1714                                         knl_mtr_reg, &mtr);
1715                         } else {
1716                                 pci_read_config_dword(pvt->pci_tad[i],
1717                                         mtr_regs[j], &mtr);
1718                         }
1719                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
1720                         if (IS_DIMM_PRESENT(mtr)) {
1721                                 pvt->channel[i].dimms++;
1722
1723                                 ranks = numrank(pvt->info.type, mtr);
1724
1725                                 if (pvt->info.type == KNIGHTS_LANDING) {
1726                                         /* For DDR4, this is fixed. */
1727                                         cols = 1 << 10;
1728                                         rows = knl_mc_sizes[i] /
1729                                                 ((u64) cols * ranks * banks * 8);
1730                                 } else {
1731                                         rows = numrow(mtr);
1732                                         cols = numcol(mtr);
1733                                 }
1734
1735                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1736                                 npages = MiB_TO_PAGES(size);
1737
1738                                 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1739                                          pvt->sbridge_dev->mc, i/4, i%4, j,
1740                                          size, npages,
1741                                          banks, ranks, rows, cols);
1742
1743                                 dimm->nr_pages = npages;
1744                                 dimm->grain = 32;
1745                                 dimm->dtype = pvt->info.get_width(pvt, mtr);
1746                                 dimm->mtype = mtype;
1747                                 dimm->edac_mode = mode;
1748                                 snprintf(dimm->label, sizeof(dimm->label),
1749                                          "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1750                                          pvt->sbridge_dev->source_id, i/4, i%4, j);
1751                         }
1752                 }
1753         }
1754
1755         return 0;
1756 }
1757
1758 static void get_memory_layout(const struct mem_ctl_info *mci)
1759 {
1760         struct sbridge_pvt *pvt = mci->pvt_info;
1761         int i, j, k, n_sads, n_tads, sad_interl;
1762         u32 reg;
1763         u64 limit, prv = 0;
1764         u64 tmp_mb;
1765         u32 gb, mb;
1766         u32 rir_way;
1767
1768         /*
1769          * Step 1) Get TOLM/TOHM ranges
1770          */
1771
1772         pvt->tolm = pvt->info.get_tolm(pvt);
1773         tmp_mb = (1 + pvt->tolm) >> 20;
1774
1775         gb = div_u64_rem(tmp_mb, 1024, &mb);
1776         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1777                 gb, (mb*1000)/1024, (u64)pvt->tolm);
1778
1779         /* Address range is already 45:25 */
1780         pvt->tohm = pvt->info.get_tohm(pvt);
1781         tmp_mb = (1 + pvt->tohm) >> 20;
1782
1783         gb = div_u64_rem(tmp_mb, 1024, &mb);
1784         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1785                 gb, (mb*1000)/1024, (u64)pvt->tohm);
1786
1787         /*
1788          * Step 2) Get SAD range and SAD Interleave list
1789          * TAD registers contain the interleave wayness. However, it
1790          * seems simpler to just discover it indirectly, with the
1791          * algorithm bellow.
1792          */
1793         prv = 0;
1794         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1795                 /* SAD_LIMIT Address range is 45:26 */
1796                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1797                                       &reg);
1798                 limit = pvt->info.sad_limit(reg);
1799
1800                 if (!DRAM_RULE_ENABLE(reg))
1801                         continue;
1802
1803                 if (limit <= prv)
1804                         break;
1805
1806                 tmp_mb = (limit + 1) >> 20;
1807                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1808                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1809                          n_sads,
1810                          show_dram_attr(pvt->info.dram_attr(reg)),
1811                          gb, (mb*1000)/1024,
1812                          ((u64)tmp_mb) << 20L,
1813                          pvt->info.show_interleave_mode(reg),
1814                          reg);
1815                 prv = limit;
1816
1817                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1818                                       &reg);
1819                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1820                 for (j = 0; j < 8; j++) {
1821                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1822                         if (j > 0 && sad_interl == pkg)
1823                                 break;
1824
1825                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1826                                  n_sads, j, pkg);
1827                 }
1828         }
1829
1830         if (pvt->info.type == KNIGHTS_LANDING)
1831                 return;
1832
1833         /*
1834          * Step 3) Get TAD range
1835          */
1836         prv = 0;
1837         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1838                 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1839                                       &reg);
1840                 limit = TAD_LIMIT(reg);
1841                 if (limit <= prv)
1842                         break;
1843                 tmp_mb = (limit + 1) >> 20;
1844
1845                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1846                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1847                          n_tads, gb, (mb*1000)/1024,
1848                          ((u64)tmp_mb) << 20L,
1849                          (u32)(1 << TAD_SOCK(reg)),
1850                          (u32)TAD_CH(reg) + 1,
1851                          (u32)TAD_TGT0(reg),
1852                          (u32)TAD_TGT1(reg),
1853                          (u32)TAD_TGT2(reg),
1854                          (u32)TAD_TGT3(reg),
1855                          reg);
1856                 prv = limit;
1857         }
1858
1859         /*
1860          * Step 4) Get TAD offsets, per each channel
1861          */
1862         for (i = 0; i < NUM_CHANNELS; i++) {
1863                 if (!pvt->channel[i].dimms)
1864                         continue;
1865                 for (j = 0; j < n_tads; j++) {
1866                         pci_read_config_dword(pvt->pci_tad[i],
1867                                               tad_ch_nilv_offset[j],
1868                                               &reg);
1869                         tmp_mb = TAD_OFFSET(reg) >> 20;
1870                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1871                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1872                                  i, j,
1873                                  gb, (mb*1000)/1024,
1874                                  ((u64)tmp_mb) << 20L,
1875                                  reg);
1876                 }
1877         }
1878
1879         /*
1880          * Step 6) Get RIR Wayness/Limit, per each channel
1881          */
1882         for (i = 0; i < NUM_CHANNELS; i++) {
1883                 if (!pvt->channel[i].dimms)
1884                         continue;
1885                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1886                         pci_read_config_dword(pvt->pci_tad[i],
1887                                               rir_way_limit[j],
1888                                               &reg);
1889
1890                         if (!IS_RIR_VALID(reg))
1891                                 continue;
1892
1893                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1894                         rir_way = 1 << RIR_WAY(reg);
1895                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1896                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1897                                  i, j,
1898                                  gb, (mb*1000)/1024,
1899                                  ((u64)tmp_mb) << 20L,
1900                                  rir_way,
1901                                  reg);
1902
1903                         for (k = 0; k < rir_way; k++) {
1904                                 pci_read_config_dword(pvt->pci_tad[i],
1905                                                       rir_offset[j][k],
1906                                                       &reg);
1907                                 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1908
1909                                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1910                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1911                                          i, j, k,
1912                                          gb, (mb*1000)/1024,
1913                                          ((u64)tmp_mb) << 20L,
1914                                          (u32)RIR_RNK_TGT(pvt->info.type, reg),
1915                                          reg);
1916                         }
1917                 }
1918         }
1919 }
1920
1921 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1922 {
1923         struct sbridge_dev *sbridge_dev;
1924
1925         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1926                 if (sbridge_dev->node_id == node_id)
1927                         return sbridge_dev->mci;
1928         }
1929         return NULL;
1930 }
1931
1932 static int get_memory_error_data(struct mem_ctl_info *mci,
1933                                  u64 addr,
1934                                  u8 *socket, u8 *ha,
1935                                  long *channel_mask,
1936                                  u8 *rank,
1937                                  char **area_type, char *msg)
1938 {
1939         struct mem_ctl_info     *new_mci;
1940         struct sbridge_pvt *pvt = mci->pvt_info;
1941         struct pci_dev          *pci_ha;
1942         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1943         int                     sad_interl, idx, base_ch;
1944         int                     interleave_mode, shiftup = 0;
1945         unsigned                sad_interleave[pvt->info.max_interleave];
1946         u32                     reg, dram_rule;
1947         u8                      ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1948         u32                     tad_offset;
1949         u32                     rir_way;
1950         u32                     mb, gb;
1951         u64                     ch_addr, offset, limit = 0, prv = 0;
1952
1953
1954         /*
1955          * Step 0) Check if the address is at special memory ranges
1956          * The check bellow is probably enough to fill all cases where
1957          * the error is not inside a memory, except for the legacy
1958          * range (e. g. VGA addresses). It is unlikely, however, that the
1959          * memory controller would generate an error on that range.
1960          */
1961         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1962                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1963                 return -EINVAL;
1964         }
1965         if (addr >= (u64)pvt->tohm) {
1966                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1967                 return -EINVAL;
1968         }
1969
1970         /*
1971          * Step 1) Get socket
1972          */
1973         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1974                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1975                                       &reg);
1976
1977                 if (!DRAM_RULE_ENABLE(reg))
1978                         continue;
1979
1980                 limit = pvt->info.sad_limit(reg);
1981                 if (limit <= prv) {
1982                         sprintf(msg, "Can't discover the memory socket");
1983                         return -EINVAL;
1984                 }
1985                 if  (addr <= limit)
1986                         break;
1987                 prv = limit;
1988         }
1989         if (n_sads == pvt->info.max_sad) {
1990                 sprintf(msg, "Can't discover the memory socket");
1991                 return -EINVAL;
1992         }
1993         dram_rule = reg;
1994         *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1995         interleave_mode = pvt->info.interleave_mode(dram_rule);
1996
1997         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1998                               &reg);
1999
2000         if (pvt->info.type == SANDY_BRIDGE) {
2001                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
2002                 for (sad_way = 0; sad_way < 8; sad_way++) {
2003                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2004                         if (sad_way > 0 && sad_interl == pkg)
2005                                 break;
2006                         sad_interleave[sad_way] = pkg;
2007                         edac_dbg(0, "SAD interleave #%d: %d\n",
2008                                  sad_way, sad_interleave[sad_way]);
2009                 }
2010                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2011                          pvt->sbridge_dev->mc,
2012                          n_sads,
2013                          addr,
2014                          limit,
2015                          sad_way + 7,
2016                          !interleave_mode ? "" : "XOR[18:16]");
2017                 if (interleave_mode)
2018                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2019                 else
2020                         idx = (addr >> 6) & 7;
2021                 switch (sad_way) {
2022                 case 1:
2023                         idx = 0;
2024                         break;
2025                 case 2:
2026                         idx = idx & 1;
2027                         break;
2028                 case 4:
2029                         idx = idx & 3;
2030                         break;
2031                 case 8:
2032                         break;
2033                 default:
2034                         sprintf(msg, "Can't discover socket interleave");
2035                         return -EINVAL;
2036                 }
2037                 *socket = sad_interleave[idx];
2038                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2039                          idx, sad_way, *socket);
2040         } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2041                 int bits, a7mode = A7MODE(dram_rule);
2042
2043                 if (a7mode) {
2044                         /* A7 mode swaps P9 with P6 */
2045                         bits = GET_BITFIELD(addr, 7, 8) << 1;
2046                         bits |= GET_BITFIELD(addr, 9, 9);
2047                 } else
2048                         bits = GET_BITFIELD(addr, 6, 8);
2049
2050                 if (interleave_mode == 0) {
2051                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
2052                         idx = GET_BITFIELD(addr, 16, 18);
2053                         idx ^= bits;
2054                 } else
2055                         idx = bits;
2056
2057                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2058                 *socket = sad_pkg_socket(pkg);
2059                 sad_ha = sad_pkg_ha(pkg);
2060                 if (sad_ha)
2061                         ch_add = 4;
2062
2063                 if (a7mode) {
2064                         /* MCChanShiftUpEnable */
2065                         pci_read_config_dword(pvt->pci_ha0,
2066                                               HASWELL_HASYSDEFEATURE2, &reg);
2067                         shiftup = GET_BITFIELD(reg, 22, 22);
2068                 }
2069
2070                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2071                          idx, *socket, sad_ha, shiftup);
2072         } else {
2073                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2074                 idx = (addr >> 6) & 7;
2075                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2076                 *socket = sad_pkg_socket(pkg);
2077                 sad_ha = sad_pkg_ha(pkg);
2078                 if (sad_ha)
2079                         ch_add = 4;
2080                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2081                          idx, *socket, sad_ha);
2082         }
2083
2084         *ha = sad_ha;
2085
2086         /*
2087          * Move to the proper node structure, in order to access the
2088          * right PCI registers
2089          */
2090         new_mci = get_mci_for_node_id(*socket);
2091         if (!new_mci) {
2092                 sprintf(msg, "Struct for socket #%u wasn't initialized",
2093                         *socket);
2094                 return -EINVAL;
2095         }
2096         mci = new_mci;
2097         pvt = mci->pvt_info;
2098
2099         /*
2100          * Step 2) Get memory channel
2101          */
2102         prv = 0;
2103         if (pvt->info.type == SANDY_BRIDGE)
2104                 pci_ha = pvt->pci_ha0;
2105         else {
2106                 if (sad_ha)
2107                         pci_ha = pvt->pci_ha1;
2108                 else
2109                         pci_ha = pvt->pci_ha0;
2110         }
2111         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2112                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2113                 limit = TAD_LIMIT(reg);
2114                 if (limit <= prv) {
2115                         sprintf(msg, "Can't discover the memory channel");
2116                         return -EINVAL;
2117                 }
2118                 if  (addr <= limit)
2119                         break;
2120                 prv = limit;
2121         }
2122         if (n_tads == MAX_TAD) {
2123                 sprintf(msg, "Can't discover the memory channel");
2124                 return -EINVAL;
2125         }
2126
2127         ch_way = TAD_CH(reg) + 1;
2128         sck_way = TAD_SOCK(reg);
2129
2130         if (ch_way == 3)
2131                 idx = addr >> 6;
2132         else {
2133                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2134                 if (pvt->is_chan_hash)
2135                         idx = haswell_chan_hash(idx, addr);
2136         }
2137         idx = idx % ch_way;
2138
2139         /*
2140          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2141          */
2142         switch (idx) {
2143         case 0:
2144                 base_ch = TAD_TGT0(reg);
2145                 break;
2146         case 1:
2147                 base_ch = TAD_TGT1(reg);
2148                 break;
2149         case 2:
2150                 base_ch = TAD_TGT2(reg);
2151                 break;
2152         case 3:
2153                 base_ch = TAD_TGT3(reg);
2154                 break;
2155         default:
2156                 sprintf(msg, "Can't discover the TAD target");
2157                 return -EINVAL;
2158         }
2159         *channel_mask = 1 << base_ch;
2160
2161         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2162                                 tad_ch_nilv_offset[n_tads],
2163                                 &tad_offset);
2164
2165         if (pvt->is_mirrored) {
2166                 *channel_mask |= 1 << ((base_ch + 2) % 4);
2167                 switch(ch_way) {
2168                 case 2:
2169                 case 4:
2170                         sck_xch = (1 << sck_way) * (ch_way >> 1);
2171                         break;
2172                 default:
2173                         sprintf(msg, "Invalid mirror set. Can't decode addr");
2174                         return -EINVAL;
2175                 }
2176         } else
2177                 sck_xch = (1 << sck_way) * ch_way;
2178
2179         if (pvt->is_lockstep)
2180                 *channel_mask |= 1 << ((base_ch + 1) % 4);
2181
2182         offset = TAD_OFFSET(tad_offset);
2183
2184         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2185                  n_tads,
2186                  addr,
2187                  limit,
2188                  sck_way,
2189                  ch_way,
2190                  offset,
2191                  idx,
2192                  base_ch,
2193                  *channel_mask);
2194
2195         /* Calculate channel address */
2196         /* Remove the TAD offset */
2197
2198         if (offset > addr) {
2199                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2200                         offset, addr);
2201                 return -EINVAL;
2202         }
2203
2204         ch_addr = addr - offset;
2205         ch_addr >>= (6 + shiftup);
2206         ch_addr /= sck_xch;
2207         ch_addr <<= (6 + shiftup);
2208         ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2209
2210         /*
2211          * Step 3) Decode rank
2212          */
2213         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2214                 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2215                                       rir_way_limit[n_rir],
2216                                       &reg);
2217
2218                 if (!IS_RIR_VALID(reg))
2219                         continue;
2220
2221                 limit = pvt->info.rir_limit(reg);
2222                 gb = div_u64_rem(limit >> 20, 1024, &mb);
2223                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2224                          n_rir,
2225                          gb, (mb*1000)/1024,
2226                          limit,
2227                          1 << RIR_WAY(reg));
2228                 if  (ch_addr <= limit)
2229                         break;
2230         }
2231         if (n_rir == MAX_RIR_RANGES) {
2232                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2233                         ch_addr);
2234                 return -EINVAL;
2235         }
2236         rir_way = RIR_WAY(reg);
2237
2238         if (pvt->is_close_pg)
2239                 idx = (ch_addr >> 6);
2240         else
2241                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
2242         idx %= 1 << rir_way;
2243
2244         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2245                               rir_offset[n_rir][idx],
2246                               &reg);
2247         *rank = RIR_RNK_TGT(pvt->info.type, reg);
2248
2249         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2250                  n_rir,
2251                  ch_addr,
2252                  limit,
2253                  rir_way,
2254                  idx);
2255
2256         return 0;
2257 }
2258
2259 /****************************************************************************
2260         Device initialization routines: put/get, init/exit
2261  ****************************************************************************/
2262
2263 /*
2264  *      sbridge_put_all_devices 'put' all the devices that we have
2265  *                              reserved via 'get'
2266  */
2267 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2268 {
2269         int i;
2270
2271         edac_dbg(0, "\n");
2272         for (i = 0; i < sbridge_dev->n_devs; i++) {
2273                 struct pci_dev *pdev = sbridge_dev->pdev[i];
2274                 if (!pdev)
2275                         continue;
2276                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2277                          pdev->bus->number,
2278                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2279                 pci_dev_put(pdev);
2280         }
2281 }
2282
2283 static void sbridge_put_all_devices(void)
2284 {
2285         struct sbridge_dev *sbridge_dev, *tmp;
2286
2287         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2288                 sbridge_put_devices(sbridge_dev);
2289                 free_sbridge_dev(sbridge_dev);
2290         }
2291 }
2292
2293 static int sbridge_get_onedevice(struct pci_dev **prev,
2294                                  u8 *num_mc,
2295                                  const struct pci_id_table *table,
2296                                  const unsigned devno,
2297                                  const int multi_bus)
2298 {
2299         struct sbridge_dev *sbridge_dev;
2300         const struct pci_id_descr *dev_descr = &table->descr[devno];
2301         struct pci_dev *pdev = NULL;
2302         u8 bus = 0;
2303
2304         sbridge_printk(KERN_DEBUG,
2305                 "Seeking for: PCI ID %04x:%04x\n",
2306                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2307
2308         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2309                               dev_descr->dev_id, *prev);
2310
2311         if (!pdev) {
2312                 if (*prev) {
2313                         *prev = pdev;
2314                         return 0;
2315                 }
2316
2317                 if (dev_descr->optional)
2318                         return 0;
2319
2320                 /* if the HA wasn't found */
2321                 if (devno == 0)
2322                         return -ENODEV;
2323
2324                 sbridge_printk(KERN_INFO,
2325                         "Device not found: %04x:%04x\n",
2326                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2327
2328                 /* End of list, leave */
2329                 return -ENODEV;
2330         }
2331         bus = pdev->bus->number;
2332
2333         sbridge_dev = get_sbridge_dev(bus, multi_bus);
2334         if (!sbridge_dev) {
2335                 sbridge_dev = alloc_sbridge_dev(bus, table);
2336                 if (!sbridge_dev) {
2337                         pci_dev_put(pdev);
2338                         return -ENOMEM;
2339                 }
2340                 (*num_mc)++;
2341         }
2342
2343         if (sbridge_dev->pdev[devno]) {
2344                 sbridge_printk(KERN_ERR,
2345                         "Duplicated device for %04x:%04x\n",
2346                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2347                 pci_dev_put(pdev);
2348                 return -ENODEV;
2349         }
2350
2351         sbridge_dev->pdev[devno] = pdev;
2352
2353         /* Be sure that the device is enabled */
2354         if (unlikely(pci_enable_device(pdev) < 0)) {
2355                 sbridge_printk(KERN_ERR,
2356                         "Couldn't enable %04x:%04x\n",
2357                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2358                 return -ENODEV;
2359         }
2360
2361         edac_dbg(0, "Detected %04x:%04x\n",
2362                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2363
2364         /*
2365          * As stated on drivers/pci/search.c, the reference count for
2366          * @from is always decremented if it is not %NULL. So, as we need
2367          * to get all devices up to null, we need to do a get for the device
2368          */
2369         pci_dev_get(pdev);
2370
2371         *prev = pdev;
2372
2373         return 0;
2374 }
2375
2376 /*
2377  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2378  *                           devices we want to reference for this driver.
2379  * @num_mc: pointer to the memory controllers count, to be incremented in case
2380  *          of success.
2381  * @table: model specific table
2382  *
2383  * returns 0 in case of success or error code
2384  */
2385 static int sbridge_get_all_devices(u8 *num_mc,
2386                                         const struct pci_id_table *table)
2387 {
2388         int i, rc;
2389         struct pci_dev *pdev = NULL;
2390         int allow_dups = 0;
2391         int multi_bus = 0;
2392
2393         if (table->type == KNIGHTS_LANDING)
2394                 allow_dups = multi_bus = 1;
2395         while (table && table->descr) {
2396                 for (i = 0; i < table->n_devs; i++) {
2397                         if (!allow_dups || i == 0 ||
2398                                         table->descr[i].dev_id !=
2399                                                 table->descr[i-1].dev_id) {
2400                                 pdev = NULL;
2401                         }
2402                         do {
2403                                 rc = sbridge_get_onedevice(&pdev, num_mc,
2404                                                            table, i, multi_bus);
2405                                 if (rc < 0) {
2406                                         if (i == 0) {
2407                                                 i = table->n_devs;
2408                                                 break;
2409                                         }
2410                                         sbridge_put_all_devices();
2411                                         return -ENODEV;
2412                                 }
2413                         } while (pdev && !allow_dups);
2414                 }
2415                 table++;
2416         }
2417
2418         return 0;
2419 }
2420
2421 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2422                                  struct sbridge_dev *sbridge_dev)
2423 {
2424         struct sbridge_pvt *pvt = mci->pvt_info;
2425         struct pci_dev *pdev;
2426         u8 saw_chan_mask = 0;
2427         int i;
2428
2429         for (i = 0; i < sbridge_dev->n_devs; i++) {
2430                 pdev = sbridge_dev->pdev[i];
2431                 if (!pdev)
2432                         continue;
2433
2434                 switch (pdev->device) {
2435                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2436                         pvt->pci_sad0 = pdev;
2437                         break;
2438                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2439                         pvt->pci_sad1 = pdev;
2440                         break;
2441                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2442                         pvt->pci_br0 = pdev;
2443                         break;
2444                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2445                         pvt->pci_ha0 = pdev;
2446                         break;
2447                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2448                         pvt->pci_ta = pdev;
2449                         break;
2450                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2451                         pvt->pci_ras = pdev;
2452                         break;
2453                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2454                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2455                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2456                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2457                 {
2458                         int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
2459                         pvt->pci_tad[id] = pdev;
2460                         saw_chan_mask |= 1 << id;
2461                 }
2462                         break;
2463                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2464                         pvt->pci_ddrio = pdev;
2465                         break;
2466                 default:
2467                         goto error;
2468                 }
2469
2470                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2471                          pdev->vendor, pdev->device,
2472                          sbridge_dev->bus,
2473                          pdev);
2474         }
2475
2476         /* Check if everything were registered */
2477         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
2478             !pvt->pci_ras || !pvt->pci_ta)
2479                 goto enodev;
2480
2481         if (saw_chan_mask != 0x0f)
2482                 goto enodev;
2483         return 0;
2484
2485 enodev:
2486         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2487         return -ENODEV;
2488
2489 error:
2490         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2491                        PCI_VENDOR_ID_INTEL, pdev->device);
2492         return -EINVAL;
2493 }
2494
2495 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2496                                  struct sbridge_dev *sbridge_dev)
2497 {
2498         struct sbridge_pvt *pvt = mci->pvt_info;
2499         struct pci_dev *pdev;
2500         u8 saw_chan_mask = 0;
2501         int i;
2502
2503         for (i = 0; i < sbridge_dev->n_devs; i++) {
2504                 pdev = sbridge_dev->pdev[i];
2505                 if (!pdev)
2506                         continue;
2507
2508                 switch (pdev->device) {
2509                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2510                         pvt->pci_ha0 = pdev;
2511                         break;
2512                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2513                         pvt->pci_ta = pdev;
2514                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2515                         pvt->pci_ras = pdev;
2516                         break;
2517                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2518                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2519                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2520                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2521                 {
2522                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
2523                         pvt->pci_tad[id] = pdev;
2524                         saw_chan_mask |= 1 << id;
2525                 }
2526                         break;
2527                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2528                         pvt->pci_ddrio = pdev;
2529                         break;
2530                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2531                         pvt->pci_ddrio = pdev;
2532                         break;
2533                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2534                         pvt->pci_sad0 = pdev;
2535                         break;
2536                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2537                         pvt->pci_br0 = pdev;
2538                         break;
2539                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2540                         pvt->pci_br1 = pdev;
2541                         break;
2542                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2543                         pvt->pci_ha1 = pdev;
2544                         break;
2545                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2546                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2547                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2548                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2549                 {
2550                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
2551                         pvt->pci_tad[id] = pdev;
2552                         saw_chan_mask |= 1 << id;
2553                 }
2554                         break;
2555                 default:
2556                         goto error;
2557                 }
2558
2559                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2560                          sbridge_dev->bus,
2561                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2562                          pdev);
2563         }
2564
2565         /* Check if everything were registered */
2566         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
2567             !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2568                 goto enodev;
2569
2570         if (saw_chan_mask != 0x0f && /* -EN */
2571             saw_chan_mask != 0x33 && /* -EP */
2572             saw_chan_mask != 0xff)   /* -EX */
2573                 goto enodev;
2574         return 0;
2575
2576 enodev:
2577         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2578         return -ENODEV;
2579
2580 error:
2581         sbridge_printk(KERN_ERR,
2582                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2583                         pdev->device);
2584         return -EINVAL;
2585 }
2586
2587 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2588                                  struct sbridge_dev *sbridge_dev)
2589 {
2590         struct sbridge_pvt *pvt = mci->pvt_info;
2591         struct pci_dev *pdev;
2592         u8 saw_chan_mask = 0;
2593         int i;
2594
2595         /* there's only one device per system; not tied to any bus */
2596         if (pvt->info.pci_vtd == NULL)
2597                 /* result will be checked later */
2598                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2599                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2600                                                    NULL);
2601
2602         for (i = 0; i < sbridge_dev->n_devs; i++) {
2603                 pdev = sbridge_dev->pdev[i];
2604                 if (!pdev)
2605                         continue;
2606
2607                 switch (pdev->device) {
2608                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2609                         pvt->pci_sad0 = pdev;
2610                         break;
2611                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2612                         pvt->pci_sad1 = pdev;
2613                         break;
2614                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2615                         pvt->pci_ha0 = pdev;
2616                         break;
2617                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2618                         pvt->pci_ta = pdev;
2619                         break;
2620                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
2621                         pvt->pci_ras = pdev;
2622                         break;
2623                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2624                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2625                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2626                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2627                 {
2628                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
2629
2630                         pvt->pci_tad[id] = pdev;
2631                         saw_chan_mask |= 1 << id;
2632                 }
2633                         break;
2634                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2635                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2636                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2637                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2638                 {
2639                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
2640
2641                         pvt->pci_tad[id] = pdev;
2642                         saw_chan_mask |= 1 << id;
2643                 }
2644                         break;
2645                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2646                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2647                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2648                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2649                         if (!pvt->pci_ddrio)
2650                                 pvt->pci_ddrio = pdev;
2651                         break;
2652                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2653                         pvt->pci_ha1 = pdev;
2654                         break;
2655                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2656                         pvt->pci_ha1_ta = pdev;
2657                         break;
2658                 default:
2659                         break;
2660                 }
2661
2662                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2663                          sbridge_dev->bus,
2664                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2665                          pdev);
2666         }
2667
2668         /* Check if everything were registered */
2669         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2670             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2671                 goto enodev;
2672
2673         if (saw_chan_mask != 0x0f && /* -EN */
2674             saw_chan_mask != 0x33 && /* -EP */
2675             saw_chan_mask != 0xff)   /* -EX */
2676                 goto enodev;
2677         return 0;
2678
2679 enodev:
2680         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2681         return -ENODEV;
2682 }
2683
2684 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2685                                  struct sbridge_dev *sbridge_dev)
2686 {
2687         struct sbridge_pvt *pvt = mci->pvt_info;
2688         struct pci_dev *pdev;
2689         u8 saw_chan_mask = 0;
2690         int i;
2691
2692         /* there's only one device per system; not tied to any bus */
2693         if (pvt->info.pci_vtd == NULL)
2694                 /* result will be checked later */
2695                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2696                                                    PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2697                                                    NULL);
2698
2699         for (i = 0; i < sbridge_dev->n_devs; i++) {
2700                 pdev = sbridge_dev->pdev[i];
2701                 if (!pdev)
2702                         continue;
2703
2704                 switch (pdev->device) {
2705                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2706                         pvt->pci_sad0 = pdev;
2707                         break;
2708                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2709                         pvt->pci_sad1 = pdev;
2710                         break;
2711                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2712                         pvt->pci_ha0 = pdev;
2713                         break;
2714                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2715                         pvt->pci_ta = pdev;
2716                         break;
2717                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
2718                         pvt->pci_ras = pdev;
2719                         break;
2720                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2721                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2722                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2723                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2724                 {
2725                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
2726                         pvt->pci_tad[id] = pdev;
2727                         saw_chan_mask |= 1 << id;
2728                 }
2729                         break;
2730                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2731                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2732                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2733                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2734                 {
2735                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2736                         pvt->pci_tad[id] = pdev;
2737                         saw_chan_mask |= 1 << id;
2738                 }
2739                         break;
2740                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2741                         pvt->pci_ddrio = pdev;
2742                         break;
2743                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2744                         pvt->pci_ha1 = pdev;
2745                         break;
2746                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2747                         pvt->pci_ha1_ta = pdev;
2748                         break;
2749                 default:
2750                         break;
2751                 }
2752
2753                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2754                          sbridge_dev->bus,
2755                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2756                          pdev);
2757         }
2758
2759         /* Check if everything were registered */
2760         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2761             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2762                 goto enodev;
2763
2764         if (saw_chan_mask != 0x0f && /* -EN */
2765             saw_chan_mask != 0x33 && /* -EP */
2766             saw_chan_mask != 0xff)   /* -EX */
2767                 goto enodev;
2768         return 0;
2769
2770 enodev:
2771         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2772         return -ENODEV;
2773 }
2774
2775 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2776                         struct sbridge_dev *sbridge_dev)
2777 {
2778         struct sbridge_pvt *pvt = mci->pvt_info;
2779         struct pci_dev *pdev;
2780         int dev, func;
2781
2782         int i;
2783         int devidx;
2784
2785         for (i = 0; i < sbridge_dev->n_devs; i++) {
2786                 pdev = sbridge_dev->pdev[i];
2787                 if (!pdev)
2788                         continue;
2789
2790                 /* Extract PCI device and function. */
2791                 dev = (pdev->devfn >> 3) & 0x1f;
2792                 func = pdev->devfn & 0x7;
2793
2794                 switch (pdev->device) {
2795                 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2796                         if (dev == 8)
2797                                 pvt->knl.pci_mc0 = pdev;
2798                         else if (dev == 9)
2799                                 pvt->knl.pci_mc1 = pdev;
2800                         else {
2801                                 sbridge_printk(KERN_ERR,
2802                                         "Memory controller in unexpected place! (dev %d, fn %d)\n",
2803                                         dev, func);
2804                                 continue;
2805                         }
2806                         break;
2807
2808                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2809                         pvt->pci_sad0 = pdev;
2810                         break;
2811
2812                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2813                         pvt->pci_sad1 = pdev;
2814                         break;
2815
2816                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2817                         /* There are one of these per tile, and range from
2818                          * 1.14.0 to 1.18.5.
2819                          */
2820                         devidx = ((dev-14)*8)+func;
2821
2822                         if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2823                                 sbridge_printk(KERN_ERR,
2824                                         "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2825                                         dev, func);
2826                                 continue;
2827                         }
2828
2829                         WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2830
2831                         pvt->knl.pci_cha[devidx] = pdev;
2832                         break;
2833
2834                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL:
2835                         devidx = -1;
2836
2837                         /*
2838                          *  MC0 channels 0-2 are device 9 function 2-4,
2839                          *  MC1 channels 3-5 are device 8 function 2-4.
2840                          */
2841
2842                         if (dev == 9)
2843                                 devidx = func-2;
2844                         else if (dev == 8)
2845                                 devidx = 3 + (func-2);
2846
2847                         if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2848                                 sbridge_printk(KERN_ERR,
2849                                         "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2850                                         dev, func);
2851                                 continue;
2852                         }
2853
2854                         WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2855                         pvt->knl.pci_channel[devidx] = pdev;
2856                         break;
2857
2858                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2859                         pvt->knl.pci_mc_info = pdev;
2860                         break;
2861
2862                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2863                         pvt->pci_ta = pdev;
2864                         break;
2865
2866                 default:
2867                         sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2868                                 pdev->device);
2869                         break;
2870                 }
2871         }
2872
2873         if (!pvt->knl.pci_mc0  || !pvt->knl.pci_mc1 ||
2874             !pvt->pci_sad0     || !pvt->pci_sad1    ||
2875             !pvt->pci_ta) {
2876                 goto enodev;
2877         }
2878
2879         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2880                 if (!pvt->knl.pci_channel[i]) {
2881                         sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2882                         goto enodev;
2883                 }
2884         }
2885
2886         for (i = 0; i < KNL_MAX_CHAS; i++) {
2887                 if (!pvt->knl.pci_cha[i]) {
2888                         sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2889                         goto enodev;
2890                 }
2891         }
2892
2893         return 0;
2894
2895 enodev:
2896         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2897         return -ENODEV;
2898 }
2899
2900 /****************************************************************************
2901                         Error check routines
2902  ****************************************************************************/
2903
2904 /*
2905  * While Sandy Bridge has error count registers, SMI BIOS read values from
2906  * and resets the counters. So, they are not reliable for the OS to read
2907  * from them. So, we have no option but to just trust on whatever MCE is
2908  * telling us about the errors.
2909  */
2910 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2911                                     const struct mce *m)
2912 {
2913         struct mem_ctl_info *new_mci;
2914         struct sbridge_pvt *pvt = mci->pvt_info;
2915         enum hw_event_mc_err_type tp_event;
2916         char *type, *optype, msg[256];
2917         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2918         bool overflow = GET_BITFIELD(m->status, 62, 62);
2919         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2920         bool recoverable;
2921         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2922         u32 mscod = GET_BITFIELD(m->status, 16, 31);
2923         u32 errcode = GET_BITFIELD(m->status, 0, 15);
2924         u32 channel = GET_BITFIELD(m->status, 0, 3);
2925         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2926         long channel_mask, first_channel;
2927         u8  rank, socket, ha;
2928         int rc, dimm;
2929         char *area_type = NULL;
2930
2931         if (pvt->info.type != SANDY_BRIDGE)
2932                 recoverable = true;
2933         else
2934                 recoverable = GET_BITFIELD(m->status, 56, 56);
2935
2936         if (uncorrected_error) {
2937                 if (ripv) {
2938                         type = "FATAL";
2939                         tp_event = HW_EVENT_ERR_FATAL;
2940                 } else {
2941                         type = "NON_FATAL";
2942                         tp_event = HW_EVENT_ERR_UNCORRECTED;
2943                 }
2944         } else {
2945                 type = "CORRECTED";
2946                 tp_event = HW_EVENT_ERR_CORRECTED;
2947         }
2948
2949         /*
2950          * According with Table 15-9 of the Intel Architecture spec vol 3A,
2951          * memory errors should fit in this mask:
2952          *      000f 0000 1mmm cccc (binary)
2953          * where:
2954          *      f = Correction Report Filtering Bit. If 1, subsequent errors
2955          *          won't be shown
2956          *      mmm = error type
2957          *      cccc = channel
2958          * If the mask doesn't match, report an error to the parsing logic
2959          */
2960         if (! ((errcode & 0xef80) == 0x80)) {
2961                 optype = "Can't parse: it is not a mem";
2962         } else {
2963                 switch (optypenum) {
2964                 case 0:
2965                         optype = "generic undef request error";
2966                         break;
2967                 case 1:
2968                         optype = "memory read error";
2969                         break;
2970                 case 2:
2971                         optype = "memory write error";
2972                         break;
2973                 case 3:
2974                         optype = "addr/cmd error";
2975                         break;
2976                 case 4:
2977                         optype = "memory scrubbing error";
2978                         break;
2979                 default:
2980                         optype = "reserved";
2981                         break;
2982                 }
2983         }
2984
2985         /* Only decode errors with an valid address (ADDRV) */
2986         if (!GET_BITFIELD(m->status, 58, 58))
2987                 return;
2988
2989         if (pvt->info.type == KNIGHTS_LANDING) {
2990                 if (channel == 14) {
2991                         edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
2992                                 overflow ? " OVERFLOW" : "",
2993                                 (uncorrected_error && recoverable)
2994                                 ? " recoverable" : "",
2995                                 mscod, errcode,
2996                                 m->bank);
2997                 } else {
2998                         char A = *("A");
2999
3000                         /*
3001                          * Reported channel is in range 0-2, so we can't map it
3002                          * back to mc. To figure out mc we check machine check
3003                          * bank register that reported this error.
3004                          * bank15 means mc0 and bank16 means mc1.
3005                          */
3006                         channel = knl_channel_remap(m->bank == 16, channel);
3007                         channel_mask = 1 << channel;
3008
3009                         snprintf(msg, sizeof(msg),
3010                                 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3011                                 overflow ? " OVERFLOW" : "",
3012                                 (uncorrected_error && recoverable)
3013                                 ? " recoverable" : " ",
3014                                 mscod, errcode, channel, A + channel);
3015                         edac_mc_handle_error(tp_event, mci, core_err_cnt,
3016                                 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3017                                 channel, 0, -1,
3018                                 optype, msg);
3019                 }
3020                 return;
3021         } else {
3022                 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3023                                 &channel_mask, &rank, &area_type, msg);
3024         }
3025
3026         if (rc < 0)
3027                 goto err_parsing;
3028         new_mci = get_mci_for_node_id(socket);
3029         if (!new_mci) {
3030                 strcpy(msg, "Error: socket got corrupted!");
3031                 goto err_parsing;
3032         }
3033         mci = new_mci;
3034         pvt = mci->pvt_info;
3035
3036         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3037
3038         if (rank < 4)
3039                 dimm = 0;
3040         else if (rank < 8)
3041                 dimm = 1;
3042         else
3043                 dimm = 2;
3044
3045
3046         /*
3047          * FIXME: On some memory configurations (mirror, lockstep), the
3048          * Memory Controller can't point the error to a single DIMM. The
3049          * EDAC core should be handling the channel mask, in order to point
3050          * to the group of dimm's where the error may be happening.
3051          */
3052         if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
3053                 channel = first_channel;
3054
3055         snprintf(msg, sizeof(msg),
3056                  "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3057                  overflow ? " OVERFLOW" : "",
3058                  (uncorrected_error && recoverable) ? " recoverable" : "",
3059                  area_type,
3060                  mscod, errcode,
3061                  socket, ha,
3062                  channel_mask,
3063                  rank);
3064
3065         edac_dbg(0, "%s\n", msg);
3066
3067         /* FIXME: need support for channel mask */
3068
3069         if (channel == CHANNEL_UNSPECIFIED)
3070                 channel = -1;
3071
3072         /* Call the helper to output message */
3073         edac_mc_handle_error(tp_event, mci, core_err_cnt,
3074                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3075                              4*ha+channel, dimm, -1,
3076                              optype, msg);
3077         return;
3078 err_parsing:
3079         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3080                              -1, -1, -1,
3081                              msg, "");
3082
3083 }
3084
3085 /*
3086  * Check that logging is enabled and that this is the right type
3087  * of error for us to handle.
3088  */
3089 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3090                                    void *data)
3091 {
3092         struct mce *mce = (struct mce *)data;
3093         struct mem_ctl_info *mci;
3094         struct sbridge_pvt *pvt;
3095         char *type;
3096
3097         if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3098                 return NOTIFY_DONE;
3099
3100         mci = get_mci_for_node_id(mce->socketid);
3101         if (!mci)
3102                 return NOTIFY_DONE;
3103         pvt = mci->pvt_info;
3104
3105         /*
3106          * Just let mcelog handle it if the error is
3107          * outside the memory controller. A memory error
3108          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3109          * bit 12 has an special meaning.
3110          */
3111         if ((mce->status & 0xefff) >> 7 != 1)
3112                 return NOTIFY_DONE;
3113
3114         if (mce->mcgstatus & MCG_STATUS_MCIP)
3115                 type = "Exception";
3116         else
3117                 type = "Event";
3118
3119         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3120
3121         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3122                           "Bank %d: %016Lx\n", mce->extcpu, type,
3123                           mce->mcgstatus, mce->bank, mce->status);
3124         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3125         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3126         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3127
3128         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3129                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3130                           mce->time, mce->socketid, mce->apicid);
3131
3132         sbridge_mce_output_error(mci, mce);
3133
3134         /* Advice mcelog that the error were handled */
3135         return NOTIFY_STOP;
3136 }
3137
3138 static struct notifier_block sbridge_mce_dec = {
3139         .notifier_call      = sbridge_mce_check_error,
3140 };
3141
3142 /****************************************************************************
3143                         EDAC register/unregister logic
3144  ****************************************************************************/
3145
3146 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3147 {
3148         struct mem_ctl_info *mci = sbridge_dev->mci;
3149         struct sbridge_pvt *pvt;
3150
3151         if (unlikely(!mci || !mci->pvt_info)) {
3152                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3153
3154                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3155                 return;
3156         }
3157
3158         pvt = mci->pvt_info;
3159
3160         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3161                  mci, &sbridge_dev->pdev[0]->dev);
3162
3163         /* Remove MC sysfs nodes */
3164         edac_mc_del_mc(mci->pdev);
3165
3166         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3167         kfree(mci->ctl_name);
3168         edac_mc_free(mci);
3169         sbridge_dev->mci = NULL;
3170 }
3171
3172 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3173 {
3174         struct mem_ctl_info *mci;
3175         struct edac_mc_layer layers[2];
3176         struct sbridge_pvt *pvt;
3177         struct pci_dev *pdev = sbridge_dev->pdev[0];
3178         int rc;
3179
3180         /* Check the number of active and not disabled channels */
3181         rc = check_if_ecc_is_active(sbridge_dev->bus, type);
3182         if (unlikely(rc < 0))
3183                 return rc;
3184
3185         /* allocate a new MC control structure */
3186         layers[0].type = EDAC_MC_LAYER_CHANNEL;
3187         layers[0].size = type == KNIGHTS_LANDING ?
3188                 KNL_MAX_CHANNELS : NUM_CHANNELS;
3189         layers[0].is_virt_csrow = false;
3190         layers[1].type = EDAC_MC_LAYER_SLOT;
3191         layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3192         layers[1].is_virt_csrow = true;
3193         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3194                             sizeof(*pvt));
3195
3196         if (unlikely(!mci))
3197                 return -ENOMEM;
3198
3199         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3200                  mci, &pdev->dev);
3201
3202         pvt = mci->pvt_info;
3203         memset(pvt, 0, sizeof(*pvt));
3204
3205         /* Associate sbridge_dev and mci for future usage */
3206         pvt->sbridge_dev = sbridge_dev;
3207         sbridge_dev->mci = mci;
3208
3209         mci->mtype_cap = type == KNIGHTS_LANDING ?
3210                 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3211         mci->edac_ctl_cap = EDAC_FLAG_NONE;
3212         mci->edac_cap = EDAC_FLAG_NONE;
3213         mci->mod_name = "sbridge_edac.c";
3214         mci->mod_ver = SBRIDGE_REVISION;
3215         mci->dev_name = pci_name(pdev);
3216         mci->ctl_page_to_phys = NULL;
3217
3218         pvt->info.type = type;
3219         switch (type) {
3220         case IVY_BRIDGE:
3221                 pvt->info.rankcfgr = IB_RANK_CFG_A;
3222                 pvt->info.get_tolm = ibridge_get_tolm;
3223                 pvt->info.get_tohm = ibridge_get_tohm;
3224                 pvt->info.dram_rule = ibridge_dram_rule;
3225                 pvt->info.get_memory_type = get_memory_type;
3226                 pvt->info.get_node_id = get_node_id;
3227                 pvt->info.rir_limit = rir_limit;
3228                 pvt->info.sad_limit = sad_limit;
3229                 pvt->info.interleave_mode = interleave_mode;
3230                 pvt->info.show_interleave_mode = show_interleave_mode;
3231                 pvt->info.dram_attr = dram_attr;
3232                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3233                 pvt->info.interleave_list = ibridge_interleave_list;
3234                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3235                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3236                 pvt->info.get_width = ibridge_get_width;
3237                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
3238
3239                 /* Store pci devices at mci for faster access */
3240                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3241                 if (unlikely(rc < 0))
3242                         goto fail0;
3243                 break;
3244         case SANDY_BRIDGE:
3245                 pvt->info.rankcfgr = SB_RANK_CFG_A;
3246                 pvt->info.get_tolm = sbridge_get_tolm;
3247                 pvt->info.get_tohm = sbridge_get_tohm;
3248                 pvt->info.dram_rule = sbridge_dram_rule;
3249                 pvt->info.get_memory_type = get_memory_type;
3250                 pvt->info.get_node_id = get_node_id;
3251                 pvt->info.rir_limit = rir_limit;
3252                 pvt->info.sad_limit = sad_limit;
3253                 pvt->info.interleave_mode = interleave_mode;
3254                 pvt->info.show_interleave_mode = show_interleave_mode;
3255                 pvt->info.dram_attr = dram_attr;
3256                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3257                 pvt->info.interleave_list = sbridge_interleave_list;
3258                 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
3259                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3260                 pvt->info.get_width = sbridge_get_width;
3261                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
3262
3263                 /* Store pci devices at mci for faster access */
3264                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3265                 if (unlikely(rc < 0))
3266                         goto fail0;
3267                 break;
3268         case HASWELL:
3269                 /* rankcfgr isn't used */
3270                 pvt->info.get_tolm = haswell_get_tolm;
3271                 pvt->info.get_tohm = haswell_get_tohm;
3272                 pvt->info.dram_rule = ibridge_dram_rule;
3273                 pvt->info.get_memory_type = haswell_get_memory_type;
3274                 pvt->info.get_node_id = haswell_get_node_id;
3275                 pvt->info.rir_limit = haswell_rir_limit;
3276                 pvt->info.sad_limit = sad_limit;
3277                 pvt->info.interleave_mode = interleave_mode;
3278                 pvt->info.show_interleave_mode = show_interleave_mode;
3279                 pvt->info.dram_attr = dram_attr;
3280                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3281                 pvt->info.interleave_list = ibridge_interleave_list;
3282                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3283                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3284                 pvt->info.get_width = ibridge_get_width;
3285                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
3286
3287                 /* Store pci devices at mci for faster access */
3288                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3289                 if (unlikely(rc < 0))
3290                         goto fail0;
3291                 break;
3292         case BROADWELL:
3293                 /* rankcfgr isn't used */
3294                 pvt->info.get_tolm = haswell_get_tolm;
3295                 pvt->info.get_tohm = haswell_get_tohm;
3296                 pvt->info.dram_rule = ibridge_dram_rule;
3297                 pvt->info.get_memory_type = haswell_get_memory_type;
3298                 pvt->info.get_node_id = haswell_get_node_id;
3299                 pvt->info.rir_limit = haswell_rir_limit;
3300                 pvt->info.sad_limit = sad_limit;
3301                 pvt->info.interleave_mode = interleave_mode;
3302                 pvt->info.show_interleave_mode = show_interleave_mode;
3303                 pvt->info.dram_attr = dram_attr;
3304                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3305                 pvt->info.interleave_list = ibridge_interleave_list;
3306                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3307                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3308                 pvt->info.get_width = broadwell_get_width;
3309                 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
3310
3311                 /* Store pci devices at mci for faster access */
3312                 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3313                 if (unlikely(rc < 0))
3314                         goto fail0;
3315                 break;
3316         case KNIGHTS_LANDING:
3317                 /* pvt->info.rankcfgr == ??? */
3318                 pvt->info.get_tolm = knl_get_tolm;
3319                 pvt->info.get_tohm = knl_get_tohm;
3320                 pvt->info.dram_rule = knl_dram_rule;
3321                 pvt->info.get_memory_type = knl_get_memory_type;
3322                 pvt->info.get_node_id = knl_get_node_id;
3323                 pvt->info.rir_limit = NULL;
3324                 pvt->info.sad_limit = knl_sad_limit;
3325                 pvt->info.interleave_mode = knl_interleave_mode;
3326                 pvt->info.show_interleave_mode = knl_show_interleave_mode;
3327                 pvt->info.dram_attr = dram_attr_knl;
3328                 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3329                 pvt->info.interleave_list = knl_interleave_list;
3330                 pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
3331                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3332                 pvt->info.get_width = knl_get_width;
3333                 mci->ctl_name = kasprintf(GFP_KERNEL,
3334                         "Knights Landing Socket#%d", mci->mc_idx);
3335
3336                 rc = knl_mci_bind_devs(mci, sbridge_dev);
3337                 if (unlikely(rc < 0))
3338                         goto fail0;
3339                 break;
3340         }
3341
3342         /* Get dimm basic config and the memory layout */
3343         get_dimm_config(mci);
3344         get_memory_layout(mci);
3345
3346         /* record ptr to the generic device */
3347         mci->pdev = &pdev->dev;
3348
3349         /* add this new MC control structure to EDAC's list of MCs */
3350         if (unlikely(edac_mc_add_mc(mci))) {
3351                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3352                 rc = -EINVAL;
3353                 goto fail0;
3354         }
3355
3356         return 0;
3357
3358 fail0:
3359         kfree(mci->ctl_name);
3360         edac_mc_free(mci);
3361         sbridge_dev->mci = NULL;
3362         return rc;
3363 }
3364
3365 #define ICPU(model, table) \
3366         { X86_VENDOR_INTEL, 6, model, 0, (unsigned long)&table }
3367
3368 static const struct x86_cpu_id sbridge_cpuids[] = {
3369         ICPU(INTEL_FAM6_SANDYBRIDGE_X,    pci_dev_descr_sbridge_table),
3370         ICPU(INTEL_FAM6_IVYBRIDGE_X,      pci_dev_descr_ibridge_table),
3371         ICPU(INTEL_FAM6_HASWELL_X,        pci_dev_descr_haswell_table),
3372         ICPU(INTEL_FAM6_BROADWELL_X,      pci_dev_descr_broadwell_table),
3373         ICPU(INTEL_FAM6_BROADWELL_XEON_D, pci_dev_descr_broadwell_table),
3374         ICPU(INTEL_FAM6_XEON_PHI_KNL,     pci_dev_descr_knl_table),
3375         ICPU(INTEL_FAM6_XEON_PHI_KNM,     pci_dev_descr_knl_table),
3376         { }
3377 };
3378 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3379
3380 /*
3381  *      sbridge_probe   Get all devices and register memory controllers
3382  *                      present.
3383  *      return:
3384  *              0 for FOUND a device
3385  *              < 0 for error code
3386  */
3387
3388 static int sbridge_probe(const struct x86_cpu_id *id)
3389 {
3390         int rc = -ENODEV;
3391         u8 mc, num_mc = 0;
3392         struct sbridge_dev *sbridge_dev;
3393         struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
3394
3395         /* get the pci devices we want to reserve for our use */
3396         rc = sbridge_get_all_devices(&num_mc, ptable);
3397
3398         if (unlikely(rc < 0)) {
3399                 edac_dbg(0, "couldn't get all devices\n");
3400                 goto fail0;
3401         }
3402
3403         mc = 0;
3404
3405         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3406                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3407                          mc, mc + 1, num_mc);
3408
3409                 sbridge_dev->mc = mc++;
3410                 rc = sbridge_register_mci(sbridge_dev, ptable->type);
3411                 if (unlikely(rc < 0))
3412                         goto fail1;
3413         }
3414
3415         sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3416
3417         return 0;
3418
3419 fail1:
3420         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3421                 sbridge_unregister_mci(sbridge_dev);
3422
3423         sbridge_put_all_devices();
3424 fail0:
3425         return rc;
3426 }
3427
3428 /*
3429  *      sbridge_remove  cleanup
3430  *
3431  */
3432 static void sbridge_remove(void)
3433 {
3434         struct sbridge_dev *sbridge_dev;
3435
3436         edac_dbg(0, "\n");
3437
3438         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3439                 sbridge_unregister_mci(sbridge_dev);
3440
3441         /* Release PCI resources */
3442         sbridge_put_all_devices();
3443 }
3444
3445 /*
3446  *      sbridge_init            Module entry function
3447  *                      Try to initialize this module for its devices
3448  */
3449 static int __init sbridge_init(void)
3450 {
3451         const struct x86_cpu_id *id;
3452         int rc;
3453
3454         edac_dbg(2, "\n");
3455
3456         id = x86_match_cpu(sbridge_cpuids);
3457         if (!id)
3458                 return -ENODEV;
3459
3460         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3461         opstate_init();
3462
3463         rc = sbridge_probe(id);
3464
3465         if (rc >= 0) {
3466                 mce_register_decode_chain(&sbridge_mce_dec);
3467                 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3468                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3469                 return 0;
3470         }
3471
3472         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3473                       rc);
3474
3475         return rc;
3476 }
3477
3478 /*
3479  *      sbridge_exit()  Module exit function
3480  *                      Unregister the driver
3481  */
3482 static void __exit sbridge_exit(void)
3483 {
3484         edac_dbg(2, "\n");
3485         sbridge_remove();
3486         mce_unregister_decode_chain(&sbridge_mce_dec);
3487 }
3488
3489 module_init(sbridge_init);
3490 module_exit(sbridge_exit);
3491
3492 module_param(edac_op_state, int, 0444);
3493 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3494
3495 MODULE_LICENSE("GPL");
3496 MODULE_AUTHOR("Mauro Carvalho Chehab");
3497 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3498 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
3499                    SBRIDGE_REVISION);