1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
4 * This driver supports the memory controllers found on the Intel
5 * processor family Sandy Bridge.
7 * Copyright (c) 2011 by:
8 * Mauro Carvalho Chehab
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pci_ids.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/edac.h>
18 #include <linux/mmzone.h>
19 #include <linux/smp.h>
20 #include <linux/bitmap.h>
21 #include <linux/math64.h>
22 #include <linux/mod_devicetable.h>
23 #include <asm/cpu_device_id.h>
24 #include <asm/intel-family.h>
25 #include <asm/processor.h>
28 #include "edac_module.h"
31 static LIST_HEAD(sbridge_edac_list);
34 * Alter this version for the module when modifications are made
36 #define SBRIDGE_REVISION " Ver: 1.1.2 "
37 #define EDAC_MOD_STR "sb_edac"
42 #define sbridge_printk(level, fmt, arg...) \
43 edac_printk(level, "sbridge", fmt, ##arg)
45 #define sbridge_mc_printk(mci, level, fmt, arg...) \
46 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
49 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 #define GET_BITFIELD(v, lo, hi) \
52 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
54 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
55 static const u32 sbridge_dram_rule[] = {
56 0x80, 0x88, 0x90, 0x98, 0xa0,
57 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
60 static const u32 ibridge_dram_rule[] = {
61 0x60, 0x68, 0x70, 0x78, 0x80,
62 0x88, 0x90, 0x98, 0xa0, 0xa8,
63 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
64 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
67 static const u32 knl_dram_rule[] = {
68 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
69 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
70 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
71 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
72 0x100, 0x108, 0x110, 0x118, /* 20-23 */
75 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
76 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
78 static char *show_dram_attr(u32 attr)
92 static const u32 sbridge_interleave_list[] = {
93 0x84, 0x8c, 0x94, 0x9c, 0xa4,
94 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
97 static const u32 ibridge_interleave_list[] = {
98 0x64, 0x6c, 0x74, 0x7c, 0x84,
99 0x8c, 0x94, 0x9c, 0xa4, 0xac,
100 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
101 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
104 static const u32 knl_interleave_list[] = {
105 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
106 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
107 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
108 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
109 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
111 #define MAX_INTERLEAVE \
112 (max_t(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \
113 max_t(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \
114 ARRAY_SIZE(knl_interleave_list))))
116 struct interleave_pkg {
121 static const struct interleave_pkg sbridge_interleave_pkg[] = {
132 static const struct interleave_pkg ibridge_interleave_pkg[] = {
143 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
146 return GET_BITFIELD(reg, table[interleave].start,
147 table[interleave].end);
150 /* Devices 12 Function 7 */
154 #define HASWELL_TOLM 0xd0
155 #define HASWELL_TOHM_0 0xd4
156 #define HASWELL_TOHM_1 0xd8
157 #define KNL_TOLM 0xd0
158 #define KNL_TOHM_0 0xd4
159 #define KNL_TOHM_1 0xd8
161 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
162 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
164 /* Device 13 Function 6 */
166 #define SAD_TARGET 0xf0
168 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
170 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
172 #define SAD_CONTROL 0xf4
174 /* Device 14 function 0 */
176 static const u32 tad_dram_rule[] = {
177 0x40, 0x44, 0x48, 0x4c,
178 0x50, 0x54, 0x58, 0x5c,
179 0x60, 0x64, 0x68, 0x6c,
181 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
183 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
184 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
185 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
186 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
187 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
188 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
189 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
191 /* Device 15, function 0 */
194 #define KNL_MCMTR 0x624
196 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
197 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
198 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
200 /* Device 15, function 1 */
202 #define RASENABLES 0xac
203 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
205 /* Device 15, functions 2-5 */
207 static const int mtr_regs[] = {
211 static const int knl_mtr_reg = 0xb60;
213 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
214 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
215 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
216 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
217 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
219 static const u32 tad_ch_nilv_offset[] = {
220 0x90, 0x94, 0x98, 0x9c,
221 0xa0, 0xa4, 0xa8, 0xac,
222 0xb0, 0xb4, 0xb8, 0xbc,
224 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
225 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
227 static const u32 rir_way_limit[] = {
228 0x108, 0x10c, 0x110, 0x114, 0x118,
230 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
232 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
233 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
235 #define MAX_RIR_WAY 8
237 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
238 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
239 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
240 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
241 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
242 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
245 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
246 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
248 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
249 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
251 /* Device 16, functions 2-7 */
254 * FIXME: Implement the error count reads directly
257 static const u32 correrrcnt[] = {
258 0x104, 0x108, 0x10c, 0x110,
261 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
262 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
263 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
264 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
266 static const u32 correrrthrsld[] = {
267 0x11c, 0x120, 0x124, 0x128,
270 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
271 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
274 /* Device 17, function 0 */
276 #define SB_RANK_CFG_A 0x0328
278 #define IB_RANK_CFG_A 0x0320
284 #define NUM_CHANNELS 6 /* Max channels per MC */
285 #define MAX_DIMMS 3 /* Max DIMMS per channel */
286 #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */
287 #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */
288 #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */
289 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
305 enum mirroring_mode {
307 ADDR_RANGE_MIRRORING,
312 struct sbridge_info {
316 u64 (*get_tolm)(struct sbridge_pvt *pvt);
317 u64 (*get_tohm)(struct sbridge_pvt *pvt);
318 u64 (*rir_limit)(u32 reg);
319 u64 (*sad_limit)(u32 reg);
320 u32 (*interleave_mode)(u32 reg);
321 u32 (*dram_attr)(u32 reg);
322 const u32 *dram_rule;
323 const u32 *interleave_list;
324 const struct interleave_pkg *interleave_pkg;
326 u8 (*get_node_id)(struct sbridge_pvt *pvt);
327 u8 (*get_ha)(u8 bank);
328 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
329 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
330 struct pci_dev *pci_vtd;
333 struct sbridge_channel {
338 struct pci_id_descr {
344 struct pci_id_table {
345 const struct pci_id_descr *descr;
353 struct list_head list;
356 u8 node_id, source_id;
357 struct pci_dev **pdev;
361 struct mem_ctl_info *mci;
365 struct pci_dev *pci_cha[KNL_MAX_CHAS];
366 struct pci_dev *pci_channel[KNL_MAX_CHANNELS];
367 struct pci_dev *pci_mc0;
368 struct pci_dev *pci_mc1;
369 struct pci_dev *pci_mc0_misc;
370 struct pci_dev *pci_mc1_misc;
371 struct pci_dev *pci_mc_info; /* tolm, tohm */
375 /* Devices per socket */
376 struct pci_dev *pci_ddrio;
377 struct pci_dev *pci_sad0, *pci_sad1;
378 struct pci_dev *pci_br0, *pci_br1;
379 /* Devices per memory controller */
380 struct pci_dev *pci_ha, *pci_ta, *pci_ras;
381 struct pci_dev *pci_tad[NUM_CHANNELS];
383 struct sbridge_dev *sbridge_dev;
385 struct sbridge_info info;
386 struct sbridge_channel channel[NUM_CHANNELS];
388 /* Memory type detection */
389 bool is_cur_addr_mirrored, is_lockstep, is_close_pg;
391 enum mirroring_mode mirror_mode;
393 /* Memory description */
398 #define PCI_DESCR(device_id, opt, domain) \
399 .dev_id = (device_id), \
403 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
404 /* Processor Home Agent */
405 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) },
407 /* Memory controller */
408 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) },
409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) },
410 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) },
411 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) },
412 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) },
413 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) },
414 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) },
416 /* System Address Decoder */
417 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) },
418 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) },
420 /* Broadcast Registers */
421 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) },
424 #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \
426 .n_devs_per_imc = N, \
427 .n_devs_per_sock = ARRAY_SIZE(A), \
428 .n_imcs_per_sock = M, \
432 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
433 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),
434 {0,} /* 0 terminated list. */
437 /* This changes depending if 1HA or 2HA:
439 * 0x0eb8 (17.0) is DDRIO0
441 * 0x0ebc (17.4) is DDRIO0
443 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
444 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
447 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
448 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
449 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
450 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
451 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
452 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
455 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
456 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
461 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
462 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
463 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
465 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
466 /* Processor Home Agent */
467 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) },
468 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) },
470 /* Memory controller */
471 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) },
472 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) },
473 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) },
474 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) },
475 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) },
476 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) },
478 /* Optional, mode 2HA */
479 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) },
480 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) },
481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) },
482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) },
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) },
484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) },
486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) },
487 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) },
489 /* System Address Decoder */
490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) },
492 /* Broadcast Registers */
493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) },
494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) },
498 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
499 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),
500 {0,} /* 0 terminated list. */
503 /* Haswell support */
506 * - 3 DDR3 channels, 2 DPC per channel
509 * - 4 DDR4 channels, 3 DPC per channel
512 * - 4 DDR4 channels, 3 DPC per channel
515 * - each IMC interfaces with a SMI 2 channel
516 * - each SMI channel interfaces with a scalable memory buffer
517 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
519 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
520 #define HASWELL_HASYSDEFEATURE2 0x84
521 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
522 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
523 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
524 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
525 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71
526 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
527 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79
528 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
529 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
530 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
539 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
540 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
541 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
542 static const struct pci_id_descr pci_dev_descr_haswell[] = {
543 /* first item must be the HA */
544 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) },
545 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) },
547 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) },
548 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) },
549 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) },
550 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) },
551 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) },
552 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) },
554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) },
555 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) },
556 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) },
557 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) },
558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) },
559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) },
561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) },
562 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) },
563 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) },
564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) },
565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) },
566 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) },
569 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
570 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),
571 {0,} /* 0 terminated list. */
574 /* Knight's Landing Support */
576 * KNL's memory channels are swizzled between memory controllers.
577 * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
579 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
581 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
582 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840
583 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
584 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843
585 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
586 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844
587 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
588 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a
589 /* SAD target - 1-29-1 (1 of these) */
590 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b
591 /* Caching / Home Agent */
592 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c
593 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
594 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810
597 * KNL differs from SB, IB, and Haswell in that it has multiple
598 * instances of the same device with the same device ID, so we handle that
599 * by creating as many copies in the table as we expect to find.
600 * (Like device ID must be grouped together.)
603 static const struct pci_id_descr pci_dev_descr_knl[] = {
604 [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)},
605 [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) },
606 [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) },
607 [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) },
608 [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) },
609 [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) },
610 [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) },
613 static const struct pci_id_table pci_dev_descr_knl_table[] = {
614 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),
623 * - 2 DDR3 channels, 2 DPC per channel
626 * - 4 DDR4 channels, 3 DPC per channel
629 * - 4 DDR4 channels, 3 DPC per channel
632 * - each IMC interfaces with a SMI 2 channel
633 * - each SMI channel interfaces with a scalable memory buffer
634 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
636 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
637 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
638 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
639 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
640 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71
641 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
642 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79
643 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
644 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
645 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
651 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
652 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
653 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
655 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
656 /* first item must be the HA */
657 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) },
658 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) },
660 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) },
661 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) },
662 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) },
663 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) },
664 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) },
665 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) },
667 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) },
668 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) },
669 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) },
670 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) },
671 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) },
672 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) },
674 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) },
675 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) },
676 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) },
679 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
680 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),
681 {0,} /* 0 terminated list. */
685 /****************************************************************************
686 Ancillary status routines
687 ****************************************************************************/
689 static inline int numrank(enum type type, u32 mtr)
691 int ranks = (1 << RANK_CNT_BITS(mtr));
694 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
698 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
699 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
706 static inline int numrow(u32 mtr)
708 int rows = (RANK_WIDTH_BITS(mtr) + 12);
710 if (rows < 13 || rows > 18) {
711 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
712 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
719 static inline int numcol(u32 mtr)
721 int cols = (COL_WIDTH_BITS(mtr) + 10);
724 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
725 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
732 static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom,
734 struct sbridge_dev *prev)
736 struct sbridge_dev *sbridge_dev;
739 * If we have devices scattered across several busses that pertain
740 * to the same memory controller, we'll lump them all together.
743 return list_first_entry_or_null(&sbridge_edac_list,
744 struct sbridge_dev, list);
747 sbridge_dev = list_entry(prev ? prev->list.next
748 : sbridge_edac_list.next, struct sbridge_dev, list);
750 list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) {
751 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) &&
752 (dom == SOCK || dom == sbridge_dev->dom))
759 static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom,
760 const struct pci_id_table *table)
762 struct sbridge_dev *sbridge_dev;
764 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
768 sbridge_dev->pdev = kcalloc(table->n_devs_per_imc,
769 sizeof(*sbridge_dev->pdev),
771 if (!sbridge_dev->pdev) {
776 sbridge_dev->seg = seg;
777 sbridge_dev->bus = bus;
778 sbridge_dev->dom = dom;
779 sbridge_dev->n_devs = table->n_devs_per_imc;
780 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
785 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
787 list_del(&sbridge_dev->list);
788 kfree(sbridge_dev->pdev);
792 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
796 /* Address range is 32:28 */
797 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
798 return GET_TOLM(reg);
801 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
805 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
806 return GET_TOHM(reg);
809 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
813 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
815 return GET_TOLM(reg);
818 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
822 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
824 return GET_TOHM(reg);
827 static u64 rir_limit(u32 reg)
829 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
832 static u64 sad_limit(u32 reg)
834 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
837 static u32 interleave_mode(u32 reg)
839 return GET_BITFIELD(reg, 1, 1);
842 static u32 dram_attr(u32 reg)
844 return GET_BITFIELD(reg, 2, 3);
847 static u64 knl_sad_limit(u32 reg)
849 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
852 static u32 knl_interleave_mode(u32 reg)
854 return GET_BITFIELD(reg, 1, 2);
857 static const char * const knl_intlv_mode[] = {
858 "[8:6]", "[10:8]", "[14:12]", "[32:30]"
861 static const char *get_intlv_mode_str(u32 reg, enum type t)
863 if (t == KNIGHTS_LANDING)
864 return knl_intlv_mode[knl_interleave_mode(reg)];
866 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
869 static u32 dram_attr_knl(u32 reg)
871 return GET_BITFIELD(reg, 3, 4);
875 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
880 if (pvt->pci_ddrio) {
881 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
883 if (GET_BITFIELD(reg, 11, 11))
884 /* FIXME: Can also be LRDIMM */
894 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
897 bool registered = false;
898 enum mem_type mtype = MEM_UNKNOWN;
903 pci_read_config_dword(pvt->pci_ddrio,
904 HASWELL_DDRCRCLKCONTROLS, ®);
906 if (GET_BITFIELD(reg, 16, 16))
909 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
910 if (GET_BITFIELD(reg, 14, 14)) {
926 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
928 /* for KNL value is fixed */
932 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
934 /* there's no way to figure out */
938 static enum dev_type __ibridge_get_width(u32 mtr)
960 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
963 * ddr3_width on the documentation but also valid for DDR4 on
966 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
969 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
971 /* ddr3_width on the documentation but also valid for DDR4 */
972 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
975 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
977 /* DDR4 RDIMMS and LRDIMMS are supported */
981 static u8 get_node_id(struct sbridge_pvt *pvt)
984 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
985 return GET_BITFIELD(reg, 0, 2);
988 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
992 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
993 return GET_BITFIELD(reg, 0, 3);
996 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
1000 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
1001 return GET_BITFIELD(reg, 0, 2);
1005 * Use the reporting bank number to determine which memory
1006 * controller (also known as "ha" for "home agent"). Sandy
1007 * Bridge only has one memory controller per socket, so the
1008 * answer is always zero.
1010 static u8 sbridge_get_ha(u8 bank)
1016 * On Ivy Bridge, Haswell and Broadwell the error may be in a
1017 * home agent bank (7, 8), or one of the per-channel memory
1018 * controller banks (9 .. 16).
1020 static u8 ibridge_get_ha(u8 bank)
1026 return (bank - 9) / 4;
1032 /* Not used, but included for safety/symmetry */
1033 static u8 knl_get_ha(u8 bank)
1038 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1042 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
1043 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1046 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1051 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
1052 rc = GET_BITFIELD(reg, 26, 31);
1053 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
1054 rc = ((reg << 6) | rc) << 26;
1056 return rc | 0x1ffffff;
1059 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1063 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®);
1064 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1067 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1072 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo);
1073 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi);
1074 rc = ((u64)reg_hi << 32) | reg_lo;
1075 return rc | 0x3ffffff;
1079 static u64 haswell_rir_limit(u32 reg)
1081 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
1084 static inline u8 sad_pkg_socket(u8 pkg)
1086 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1087 return ((pkg >> 3) << 2) | (pkg & 0x3);
1090 static inline u8 sad_pkg_ha(u8 pkg)
1092 return (pkg >> 2) & 0x1;
1095 static int haswell_chan_hash(int idx, u64 addr)
1100 * XOR even bits from 12:26 to bit0 of idx,
1101 * odd bits from 13:27 to bit1
1103 for (i = 12; i < 28; i += 2)
1104 idx ^= (addr >> i) & 3;
1109 /* Low bits of TAD limit, and some metadata. */
1110 static const u32 knl_tad_dram_limit_lo[] = {
1111 0x400, 0x500, 0x600, 0x700,
1112 0x800, 0x900, 0xa00, 0xb00,
1115 /* Low bits of TAD offset. */
1116 static const u32 knl_tad_dram_offset_lo[] = {
1117 0x404, 0x504, 0x604, 0x704,
1118 0x804, 0x904, 0xa04, 0xb04,
1121 /* High 16 bits of TAD limit and offset. */
1122 static const u32 knl_tad_dram_hi[] = {
1123 0x408, 0x508, 0x608, 0x708,
1124 0x808, 0x908, 0xa08, 0xb08,
1127 /* Number of ways a tad entry is interleaved. */
1128 static const u32 knl_tad_ways[] = {
1133 * Retrieve the n'th Target Address Decode table entry
1134 * from the memory controller's TAD table.
1136 * @pvt: driver private data
1137 * @entry: which entry you want to retrieve
1138 * @mc: which memory controller (0 or 1)
1139 * @offset: output tad range offset
1140 * @limit: output address of first byte above tad range
1141 * @ways: output number of interleave ways
1143 * The offset value has curious semantics. It's a sort of running total
1144 * of the sizes of all the memory regions that aren't mapped in this
1147 static int knl_get_tad(const struct sbridge_pvt *pvt,
1154 u32 reg_limit_lo, reg_offset_lo, reg_hi;
1155 struct pci_dev *pci_mc;
1160 pci_mc = pvt->knl.pci_mc0;
1163 pci_mc = pvt->knl.pci_mc1;
1170 pci_read_config_dword(pci_mc,
1171 knl_tad_dram_limit_lo[entry], ®_limit_lo);
1172 pci_read_config_dword(pci_mc,
1173 knl_tad_dram_offset_lo[entry], ®_offset_lo);
1174 pci_read_config_dword(pci_mc,
1175 knl_tad_dram_hi[entry], ®_hi);
1177 /* Is this TAD entry enabled? */
1178 if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1181 way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1183 if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1184 *ways = knl_tad_ways[way_id];
1187 sbridge_printk(KERN_ERR,
1188 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1194 * The least significant 6 bits of base and limit are truncated.
1195 * For limit, we fill the missing bits with 1s.
1197 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1198 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32);
1199 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 |
1200 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1205 /* Determine which memory controller is responsible for a given channel. */
1206 static int knl_channel_mc(int channel)
1208 WARN_ON(channel < 0 || channel >= 6);
1210 return channel < 3 ? 1 : 0;
1214 * Get the Nth entry from EDC_ROUTE_TABLE register.
1215 * (This is the per-tile mapping of logical interleave targets to
1216 * physical EDC modules.)
1228 static u32 knl_get_edc_route(int entry, u32 reg)
1230 WARN_ON(entry >= KNL_MAX_EDCS);
1231 return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1235 * Get the Nth entry from MC_ROUTE_TABLE register.
1236 * (This is the per-tile mapping of logical interleave targets to
1237 * physical DRAM channels modules.)
1239 * entry 0: mc 0:2 channel 18:19
1240 * 1: mc 3:5 channel 20:21
1241 * 2: mc 6:8 channel 22:23
1242 * 3: mc 9:11 channel 24:25
1243 * 4: mc 12:14 channel 26:27
1244 * 5: mc 15:17 channel 28:29
1247 * Though we have 3 bits to identify the MC, we should only see
1248 * the values 0 or 1.
1251 static u32 knl_get_mc_route(int entry, u32 reg)
1255 WARN_ON(entry >= KNL_MAX_CHANNELS);
1257 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1258 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1260 return knl_channel_remap(mc, chan);
1264 * Render the EDC_ROUTE register in human-readable form.
1265 * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1267 static void knl_show_edc_route(u32 reg, char *s)
1271 for (i = 0; i < KNL_MAX_EDCS; i++) {
1272 s[i*2] = knl_get_edc_route(i, reg) + '0';
1276 s[KNL_MAX_EDCS*2 - 1] = '\0';
1280 * Render the MC_ROUTE register in human-readable form.
1281 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1283 static void knl_show_mc_route(u32 reg, char *s)
1287 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1288 s[i*2] = knl_get_mc_route(i, reg) + '0';
1292 s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1295 #define KNL_EDC_ROUTE 0xb8
1296 #define KNL_MC_ROUTE 0xb4
1298 /* Is this dram rule backed by regular DRAM in flat mode? */
1299 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1301 /* Is this dram rule cached? */
1302 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1304 /* Is this rule backed by edc ? */
1305 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1307 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1308 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1310 /* Is this rule mod3? */
1311 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1314 * Figure out how big our RAM modules are.
1316 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1317 * have to figure this out from the SAD rules, interleave lists, route tables,
1320 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1321 * inspect the TAD rules to figure out how large the SAD regions really are.
1323 * When we know the real size of a SAD region and how many ways it's
1324 * interleaved, we know the individual contribution of each channel to
1327 * Finally, we have to check whether each channel participates in each SAD
1330 * Fortunately, KNL only supports one DIMM per channel, so once we know how
1331 * much memory the channel uses, we know the DIMM is at least that large.
1332 * (The BIOS might possibly choose not to map all available memory, in which
1333 * case we will underreport the size of the DIMM.)
1335 * In theory, we could try to determine the EDC sizes as well, but that would
1336 * only work in flat mode, not in cache mode.
1338 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1341 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1343 u64 sad_base, sad_size, sad_limit = 0;
1344 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1347 int intrlv_ways, tad_ways;
1350 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1351 u32 dram_rule, interleave_reg;
1352 u32 mc_route_reg[KNL_MAX_CHAS];
1353 u32 edc_route_reg[KNL_MAX_CHAS];
1355 char edc_route_string[KNL_MAX_EDCS*2];
1356 char mc_route_string[KNL_MAX_CHANNELS*2];
1360 int participants[KNL_MAX_CHANNELS];
1362 for (i = 0; i < KNL_MAX_CHANNELS; i++)
1365 /* Read the EDC route table in each CHA. */
1367 for (i = 0; i < KNL_MAX_CHAS; i++) {
1368 pci_read_config_dword(pvt->knl.pci_cha[i],
1369 KNL_EDC_ROUTE, &edc_route_reg[i]);
1371 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1372 knl_show_edc_route(edc_route_reg[i-1],
1374 if (cur_reg_start == i-1)
1375 edac_dbg(0, "edc route table for CHA %d: %s\n",
1376 cur_reg_start, edc_route_string);
1378 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1379 cur_reg_start, i-1, edc_route_string);
1383 knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1384 if (cur_reg_start == i-1)
1385 edac_dbg(0, "edc route table for CHA %d: %s\n",
1386 cur_reg_start, edc_route_string);
1388 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1389 cur_reg_start, i-1, edc_route_string);
1391 /* Read the MC route table in each CHA. */
1393 for (i = 0; i < KNL_MAX_CHAS; i++) {
1394 pci_read_config_dword(pvt->knl.pci_cha[i],
1395 KNL_MC_ROUTE, &mc_route_reg[i]);
1397 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1398 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1399 if (cur_reg_start == i-1)
1400 edac_dbg(0, "mc route table for CHA %d: %s\n",
1401 cur_reg_start, mc_route_string);
1403 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1404 cur_reg_start, i-1, mc_route_string);
1408 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1409 if (cur_reg_start == i-1)
1410 edac_dbg(0, "mc route table for CHA %d: %s\n",
1411 cur_reg_start, mc_route_string);
1413 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1414 cur_reg_start, i-1, mc_route_string);
1416 /* Process DRAM rules */
1417 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1418 /* previous limit becomes the new base */
1419 sad_base = sad_limit;
1421 pci_read_config_dword(pvt->pci_sad0,
1422 pvt->info.dram_rule[sad_rule], &dram_rule);
1424 if (!DRAM_RULE_ENABLE(dram_rule))
1427 edram_only = KNL_EDRAM_ONLY(dram_rule);
1429 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1430 sad_size = sad_limit - sad_base;
1432 pci_read_config_dword(pvt->pci_sad0,
1433 pvt->info.interleave_list[sad_rule], &interleave_reg);
1436 * Find out how many ways this dram rule is interleaved.
1437 * We stop when we see the first channel again.
1439 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1441 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1442 pkg = sad_pkg(pvt->info.interleave_pkg,
1443 interleave_reg, intrlv_ways);
1445 if ((pkg & 0x8) == 0) {
1447 * 0 bit means memory is non-local,
1448 * which KNL doesn't support
1450 edac_dbg(0, "Unexpected interleave target %d\n",
1455 if (pkg == first_pkg)
1458 if (KNL_MOD3(dram_rule))
1461 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1466 edram_only ? ", EDRAM" : "");
1469 * Find out how big the SAD region really is by iterating
1470 * over TAD tables (SAD regions may contain holes).
1471 * Each memory controller might have a different TAD table, so
1472 * we have to look at both.
1474 * Livespace is the memory that's mapped in this TAD table,
1475 * deadspace is the holes (this could be the MMIO hole, or it
1476 * could be memory that's mapped by the other TAD table but
1479 for (mc = 0; mc < 2; mc++) {
1480 sad_actual_size[mc] = 0;
1483 tad_rule < ARRAY_SIZE(
1484 knl_tad_dram_limit_lo);
1486 if (knl_get_tad(pvt,
1494 tad_size = (tad_limit+1) -
1495 (tad_livespace + tad_deadspace);
1496 tad_livespace += tad_size;
1497 tad_base = (tad_limit+1) - tad_size;
1499 if (tad_base < sad_base) {
1500 if (tad_limit > sad_base)
1501 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1502 } else if (tad_base < sad_limit) {
1503 if (tad_limit+1 > sad_limit) {
1504 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1506 /* TAD region is completely inside SAD region */
1507 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1509 tad_limit, tad_size,
1511 sad_actual_size[mc] += tad_size;
1517 for (mc = 0; mc < 2; mc++) {
1518 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1519 mc, sad_actual_size[mc], sad_actual_size[mc]);
1522 /* Ignore EDRAM rule */
1526 /* Figure out which channels participate in interleave. */
1527 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1528 participants[channel] = 0;
1530 /* For each channel, does at least one CHA have
1531 * this channel mapped to the given target?
1533 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1537 for (target = 0; target < KNL_MAX_CHANNELS; target++) {
1538 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1539 if (knl_get_mc_route(target,
1540 mc_route_reg[cha]) == channel
1541 && !participants[channel]) {
1542 participants[channel] = 1;
1549 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1550 mc = knl_channel_mc(channel);
1551 if (participants[channel]) {
1552 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1554 sad_actual_size[mc]/intrlv_ways,
1556 mc_sizes[channel] +=
1557 sad_actual_size[mc]/intrlv_ways;
1565 static void get_source_id(struct mem_ctl_info *mci)
1567 struct sbridge_pvt *pvt = mci->pvt_info;
1570 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1571 pvt->info.type == KNIGHTS_LANDING)
1572 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
1574 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
1576 if (pvt->info.type == KNIGHTS_LANDING)
1577 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1579 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1582 static int __populate_dimms(struct mem_ctl_info *mci,
1583 u64 knl_mc_sizes[KNL_MAX_CHANNELS],
1584 enum edac_type mode)
1586 struct sbridge_pvt *pvt = mci->pvt_info;
1587 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1589 unsigned int i, j, banks, ranks, rows, cols, npages;
1590 struct dimm_info *dimm;
1591 enum mem_type mtype;
1594 mtype = pvt->info.get_memory_type(pvt);
1595 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1596 edac_dbg(0, "Memory is registered\n");
1597 else if (mtype == MEM_UNKNOWN)
1598 edac_dbg(0, "Cannot determine memory type\n");
1600 edac_dbg(0, "Memory is unregistered\n");
1602 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1607 for (i = 0; i < channels; i++) {
1610 int max_dimms_per_channel;
1612 if (pvt->info.type == KNIGHTS_LANDING) {
1613 max_dimms_per_channel = 1;
1614 if (!pvt->knl.pci_channel[i])
1617 max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1618 if (!pvt->pci_tad[i])
1622 for (j = 0; j < max_dimms_per_channel; j++) {
1623 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0);
1624 if (pvt->info.type == KNIGHTS_LANDING) {
1625 pci_read_config_dword(pvt->knl.pci_channel[i],
1628 pci_read_config_dword(pvt->pci_tad[i],
1631 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
1632 if (IS_DIMM_PRESENT(mtr)) {
1633 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1634 sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n",
1635 pvt->sbridge_dev->source_id,
1636 pvt->sbridge_dev->dom, i);
1639 pvt->channel[i].dimms++;
1641 ranks = numrank(pvt->info.type, mtr);
1643 if (pvt->info.type == KNIGHTS_LANDING) {
1644 /* For DDR4, this is fixed. */
1646 rows = knl_mc_sizes[i] /
1647 ((u64) cols * ranks * banks * 8);
1653 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1654 npages = MiB_TO_PAGES(size);
1656 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1657 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1659 banks, ranks, rows, cols);
1661 dimm->nr_pages = npages;
1663 dimm->dtype = pvt->info.get_width(pvt, mtr);
1664 dimm->mtype = mtype;
1665 dimm->edac_mode = mode;
1666 snprintf(dimm->label, sizeof(dimm->label),
1667 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1668 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
1676 static int get_dimm_config(struct mem_ctl_info *mci)
1678 struct sbridge_pvt *pvt = mci->pvt_info;
1679 u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1680 enum edac_type mode;
1683 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1684 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1685 pvt->sbridge_dev->mc,
1686 pvt->sbridge_dev->node_id,
1687 pvt->sbridge_dev->source_id);
1689 /* KNL doesn't support mirroring or lockstep,
1690 * and is always closed page
1692 if (pvt->info.type == KNIGHTS_LANDING) {
1693 mode = EDAC_S4ECD4ED;
1694 pvt->mirror_mode = NON_MIRRORING;
1695 pvt->is_cur_addr_mirrored = false;
1697 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1699 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1700 edac_dbg(0, "Failed to read KNL_MCMTR register\n");
1704 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1705 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {
1706 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n");
1709 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1710 if (GET_BITFIELD(reg, 28, 28)) {
1711 pvt->mirror_mode = ADDR_RANGE_MIRRORING;
1712 edac_dbg(0, "Address range partial memory mirroring is enabled\n");
1716 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {
1717 edac_dbg(0, "Failed to read RASENABLES register\n");
1720 if (IS_MIRROR_ENABLED(reg)) {
1721 pvt->mirror_mode = FULL_MIRRORING;
1722 edac_dbg(0, "Full memory mirroring is enabled\n");
1724 pvt->mirror_mode = NON_MIRRORING;
1725 edac_dbg(0, "Memory mirroring is disabled\n");
1729 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1730 edac_dbg(0, "Failed to read MCMTR register\n");
1733 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1734 edac_dbg(0, "Lockstep is enabled\n");
1735 mode = EDAC_S8ECD8ED;
1736 pvt->is_lockstep = true;
1738 edac_dbg(0, "Lockstep is disabled\n");
1739 mode = EDAC_S4ECD4ED;
1740 pvt->is_lockstep = false;
1742 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1743 edac_dbg(0, "address map is on closed page mode\n");
1744 pvt->is_close_pg = true;
1746 edac_dbg(0, "address map is on open page mode\n");
1747 pvt->is_close_pg = false;
1751 return __populate_dimms(mci, knl_mc_sizes, mode);
1754 static void get_memory_layout(const struct mem_ctl_info *mci)
1756 struct sbridge_pvt *pvt = mci->pvt_info;
1757 int i, j, k, n_sads, n_tads, sad_interl;
1765 * Step 1) Get TOLM/TOHM ranges
1768 pvt->tolm = pvt->info.get_tolm(pvt);
1769 tmp_mb = (1 + pvt->tolm) >> 20;
1771 gb = div_u64_rem(tmp_mb, 1024, &mb);
1772 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1773 gb, (mb*1000)/1024, (u64)pvt->tolm);
1775 /* Address range is already 45:25 */
1776 pvt->tohm = pvt->info.get_tohm(pvt);
1777 tmp_mb = (1 + pvt->tohm) >> 20;
1779 gb = div_u64_rem(tmp_mb, 1024, &mb);
1780 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1781 gb, (mb*1000)/1024, (u64)pvt->tohm);
1784 * Step 2) Get SAD range and SAD Interleave list
1785 * TAD registers contain the interleave wayness. However, it
1786 * seems simpler to just discover it indirectly, with the
1790 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1791 /* SAD_LIMIT Address range is 45:26 */
1792 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1794 limit = pvt->info.sad_limit(reg);
1796 if (!DRAM_RULE_ENABLE(reg))
1802 tmp_mb = (limit + 1) >> 20;
1803 gb = div_u64_rem(tmp_mb, 1024, &mb);
1804 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1806 show_dram_attr(pvt->info.dram_attr(reg)),
1808 ((u64)tmp_mb) << 20L,
1809 get_intlv_mode_str(reg, pvt->info.type),
1813 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1815 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1816 for (j = 0; j < 8; j++) {
1817 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1818 if (j > 0 && sad_interl == pkg)
1821 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1826 if (pvt->info.type == KNIGHTS_LANDING)
1830 * Step 3) Get TAD range
1833 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1834 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®);
1835 limit = TAD_LIMIT(reg);
1838 tmp_mb = (limit + 1) >> 20;
1840 gb = div_u64_rem(tmp_mb, 1024, &mb);
1841 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1842 n_tads, gb, (mb*1000)/1024,
1843 ((u64)tmp_mb) << 20L,
1844 (u32)(1 << TAD_SOCK(reg)),
1845 (u32)TAD_CH(reg) + 1,
1855 * Step 4) Get TAD offsets, per each channel
1857 for (i = 0; i < NUM_CHANNELS; i++) {
1858 if (!pvt->channel[i].dimms)
1860 for (j = 0; j < n_tads; j++) {
1861 pci_read_config_dword(pvt->pci_tad[i],
1862 tad_ch_nilv_offset[j],
1864 tmp_mb = TAD_OFFSET(reg) >> 20;
1865 gb = div_u64_rem(tmp_mb, 1024, &mb);
1866 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1869 ((u64)tmp_mb) << 20L,
1875 * Step 6) Get RIR Wayness/Limit, per each channel
1877 for (i = 0; i < NUM_CHANNELS; i++) {
1878 if (!pvt->channel[i].dimms)
1880 for (j = 0; j < MAX_RIR_RANGES; j++) {
1881 pci_read_config_dword(pvt->pci_tad[i],
1885 if (!IS_RIR_VALID(reg))
1888 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1889 rir_way = 1 << RIR_WAY(reg);
1890 gb = div_u64_rem(tmp_mb, 1024, &mb);
1891 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1894 ((u64)tmp_mb) << 20L,
1898 for (k = 0; k < rir_way; k++) {
1899 pci_read_config_dword(pvt->pci_tad[i],
1902 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1904 gb = div_u64_rem(tmp_mb, 1024, &mb);
1905 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1908 ((u64)tmp_mb) << 20L,
1909 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1916 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)
1918 struct sbridge_dev *sbridge_dev;
1920 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1921 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha)
1922 return sbridge_dev->mci;
1927 static int get_memory_error_data(struct mem_ctl_info *mci,
1932 char **area_type, char *msg)
1934 struct mem_ctl_info *new_mci;
1935 struct sbridge_pvt *pvt = mci->pvt_info;
1936 struct pci_dev *pci_ha;
1937 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1938 int sad_interl, idx, base_ch;
1939 int interleave_mode, shiftup = 0;
1940 unsigned int sad_interleave[MAX_INTERLEAVE];
1942 u8 ch_way, sck_way, pkg, sad_ha = 0;
1946 u64 ch_addr, offset, limit = 0, prv = 0;
1950 * Step 0) Check if the address is at special memory ranges
1951 * The check bellow is probably enough to fill all cases where
1952 * the error is not inside a memory, except for the legacy
1953 * range (e. g. VGA addresses). It is unlikely, however, that the
1954 * memory controller would generate an error on that range.
1956 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1957 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1960 if (addr >= (u64)pvt->tohm) {
1961 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1966 * Step 1) Get socket
1968 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1969 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1972 if (!DRAM_RULE_ENABLE(reg))
1975 limit = pvt->info.sad_limit(reg);
1977 sprintf(msg, "Can't discover the memory socket");
1984 if (n_sads == pvt->info.max_sad) {
1985 sprintf(msg, "Can't discover the memory socket");
1989 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1990 interleave_mode = pvt->info.interleave_mode(dram_rule);
1992 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1995 if (pvt->info.type == SANDY_BRIDGE) {
1996 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1997 for (sad_way = 0; sad_way < 8; sad_way++) {
1998 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1999 if (sad_way > 0 && sad_interl == pkg)
2001 sad_interleave[sad_way] = pkg;
2002 edac_dbg(0, "SAD interleave #%d: %d\n",
2003 sad_way, sad_interleave[sad_way]);
2005 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2006 pvt->sbridge_dev->mc,
2011 !interleave_mode ? "" : "XOR[18:16]");
2012 if (interleave_mode)
2013 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2015 idx = (addr >> 6) & 7;
2029 sprintf(msg, "Can't discover socket interleave");
2032 *socket = sad_interleave[idx];
2033 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2034 idx, sad_way, *socket);
2035 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2036 int bits, a7mode = A7MODE(dram_rule);
2039 /* A7 mode swaps P9 with P6 */
2040 bits = GET_BITFIELD(addr, 7, 8) << 1;
2041 bits |= GET_BITFIELD(addr, 9, 9);
2043 bits = GET_BITFIELD(addr, 6, 8);
2045 if (interleave_mode == 0) {
2046 /* interleave mode will XOR {8,7,6} with {18,17,16} */
2047 idx = GET_BITFIELD(addr, 16, 18);
2052 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2053 *socket = sad_pkg_socket(pkg);
2054 sad_ha = sad_pkg_ha(pkg);
2057 /* MCChanShiftUpEnable */
2058 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®);
2059 shiftup = GET_BITFIELD(reg, 22, 22);
2062 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2063 idx, *socket, sad_ha, shiftup);
2065 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2066 idx = (addr >> 6) & 7;
2067 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2068 *socket = sad_pkg_socket(pkg);
2069 sad_ha = sad_pkg_ha(pkg);
2070 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2071 idx, *socket, sad_ha);
2077 * Move to the proper node structure, in order to access the
2078 * right PCI registers
2080 new_mci = get_mci_for_node_id(*socket, sad_ha);
2082 sprintf(msg, "Struct for socket #%u wasn't initialized",
2087 pvt = mci->pvt_info;
2090 * Step 2) Get memory channel
2093 pci_ha = pvt->pci_ha;
2094 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2095 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
2096 limit = TAD_LIMIT(reg);
2098 sprintf(msg, "Can't discover the memory channel");
2105 if (n_tads == MAX_TAD) {
2106 sprintf(msg, "Can't discover the memory channel");
2110 ch_way = TAD_CH(reg) + 1;
2111 sck_way = TAD_SOCK(reg);
2116 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2117 if (pvt->is_chan_hash)
2118 idx = haswell_chan_hash(idx, addr);
2123 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2127 base_ch = TAD_TGT0(reg);
2130 base_ch = TAD_TGT1(reg);
2133 base_ch = TAD_TGT2(reg);
2136 base_ch = TAD_TGT3(reg);
2139 sprintf(msg, "Can't discover the TAD target");
2142 *channel_mask = 1 << base_ch;
2144 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
2146 if (pvt->mirror_mode == FULL_MIRRORING ||
2147 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
2148 *channel_mask |= 1 << ((base_ch + 2) % 4);
2152 sck_xch = (1 << sck_way) * (ch_way >> 1);
2155 sprintf(msg, "Invalid mirror set. Can't decode addr");
2159 pvt->is_cur_addr_mirrored = true;
2161 sck_xch = (1 << sck_way) * ch_way;
2162 pvt->is_cur_addr_mirrored = false;
2165 if (pvt->is_lockstep)
2166 *channel_mask |= 1 << ((base_ch + 1) % 4);
2168 offset = TAD_OFFSET(tad_offset);
2170 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2181 /* Calculate channel address */
2182 /* Remove the TAD offset */
2184 if (offset > addr) {
2185 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2190 ch_addr = addr - offset;
2191 ch_addr >>= (6 + shiftup);
2193 ch_addr <<= (6 + shiftup);
2194 ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2197 * Step 3) Decode rank
2199 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2200 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®);
2202 if (!IS_RIR_VALID(reg))
2205 limit = pvt->info.rir_limit(reg);
2206 gb = div_u64_rem(limit >> 20, 1024, &mb);
2207 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2212 if (ch_addr <= limit)
2215 if (n_rir == MAX_RIR_RANGES) {
2216 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2220 rir_way = RIR_WAY(reg);
2222 if (pvt->is_close_pg)
2223 idx = (ch_addr >> 6);
2225 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
2226 idx %= 1 << rir_way;
2228 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
2229 *rank = RIR_RNK_TGT(pvt->info.type, reg);
2231 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2241 static int get_memory_error_data_from_mce(struct mem_ctl_info *mci,
2242 const struct mce *m, u8 *socket,
2243 u8 *ha, long *channel_mask,
2246 u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2247 struct mem_ctl_info *new_mci;
2248 struct sbridge_pvt *pvt;
2249 struct pci_dev *pci_ha;
2252 if (channel >= NUM_CHANNELS) {
2253 sprintf(msg, "Invalid channel 0x%x", channel);
2257 pvt = mci->pvt_info;
2258 if (!pvt->info.get_ha) {
2259 sprintf(msg, "No get_ha()");
2262 *ha = pvt->info.get_ha(m->bank);
2263 if (*ha != 0 && *ha != 1) {
2264 sprintf(msg, "Impossible bank %d", m->bank);
2268 *socket = m->socketid;
2269 new_mci = get_mci_for_node_id(*socket, *ha);
2271 strcpy(msg, "mci socket got corrupted!");
2275 pvt = new_mci->pvt_info;
2276 pci_ha = pvt->pci_ha;
2277 pci_read_config_dword(pci_ha, tad_dram_rule[0], ®);
2278 tad0 = m->addr <= TAD_LIMIT(reg);
2280 *channel_mask = 1 << channel;
2281 if (pvt->mirror_mode == FULL_MIRRORING ||
2282 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
2283 *channel_mask |= 1 << ((channel + 2) % 4);
2284 pvt->is_cur_addr_mirrored = true;
2286 pvt->is_cur_addr_mirrored = false;
2289 if (pvt->is_lockstep)
2290 *channel_mask |= 1 << ((channel + 1) % 4);
2295 /****************************************************************************
2296 Device initialization routines: put/get, init/exit
2297 ****************************************************************************/
2300 * sbridge_put_all_devices 'put' all the devices that we have
2301 * reserved via 'get'
2303 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2308 for (i = 0; i < sbridge_dev->n_devs; i++) {
2309 struct pci_dev *pdev = sbridge_dev->pdev[i];
2312 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2314 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2319 static void sbridge_put_all_devices(void)
2321 struct sbridge_dev *sbridge_dev, *tmp;
2323 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2324 sbridge_put_devices(sbridge_dev);
2325 free_sbridge_dev(sbridge_dev);
2329 static int sbridge_get_onedevice(struct pci_dev **prev,
2331 const struct pci_id_table *table,
2332 const unsigned devno,
2333 const int multi_bus)
2335 struct sbridge_dev *sbridge_dev = NULL;
2336 const struct pci_id_descr *dev_descr = &table->descr[devno];
2337 struct pci_dev *pdev = NULL;
2342 sbridge_printk(KERN_DEBUG,
2343 "Seeking for: PCI ID %04x:%04x\n",
2344 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2346 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2347 dev_descr->dev_id, *prev);
2355 if (dev_descr->optional)
2358 /* if the HA wasn't found */
2362 sbridge_printk(KERN_INFO,
2363 "Device not found: %04x:%04x\n",
2364 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2366 /* End of list, leave */
2369 seg = pci_domain_nr(pdev->bus);
2370 bus = pdev->bus->number;
2373 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom,
2374 multi_bus, sbridge_dev);
2376 /* If the HA1 wasn't found, don't create EDAC second memory controller */
2377 if (dev_descr->dom == IMC1 && devno != 1) {
2378 edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n",
2379 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2384 if (dev_descr->dom == SOCK)
2387 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table);
2395 if (sbridge_dev->pdev[sbridge_dev->i_devs]) {
2396 sbridge_printk(KERN_ERR,
2397 "Duplicated device for %04x:%04x\n",
2398 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2403 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev;
2405 /* pdev belongs to more than one IMC, do extra gets */
2409 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock)
2413 /* Be sure that the device is enabled */
2414 if (unlikely(pci_enable_device(pdev) < 0)) {
2415 sbridge_printk(KERN_ERR,
2416 "Couldn't enable %04x:%04x\n",
2417 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2421 edac_dbg(0, "Detected %04x:%04x\n",
2422 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2425 * As stated on drivers/pci/search.c, the reference count for
2426 * @from is always decremented if it is not %NULL. So, as we need
2427 * to get all devices up to null, we need to do a get for the device
2437 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2438 * devices we want to reference for this driver.
2439 * @num_mc: pointer to the memory controllers count, to be incremented in case
2441 * @table: model specific table
2443 * returns 0 in case of success or error code
2445 static int sbridge_get_all_devices(u8 *num_mc,
2446 const struct pci_id_table *table)
2449 struct pci_dev *pdev = NULL;
2453 if (table->type == KNIGHTS_LANDING)
2454 allow_dups = multi_bus = 1;
2455 while (table && table->descr) {
2456 for (i = 0; i < table->n_devs_per_sock; i++) {
2457 if (!allow_dups || i == 0 ||
2458 table->descr[i].dev_id !=
2459 table->descr[i-1].dev_id) {
2463 rc = sbridge_get_onedevice(&pdev, num_mc,
2464 table, i, multi_bus);
2467 i = table->n_devs_per_sock;
2470 sbridge_put_all_devices();
2473 } while (pdev && !allow_dups);
2482 * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in
2483 * the format: XXXa. So we can convert from a device to the corresponding
2486 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2488 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2489 struct sbridge_dev *sbridge_dev)
2491 struct sbridge_pvt *pvt = mci->pvt_info;
2492 struct pci_dev *pdev;
2493 u8 saw_chan_mask = 0;
2496 for (i = 0; i < sbridge_dev->n_devs; i++) {
2497 pdev = sbridge_dev->pdev[i];
2501 switch (pdev->device) {
2502 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2503 pvt->pci_sad0 = pdev;
2505 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2506 pvt->pci_sad1 = pdev;
2508 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2509 pvt->pci_br0 = pdev;
2511 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2514 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2517 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2518 pvt->pci_ras = pdev;
2520 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2521 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2522 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2523 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2525 int id = TAD_DEV_TO_CHAN(pdev->device);
2526 pvt->pci_tad[id] = pdev;
2527 saw_chan_mask |= 1 << id;
2530 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2531 pvt->pci_ddrio = pdev;
2537 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2538 pdev->vendor, pdev->device,
2543 /* Check if everything were registered */
2544 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
2545 !pvt->pci_ras || !pvt->pci_ta)
2548 if (saw_chan_mask != 0x0f)
2553 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2557 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2558 PCI_VENDOR_ID_INTEL, pdev->device);
2562 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2563 struct sbridge_dev *sbridge_dev)
2565 struct sbridge_pvt *pvt = mci->pvt_info;
2566 struct pci_dev *pdev;
2567 u8 saw_chan_mask = 0;
2570 for (i = 0; i < sbridge_dev->n_devs; i++) {
2571 pdev = sbridge_dev->pdev[i];
2575 switch (pdev->device) {
2576 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2577 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2580 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2581 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
2584 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2585 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:
2586 pvt->pci_ras = pdev;
2588 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2589 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2590 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2591 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2592 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2593 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2594 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2595 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2597 int id = TAD_DEV_TO_CHAN(pdev->device);
2598 pvt->pci_tad[id] = pdev;
2599 saw_chan_mask |= 1 << id;
2602 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2603 pvt->pci_ddrio = pdev;
2605 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2606 pvt->pci_ddrio = pdev;
2608 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2609 pvt->pci_sad0 = pdev;
2611 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2612 pvt->pci_br0 = pdev;
2614 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2615 pvt->pci_br1 = pdev;
2621 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2623 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2627 /* Check if everything were registered */
2628 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
2629 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2632 if (saw_chan_mask != 0x0f && /* -EN/-EX */
2633 saw_chan_mask != 0x03) /* -EP */
2638 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2642 sbridge_printk(KERN_ERR,
2643 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2648 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2649 struct sbridge_dev *sbridge_dev)
2651 struct sbridge_pvt *pvt = mci->pvt_info;
2652 struct pci_dev *pdev;
2653 u8 saw_chan_mask = 0;
2656 /* there's only one device per system; not tied to any bus */
2657 if (pvt->info.pci_vtd == NULL)
2658 /* result will be checked later */
2659 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2660 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2663 for (i = 0; i < sbridge_dev->n_devs; i++) {
2664 pdev = sbridge_dev->pdev[i];
2668 switch (pdev->device) {
2669 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2670 pvt->pci_sad0 = pdev;
2672 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2673 pvt->pci_sad1 = pdev;
2675 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2676 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2679 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2680 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2683 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:
2684 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM:
2685 pvt->pci_ras = pdev;
2687 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2688 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2689 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2690 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2691 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2692 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2693 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2694 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2696 int id = TAD_DEV_TO_CHAN(pdev->device);
2697 pvt->pci_tad[id] = pdev;
2698 saw_chan_mask |= 1 << id;
2701 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2702 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2703 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2704 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2705 if (!pvt->pci_ddrio)
2706 pvt->pci_ddrio = pdev;
2712 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2714 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2718 /* Check if everything were registered */
2719 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2720 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2723 if (saw_chan_mask != 0x0f && /* -EN/-EX */
2724 saw_chan_mask != 0x03) /* -EP */
2729 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2733 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2734 struct sbridge_dev *sbridge_dev)
2736 struct sbridge_pvt *pvt = mci->pvt_info;
2737 struct pci_dev *pdev;
2738 u8 saw_chan_mask = 0;
2741 /* there's only one device per system; not tied to any bus */
2742 if (pvt->info.pci_vtd == NULL)
2743 /* result will be checked later */
2744 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2745 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2748 for (i = 0; i < sbridge_dev->n_devs; i++) {
2749 pdev = sbridge_dev->pdev[i];
2753 switch (pdev->device) {
2754 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2755 pvt->pci_sad0 = pdev;
2757 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2758 pvt->pci_sad1 = pdev;
2760 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2761 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2764 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2765 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2768 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:
2769 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM:
2770 pvt->pci_ras = pdev;
2772 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2773 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2774 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2775 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2776 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2777 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2778 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2779 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2781 int id = TAD_DEV_TO_CHAN(pdev->device);
2782 pvt->pci_tad[id] = pdev;
2783 saw_chan_mask |= 1 << id;
2786 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2787 pvt->pci_ddrio = pdev;
2793 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2795 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2799 /* Check if everything were registered */
2800 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2801 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2804 if (saw_chan_mask != 0x0f && /* -EN/-EX */
2805 saw_chan_mask != 0x03) /* -EP */
2810 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2814 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2815 struct sbridge_dev *sbridge_dev)
2817 struct sbridge_pvt *pvt = mci->pvt_info;
2818 struct pci_dev *pdev;
2824 for (i = 0; i < sbridge_dev->n_devs; i++) {
2825 pdev = sbridge_dev->pdev[i];
2829 /* Extract PCI device and function. */
2830 dev = (pdev->devfn >> 3) & 0x1f;
2831 func = pdev->devfn & 0x7;
2833 switch (pdev->device) {
2834 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2836 pvt->knl.pci_mc0 = pdev;
2838 pvt->knl.pci_mc1 = pdev;
2840 sbridge_printk(KERN_ERR,
2841 "Memory controller in unexpected place! (dev %d, fn %d)\n",
2847 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2848 pvt->pci_sad0 = pdev;
2851 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2852 pvt->pci_sad1 = pdev;
2855 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2856 /* There are one of these per tile, and range from
2859 devidx = ((dev-14)*8)+func;
2861 if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2862 sbridge_printk(KERN_ERR,
2863 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2868 WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2870 pvt->knl.pci_cha[devidx] = pdev;
2873 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:
2877 * MC0 channels 0-2 are device 9 function 2-4,
2878 * MC1 channels 3-5 are device 8 function 2-4.
2884 devidx = 3 + (func-2);
2886 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2887 sbridge_printk(KERN_ERR,
2888 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2893 WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2894 pvt->knl.pci_channel[devidx] = pdev;
2897 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2898 pvt->knl.pci_mc_info = pdev;
2901 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2906 sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2912 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
2913 !pvt->pci_sad0 || !pvt->pci_sad1 ||
2918 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2919 if (!pvt->knl.pci_channel[i]) {
2920 sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2925 for (i = 0; i < KNL_MAX_CHAS; i++) {
2926 if (!pvt->knl.pci_cha[i]) {
2927 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2935 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2939 /****************************************************************************
2940 Error check routines
2941 ****************************************************************************/
2944 * While Sandy Bridge has error count registers, SMI BIOS read values from
2945 * and resets the counters. So, they are not reliable for the OS to read
2946 * from them. So, we have no option but to just trust on whatever MCE is
2947 * telling us about the errors.
2949 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2950 const struct mce *m)
2952 struct mem_ctl_info *new_mci;
2953 struct sbridge_pvt *pvt = mci->pvt_info;
2954 enum hw_event_mc_err_type tp_event;
2955 char *type, *optype, msg[256];
2956 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2957 bool overflow = GET_BITFIELD(m->status, 62, 62);
2958 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2960 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2961 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2962 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2963 u32 channel = GET_BITFIELD(m->status, 0, 3);
2964 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2966 * Bits 5-0 of MCi_MISC give the least significant bit that is valid.
2967 * A value 6 is for cache line aligned address, a value 12 is for page
2968 * aligned address reported by patrol scrubber.
2970 u32 lsb = GET_BITFIELD(m->misc, 0, 5);
2971 long channel_mask, first_channel;
2972 u8 rank = 0xff, socket, ha;
2974 char *area_type = "DRAM";
2976 if (pvt->info.type != SANDY_BRIDGE)
2979 recoverable = GET_BITFIELD(m->status, 56, 56);
2981 if (uncorrected_error) {
2985 tp_event = HW_EVENT_ERR_FATAL;
2988 tp_event = HW_EVENT_ERR_UNCORRECTED;
2992 tp_event = HW_EVENT_ERR_CORRECTED;
2996 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2997 * memory errors should fit in this mask:
2998 * 000f 0000 1mmm cccc (binary)
3000 * f = Correction Report Filtering Bit. If 1, subsequent errors
3004 * If the mask doesn't match, report an error to the parsing logic
3006 switch (optypenum) {
3008 optype = "generic undef request error";
3011 optype = "memory read error";
3014 optype = "memory write error";
3017 optype = "addr/cmd error";
3020 optype = "memory scrubbing error";
3023 optype = "reserved";
3027 if (pvt->info.type == KNIGHTS_LANDING) {
3028 if (channel == 14) {
3029 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
3030 overflow ? " OVERFLOW" : "",
3031 (uncorrected_error && recoverable)
3032 ? " recoverable" : "",
3039 * Reported channel is in range 0-2, so we can't map it
3040 * back to mc. To figure out mc we check machine check
3041 * bank register that reported this error.
3042 * bank15 means mc0 and bank16 means mc1.
3044 channel = knl_channel_remap(m->bank == 16, channel);
3045 channel_mask = 1 << channel;
3047 snprintf(msg, sizeof(msg),
3048 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3049 overflow ? " OVERFLOW" : "",
3050 (uncorrected_error && recoverable)
3051 ? " recoverable" : " ",
3052 mscod, errcode, channel, A + channel);
3053 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3054 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3059 } else if (lsb < 12) {
3060 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3061 &channel_mask, &rank,
3064 rc = get_memory_error_data_from_mce(mci, m, &socket, &ha,
3065 &channel_mask, msg);
3070 new_mci = get_mci_for_node_id(socket, ha);
3072 strcpy(msg, "Error: socket got corrupted!");
3076 pvt = mci->pvt_info;
3078 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3090 * FIXME: On some memory configurations (mirror, lockstep), the
3091 * Memory Controller can't point the error to a single DIMM. The
3092 * EDAC core should be handling the channel mask, in order to point
3093 * to the group of dimm's where the error may be happening.
3095 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
3096 channel = first_channel;
3098 snprintf(msg, sizeof(msg),
3099 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3100 overflow ? " OVERFLOW" : "",
3101 (uncorrected_error && recoverable) ? " recoverable" : "",
3108 edac_dbg(0, "%s\n", msg);
3110 /* FIXME: need support for channel mask */
3112 if (channel == CHANNEL_UNSPECIFIED)
3115 /* Call the helper to output message */
3116 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3117 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3122 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3129 * Check that logging is enabled and that this is the right type
3130 * of error for us to handle.
3132 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3135 struct mce *mce = (struct mce *)data;
3136 struct mem_ctl_info *mci;
3139 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3143 * Just let mcelog handle it if the error is
3144 * outside the memory controller. A memory error
3145 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3146 * bit 12 has an special meaning.
3148 if ((mce->status & 0xefff) >> 7 != 1)
3151 /* Check ADDRV bit in STATUS */
3152 if (!GET_BITFIELD(mce->status, 58, 58))
3155 /* Check MISCV bit in STATUS */
3156 if (!GET_BITFIELD(mce->status, 59, 59))
3159 /* Check address type in MISC (physical address only) */
3160 if (GET_BITFIELD(mce->misc, 6, 8) != 2)
3163 mci = get_mci_for_node_id(mce->socketid, IMC0);
3167 if (mce->mcgstatus & MCG_STATUS_MCIP)
3172 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3174 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3175 "Bank %d: %016Lx\n", mce->extcpu, type,
3176 mce->mcgstatus, mce->bank, mce->status);
3177 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3178 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3179 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3181 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3182 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3183 mce->time, mce->socketid, mce->apicid);
3185 sbridge_mce_output_error(mci, mce);
3187 /* Advice mcelog that the error were handled */
3191 static struct notifier_block sbridge_mce_dec = {
3192 .notifier_call = sbridge_mce_check_error,
3193 .priority = MCE_PRIO_EDAC,
3196 /****************************************************************************
3197 EDAC register/unregister logic
3198 ****************************************************************************/
3200 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3202 struct mem_ctl_info *mci = sbridge_dev->mci;
3203 struct sbridge_pvt *pvt;
3205 if (unlikely(!mci || !mci->pvt_info)) {
3206 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3208 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3212 pvt = mci->pvt_info;
3214 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3215 mci, &sbridge_dev->pdev[0]->dev);
3217 /* Remove MC sysfs nodes */
3218 edac_mc_del_mc(mci->pdev);
3220 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3221 kfree(mci->ctl_name);
3223 sbridge_dev->mci = NULL;
3226 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3228 struct mem_ctl_info *mci;
3229 struct edac_mc_layer layers[2];
3230 struct sbridge_pvt *pvt;
3231 struct pci_dev *pdev = sbridge_dev->pdev[0];
3234 /* allocate a new MC control structure */
3235 layers[0].type = EDAC_MC_LAYER_CHANNEL;
3236 layers[0].size = type == KNIGHTS_LANDING ?
3237 KNL_MAX_CHANNELS : NUM_CHANNELS;
3238 layers[0].is_virt_csrow = false;
3239 layers[1].type = EDAC_MC_LAYER_SLOT;
3240 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3241 layers[1].is_virt_csrow = true;
3242 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3248 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3251 pvt = mci->pvt_info;
3252 memset(pvt, 0, sizeof(*pvt));
3254 /* Associate sbridge_dev and mci for future usage */
3255 pvt->sbridge_dev = sbridge_dev;
3256 sbridge_dev->mci = mci;
3258 mci->mtype_cap = type == KNIGHTS_LANDING ?
3259 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3260 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3261 mci->edac_cap = EDAC_FLAG_NONE;
3262 mci->mod_name = EDAC_MOD_STR;
3263 mci->dev_name = pci_name(pdev);
3264 mci->ctl_page_to_phys = NULL;
3266 pvt->info.type = type;
3269 pvt->info.rankcfgr = IB_RANK_CFG_A;
3270 pvt->info.get_tolm = ibridge_get_tolm;
3271 pvt->info.get_tohm = ibridge_get_tohm;
3272 pvt->info.dram_rule = ibridge_dram_rule;
3273 pvt->info.get_memory_type = get_memory_type;
3274 pvt->info.get_node_id = get_node_id;
3275 pvt->info.get_ha = ibridge_get_ha;
3276 pvt->info.rir_limit = rir_limit;
3277 pvt->info.sad_limit = sad_limit;
3278 pvt->info.interleave_mode = interleave_mode;
3279 pvt->info.dram_attr = dram_attr;
3280 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3281 pvt->info.interleave_list = ibridge_interleave_list;
3282 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3283 pvt->info.get_width = ibridge_get_width;
3285 /* Store pci devices at mci for faster access */
3286 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3287 if (unlikely(rc < 0))
3290 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d",
3291 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3294 pvt->info.rankcfgr = SB_RANK_CFG_A;
3295 pvt->info.get_tolm = sbridge_get_tolm;
3296 pvt->info.get_tohm = sbridge_get_tohm;
3297 pvt->info.dram_rule = sbridge_dram_rule;
3298 pvt->info.get_memory_type = get_memory_type;
3299 pvt->info.get_node_id = get_node_id;
3300 pvt->info.get_ha = sbridge_get_ha;
3301 pvt->info.rir_limit = rir_limit;
3302 pvt->info.sad_limit = sad_limit;
3303 pvt->info.interleave_mode = interleave_mode;
3304 pvt->info.dram_attr = dram_attr;
3305 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3306 pvt->info.interleave_list = sbridge_interleave_list;
3307 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3308 pvt->info.get_width = sbridge_get_width;
3310 /* Store pci devices at mci for faster access */
3311 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3312 if (unlikely(rc < 0))
3315 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d",
3316 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3319 /* rankcfgr isn't used */
3320 pvt->info.get_tolm = haswell_get_tolm;
3321 pvt->info.get_tohm = haswell_get_tohm;
3322 pvt->info.dram_rule = ibridge_dram_rule;
3323 pvt->info.get_memory_type = haswell_get_memory_type;
3324 pvt->info.get_node_id = haswell_get_node_id;
3325 pvt->info.get_ha = ibridge_get_ha;
3326 pvt->info.rir_limit = haswell_rir_limit;
3327 pvt->info.sad_limit = sad_limit;
3328 pvt->info.interleave_mode = interleave_mode;
3329 pvt->info.dram_attr = dram_attr;
3330 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3331 pvt->info.interleave_list = ibridge_interleave_list;
3332 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3333 pvt->info.get_width = ibridge_get_width;
3335 /* Store pci devices at mci for faster access */
3336 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3337 if (unlikely(rc < 0))
3340 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d",
3341 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3344 /* rankcfgr isn't used */
3345 pvt->info.get_tolm = haswell_get_tolm;
3346 pvt->info.get_tohm = haswell_get_tohm;
3347 pvt->info.dram_rule = ibridge_dram_rule;
3348 pvt->info.get_memory_type = haswell_get_memory_type;
3349 pvt->info.get_node_id = haswell_get_node_id;
3350 pvt->info.get_ha = ibridge_get_ha;
3351 pvt->info.rir_limit = haswell_rir_limit;
3352 pvt->info.sad_limit = sad_limit;
3353 pvt->info.interleave_mode = interleave_mode;
3354 pvt->info.dram_attr = dram_attr;
3355 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3356 pvt->info.interleave_list = ibridge_interleave_list;
3357 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3358 pvt->info.get_width = broadwell_get_width;
3360 /* Store pci devices at mci for faster access */
3361 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3362 if (unlikely(rc < 0))
3365 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d",
3366 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3368 case KNIGHTS_LANDING:
3369 /* pvt->info.rankcfgr == ??? */
3370 pvt->info.get_tolm = knl_get_tolm;
3371 pvt->info.get_tohm = knl_get_tohm;
3372 pvt->info.dram_rule = knl_dram_rule;
3373 pvt->info.get_memory_type = knl_get_memory_type;
3374 pvt->info.get_node_id = knl_get_node_id;
3375 pvt->info.get_ha = knl_get_ha;
3376 pvt->info.rir_limit = NULL;
3377 pvt->info.sad_limit = knl_sad_limit;
3378 pvt->info.interleave_mode = knl_interleave_mode;
3379 pvt->info.dram_attr = dram_attr_knl;
3380 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3381 pvt->info.interleave_list = knl_interleave_list;
3382 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3383 pvt->info.get_width = knl_get_width;
3385 rc = knl_mci_bind_devs(mci, sbridge_dev);
3386 if (unlikely(rc < 0))
3389 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d",
3390 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3394 if (!mci->ctl_name) {
3399 /* Get dimm basic config and the memory layout */
3400 rc = get_dimm_config(mci);
3402 edac_dbg(0, "MC: failed to get_dimm_config()\n");
3405 get_memory_layout(mci);
3407 /* record ptr to the generic device */
3408 mci->pdev = &pdev->dev;
3410 /* add this new MC control structure to EDAC's list of MCs */
3411 if (unlikely(edac_mc_add_mc(mci))) {
3412 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3420 kfree(mci->ctl_name);
3423 sbridge_dev->mci = NULL;
3427 static const struct x86_cpu_id sbridge_cpuids[] = {
3428 INTEL_CPU_FAM6(SANDYBRIDGE_X, pci_dev_descr_sbridge_table),
3429 INTEL_CPU_FAM6(IVYBRIDGE_X, pci_dev_descr_ibridge_table),
3430 INTEL_CPU_FAM6(HASWELL_X, pci_dev_descr_haswell_table),
3431 INTEL_CPU_FAM6(BROADWELL_X, pci_dev_descr_broadwell_table),
3432 INTEL_CPU_FAM6(BROADWELL_D, pci_dev_descr_broadwell_table),
3433 INTEL_CPU_FAM6(XEON_PHI_KNL, pci_dev_descr_knl_table),
3434 INTEL_CPU_FAM6(XEON_PHI_KNM, pci_dev_descr_knl_table),
3437 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3440 * sbridge_probe Get all devices and register memory controllers
3443 * 0 for FOUND a device
3444 * < 0 for error code
3447 static int sbridge_probe(const struct x86_cpu_id *id)
3451 struct sbridge_dev *sbridge_dev;
3452 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
3454 /* get the pci devices we want to reserve for our use */
3455 rc = sbridge_get_all_devices(&num_mc, ptable);
3457 if (unlikely(rc < 0)) {
3458 edac_dbg(0, "couldn't get all devices\n");
3464 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3465 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3466 mc, mc + 1, num_mc);
3468 sbridge_dev->mc = mc++;
3469 rc = sbridge_register_mci(sbridge_dev, ptable->type);
3470 if (unlikely(rc < 0))
3474 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3479 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3480 sbridge_unregister_mci(sbridge_dev);
3482 sbridge_put_all_devices();
3488 * sbridge_remove cleanup
3491 static void sbridge_remove(void)
3493 struct sbridge_dev *sbridge_dev;
3497 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3498 sbridge_unregister_mci(sbridge_dev);
3500 /* Release PCI resources */
3501 sbridge_put_all_devices();
3505 * sbridge_init Module entry function
3506 * Try to initialize this module for its devices
3508 static int __init sbridge_init(void)
3510 const struct x86_cpu_id *id;
3516 owner = edac_get_owner();
3517 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
3520 id = x86_match_cpu(sbridge_cpuids);
3524 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3527 rc = sbridge_probe(id);
3530 mce_register_decode_chain(&sbridge_mce_dec);
3531 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3532 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3536 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3543 * sbridge_exit() Module exit function
3544 * Unregister the driver
3546 static void __exit sbridge_exit(void)
3550 mce_unregister_decode_chain(&sbridge_mce_dec);
3553 module_init(sbridge_init);
3554 module_exit(sbridge_exit);
3556 module_param(edac_op_state, int, 0444);
3557 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3559 MODULE_LICENSE("GPL");
3560 MODULE_AUTHOR("Mauro Carvalho Chehab");
3561 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3562 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "