1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
6 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/mutex.h>
10 #include <linux/errno.h>
11 #include <linux/err.h>
12 #include <linux/qcom_scm.h>
13 #include <linux/dma-mapping.h>
17 #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
18 #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
19 #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
20 #define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
22 #define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
23 #define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
24 #define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
25 #define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
27 struct qcom_scm_entry {
32 static struct qcom_scm_entry qcom_scm_wb[] = {
33 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
34 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
35 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
36 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
39 static DEFINE_MUTEX(qcom_scm_lock);
42 * struct qcom_scm_command - one SCM command buffer
43 * @len: total available memory for command and response
44 * @buf_offset: start of command buffer
45 * @resp_hdr_offset: start of response buffer
46 * @id: command to be executed
47 * @buf: buffer returned from qcom_scm_get_command_buffer()
49 * An SCM command is laid out in memory as follows:
51 * ------------------- <--- struct qcom_scm_command
53 * ------------------- <--- qcom_scm_get_command_buffer()
55 * ------------------- <--- struct qcom_scm_response and
56 * | response header | qcom_scm_command_to_response()
57 * ------------------- <--- qcom_scm_get_response_buffer()
61 * There can be arbitrary padding between the headers and buffers so
62 * you should always use the appropriate qcom_scm_get_*_buffer() routines
63 * to access the buffers in a safe manner.
65 struct qcom_scm_command {
68 __le32 resp_hdr_offset;
74 * struct qcom_scm_response - one SCM response buffer
75 * @len: total available memory for response
76 * @buf_offset: start of response data relative to start of qcom_scm_response
77 * @is_complete: indicates if the command has finished processing
79 struct qcom_scm_response {
86 * qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response
89 * Returns a pointer to a response for a command.
91 static inline struct qcom_scm_response *qcom_scm_command_to_response(
92 const struct qcom_scm_command *cmd)
94 return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
98 * qcom_scm_get_command_buffer() - Get a pointer to a command buffer
101 * Returns a pointer to the command buffer of a command.
103 static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd)
105 return (void *)cmd->buf;
109 * qcom_scm_get_response_buffer() - Get a pointer to a response buffer
112 * Returns a pointer to a response buffer of a response.
114 static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp)
116 return (void *)rsp + le32_to_cpu(rsp->buf_offset);
119 static u32 smc(u32 cmd_addr)
122 register u32 r0 asm("r0") = 1;
123 register u32 r1 asm("r1") = (u32)&context_id;
124 register u32 r2 asm("r2") = cmd_addr;
132 ".arch_extension sec\n"
134 "smc #0 @ switch to secure world\n"
136 : "r" (r0), "r" (r1), "r" (r2)
138 } while (r0 == QCOM_SCM_INTERRUPTED);
144 * qcom_scm_call() - Send an SCM command
145 * @dev: struct device
146 * @svc_id: service identifier
147 * @cmd_id: command identifier
148 * @cmd_buf: command buffer
149 * @cmd_len: length of the command buffer
150 * @resp_buf: response buffer
151 * @resp_len: length of the response buffer
153 * Sends a command to the SCM and waits for the command to finish processing.
155 * A note on cache maintenance:
156 * Note that any buffers that are expected to be accessed by the secure world
157 * must be flushed before invoking qcom_scm_call and invalidated in the cache
158 * immediately after qcom_scm_call returns. Cache maintenance on the command
159 * and response buffers is taken care of by qcom_scm_call; however, callers are
160 * responsible for any other cached buffers passed over to the secure world.
162 static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
163 const void *cmd_buf, size_t cmd_len, void *resp_buf,
167 struct qcom_scm_command *cmd;
168 struct qcom_scm_response *rsp;
169 size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
172 cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
176 cmd->len = cpu_to_le32(alloc_len);
177 cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
178 cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
180 cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
182 memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len);
184 rsp = qcom_scm_command_to_response(cmd);
186 cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
187 if (dma_mapping_error(dev, cmd_phys)) {
192 mutex_lock(&qcom_scm_lock);
195 ret = qcom_scm_remap_error(ret);
196 mutex_unlock(&qcom_scm_lock);
201 dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
202 sizeof(*rsp), DMA_FROM_DEVICE);
203 } while (!rsp->is_complete);
206 dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
207 le32_to_cpu(rsp->buf_offset),
208 resp_len, DMA_FROM_DEVICE);
209 memcpy(resp_buf, qcom_scm_get_response_buffer(rsp),
213 dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
218 #define SCM_CLASS_REGISTER (0x2 << 8)
219 #define SCM_MASK_IRQS BIT(5)
220 #define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
221 SCM_CLASS_REGISTER | \
226 * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
227 * @svc_id: service identifier
228 * @cmd_id: command identifier
229 * @arg1: first argument
231 * This shall only be used with commands that are guaranteed to be
232 * uninterruptable, atomic and SMP safe.
234 static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
238 register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
239 register u32 r1 asm("r1") = (u32)&context_id;
240 register u32 r2 asm("r2") = arg1;
248 ".arch_extension sec\n"
250 "smc #0 @ switch to secure world\n"
252 : "r" (r0), "r" (r1), "r" (r2)
258 * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments
259 * @svc_id: service identifier
260 * @cmd_id: command identifier
261 * @arg1: first argument
262 * @arg2: second argument
264 * This shall only be used with commands that are guaranteed to be
265 * uninterruptable, atomic and SMP safe.
267 static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
271 register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2);
272 register u32 r1 asm("r1") = (u32)&context_id;
273 register u32 r2 asm("r2") = arg1;
274 register u32 r3 asm("r3") = arg2;
283 ".arch_extension sec\n"
285 "smc #0 @ switch to secure world\n"
287 : "r" (r0), "r" (r1), "r" (r2), "r" (r3)
292 u32 qcom_scm_get_version(void)
295 static u32 version = -1;
296 register u32 r0 asm("r0");
297 register u32 r1 asm("r1");
302 mutex_lock(&qcom_scm_lock);
305 r1 = (u32)&context_id;
313 ".arch_extension sec\n"
315 "smc #0 @ switch to secure world\n"
316 : "=r" (r0), "=r" (r1)
318 : "r2", "r3", "r12");
319 } while (r0 == QCOM_SCM_INTERRUPTED);
322 mutex_unlock(&qcom_scm_lock);
326 EXPORT_SYMBOL(qcom_scm_get_version);
329 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
330 * @entry: Entry point function for the cpus
331 * @cpus: The cpumask of cpus that will use the entry point
333 * Set the cold boot address of the cpus. Any cpu outside the supported
334 * range would be removed from the cpu present mask.
336 int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
340 int scm_cb_flags[] = {
341 QCOM_SCM_FLAG_COLDBOOT_CPU0,
342 QCOM_SCM_FLAG_COLDBOOT_CPU1,
343 QCOM_SCM_FLAG_COLDBOOT_CPU2,
344 QCOM_SCM_FLAG_COLDBOOT_CPU3,
347 if (!cpus || (cpus && cpumask_empty(cpus)))
350 for_each_cpu(cpu, cpus) {
351 if (cpu < ARRAY_SIZE(scm_cb_flags))
352 flags |= scm_cb_flags[cpu];
354 set_cpu_present(cpu, false);
357 return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
358 flags, virt_to_phys(entry));
362 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
363 * @entry: Entry point function for the cpus
364 * @cpus: The cpumask of cpus that will use the entry point
366 * Set the Linux entry point for the SCM to transfer control to when coming
367 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
369 int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
370 const cpumask_t *cpus)
381 * Reassign only if we are switching from hotplug entry point
382 * to cpuidle entry point or vice versa.
384 for_each_cpu(cpu, cpus) {
385 if (entry == qcom_scm_wb[cpu].entry)
387 flags |= qcom_scm_wb[cpu].flag;
390 /* No change in entry function */
394 cmd.addr = cpu_to_le32(virt_to_phys(entry));
395 cmd.flags = cpu_to_le32(flags);
396 ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
397 &cmd, sizeof(cmd), NULL, 0);
399 for_each_cpu(cpu, cpus)
400 qcom_scm_wb[cpu].entry = entry;
407 * qcom_scm_cpu_power_down() - Power down the cpu
408 * @flags - Flags to flush cache
410 * This is an end point to power down cpu. If there was a pending interrupt,
411 * the control would return from this function, otherwise, the cpu jumps to the
412 * warm boot entry point set for this cpu upon reset.
414 void __qcom_scm_cpu_power_down(u32 flags)
416 qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
417 flags & QCOM_SCM_FLUSH_FLAG_MASK);
420 int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
423 __le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
426 ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD,
427 &svc_cmd, sizeof(svc_cmd), &ret_val,
432 return le32_to_cpu(ret_val);
435 int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
436 u32 req_cnt, u32 *resp)
438 if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
441 return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP,
442 req, req_cnt * sizeof(*req), resp, sizeof(*resp));
445 void __qcom_scm_init(void)
449 bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
455 in = cpu_to_le32(peripheral);
456 ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
457 QCOM_SCM_PAS_IS_SUPPORTED_CMD,
461 return ret ? false : !!out;
464 int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
465 dma_addr_t metadata_phys)
474 request.proc = cpu_to_le32(peripheral);
475 request.image_addr = cpu_to_le32(metadata_phys);
477 ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
478 QCOM_SCM_PAS_INIT_IMAGE_CMD,
479 &request, sizeof(request),
480 &scm_ret, sizeof(scm_ret));
482 return ret ? : le32_to_cpu(scm_ret);
485 int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
486 phys_addr_t addr, phys_addr_t size)
496 request.proc = cpu_to_le32(peripheral);
497 request.addr = cpu_to_le32(addr);
498 request.len = cpu_to_le32(size);
500 ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
501 QCOM_SCM_PAS_MEM_SETUP_CMD,
502 &request, sizeof(request),
503 &scm_ret, sizeof(scm_ret));
505 return ret ? : le32_to_cpu(scm_ret);
508 int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
514 in = cpu_to_le32(peripheral);
515 ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
516 QCOM_SCM_PAS_AUTH_AND_RESET_CMD,
520 return ret ? : le32_to_cpu(out);
523 int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
529 in = cpu_to_le32(peripheral);
530 ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
531 QCOM_SCM_PAS_SHUTDOWN_CMD,
535 return ret ? : le32_to_cpu(out);
538 int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
541 __le32 in = cpu_to_le32(reset);
544 ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET,
548 return ret ? : le32_to_cpu(out);
551 int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
553 return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE,
554 enable ? QCOM_SCM_SET_DLOAD_MODE : 0, 0);
557 int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
566 req.state = cpu_to_le32(state);
567 req.id = cpu_to_le32(id);
569 ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
570 &req, sizeof(req), &scm_ret, sizeof(scm_ret));
572 return ret ? : le32_to_cpu(scm_ret);
575 int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
576 size_t mem_sz, phys_addr_t src, size_t src_sz,
577 phys_addr_t dest, size_t dest_sz)
582 int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
588 int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
594 int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
600 int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
605 ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
609 return ret < 0 ? ret : 0;
612 int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
614 return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,