drivers/firmware/trusted_foundations.c

   1 /*
   2  * Trusted Foundations support for ARM CPUs
   3  *
   4  * Copyright (c) 2013, NVIDIA Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20
  21 #include <linux/firmware/trusted_foundations.h>
  22
  23 #include <asm/firmware.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/outercache.h>
  26
  27 #define TF_CACHE_MAINT          0xfffff100
  28
  29 #define TF_CACHE_ENABLE         1
  30 #define TF_CACHE_DISABLE        2
  31
  32 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
  33
  34 #define TF_CPU_PM               0xfffffffc
  35 #define TF_CPU_PM_S3            0xffffffe3
  36 #define TF_CPU_PM_S2            0xffffffe6
  37 #define TF_CPU_PM_S2_NO_MC_CLK  0xffffffe5
  38 #define TF_CPU_PM_S1            0xffffffe4
  39 #define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
  40
  41 static unsigned long cpu_boot_addr;
  42
  43 static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
  44 {
  45         register u32 r0 asm("r0") = type;
  46         register u32 r1 asm("r1") = arg1;
  47         register u32 r2 asm("r2") = arg2;
  48
  49         asm volatile(
  50                 ".arch_extension        sec\n\t"
  51                 "stmfd  sp!, {r4 - r11}\n\t"
  52                 __asmeq("%0", "r0")
  53                 __asmeq("%1", "r1")
  54                 __asmeq("%2", "r2")
  55                 "mov    r3, #0\n\t"
  56                 "mov    r4, #0\n\t"
  57                 "smc    #0\n\t"
  58                 "ldmfd  sp!, {r4 - r11}\n\t"
  59                 :
  60                 : "r" (r0), "r" (r1), "r" (r2)
  61                 : "memory", "r3", "r12", "lr");
  62 }
  63
  64 static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
  65 {
  66         cpu_boot_addr = boot_addr;
  67         tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
  68
  69         return 0;
  70 }
  71
  72 static int tf_prepare_idle(unsigned long mode)
  73 {
  74         switch (mode) {
  75         case TF_PM_MODE_LP0:
  76                 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
  77                 break;
  78
  79         case TF_PM_MODE_LP1:
  80                 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
  81                 break;
  82
  83         case TF_PM_MODE_LP1_NO_MC_CLK:
  84                 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
  85                                cpu_boot_addr);
  86                 break;
  87
  88         case TF_PM_MODE_LP2:
  89                 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
  90                 break;
  91
  92         case TF_PM_MODE_LP2_NOFLUSH_L2:
  93                 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
  94                                cpu_boot_addr);
  95                 break;
  96
  97         default:
  98                 return -EINVAL;
  99         }
 100
 101         return 0;
 102 }
 103
 104 #ifdef CONFIG_CACHE_L2X0
 105 static void tf_cache_write_sec(unsigned long val, unsigned int reg)
 106 {
 107         u32 l2x0_way_mask = 0xff;
 108
 109         switch (reg) {
 110         case L2X0_CTRL:
 111                 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
 112                         l2x0_way_mask = 0xffff;
 113
 114                 if (val == L2X0_CTRL_EN)
 115                         tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
 116                                        l2x0_saved_regs.aux_ctrl);
 117                 else
 118                         tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
 119                                        l2x0_way_mask);
 120                 break;
 121
 122         default:
 123                 break;
 124         }
 125 }
 126
 127 static int tf_init_cache(void)
 128 {
 129         outer_cache.write_sec = tf_cache_write_sec;
 130
 131         return 0;
 132 }
 133 #endif /* CONFIG_CACHE_L2X0 */
 134
 135 static const struct firmware_ops trusted_foundations_ops = {
 136         .set_cpu_boot_addr = tf_set_cpu_boot_addr,
 137         .prepare_idle = tf_prepare_idle,
 138 #ifdef CONFIG_CACHE_L2X0
 139         .l2x0_init = tf_init_cache,
 140 #endif
 141 };
 142
 143 void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
 144 {
 145         /*
 146          * we are not using version information for now since currently
 147          * supported SMCs are compatible with all TF releases
 148          */
 149         register_firmware_ops(&trusted_foundations_ops);
 150 }
 151
 152 void of_register_trusted_foundations(void)
 153 {
 154         struct device_node *node;
 155         struct trusted_foundations_platform_data pdata;
 156         int err;
 157
 158         node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
 159         if (!node)
 160                 return;
 161
 162         err = of_property_read_u32(node, "tlm,version-major",
 163                                    &pdata.version_major);
 164         if (err != 0)
 165                 panic("Trusted Foundation: missing version-major property\n");
 166         err = of_property_read_u32(node, "tlm,version-minor",
 167                                    &pdata.version_minor);
 168         if (err != 0)
 169                 panic("Trusted Foundation: missing version-minor property\n");
 170         register_trusted_foundations(&pdata);
 171 }
 172
 173 bool trusted_foundations_registered(void)
 174 {
 175         return firmware_ops == &trusted_foundations_ops;
 176 }