1 // SPDX-License-Identifier: GPL-2.0
3 * Generic EP93xx GPIO handling
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/slab.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/bitops.h>
20 /* FIXME: this is here for gpio_to_irq() - get rid of this! */
21 #include <linux/gpio.h>
23 #define EP93XX_GPIO_F_INT_STATUS 0x5c
24 #define EP93XX_GPIO_A_INT_STATUS 0xa0
25 #define EP93XX_GPIO_B_INT_STATUS 0xbc
27 /* Maximum value for gpio line identifiers */
28 #define EP93XX_GPIO_LINE_MAX 63
30 /* Maximum value for irq capable line identifiers */
31 #define EP93XX_GPIO_LINE_MAX_IRQ 23
35 struct gpio_chip gc[8];
38 /*************************************************************************
39 * Interrupt handling for EP93xx on-chip GPIOs
40 *************************************************************************/
41 static unsigned char gpio_int_unmasked[3];
42 static unsigned char gpio_int_enabled[3];
43 static unsigned char gpio_int_type1[3];
44 static unsigned char gpio_int_type2[3];
45 static unsigned char gpio_int_debounce[3];
47 /* Port ordering is: A B F */
48 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
49 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
50 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
51 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
52 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
54 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
58 writeb_relaxed(0, epg->base + int_en_register_offset[port]);
60 writeb_relaxed(gpio_int_type2[port],
61 epg->base + int_type2_register_offset[port]);
63 writeb_relaxed(gpio_int_type1[port],
64 epg->base + int_type1_register_offset[port]);
66 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
67 epg->base + int_en_register_offset[port]);
70 static int ep93xx_gpio_port(struct gpio_chip *gc)
72 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
75 while (gc != &epg->gc[port] && port < sizeof(epg->gc))
78 /* This should not happen but is there as a last safeguard */
79 if (gc != &epg->gc[port]) {
80 pr_crit("can't find the GPIO port\n");
87 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
88 unsigned int offset, bool enable)
90 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
91 int port = ep93xx_gpio_port(gc);
92 int port_mask = BIT(offset);
95 gpio_int_debounce[port] |= port_mask;
97 gpio_int_debounce[port] &= ~port_mask;
99 writeb(gpio_int_debounce[port],
100 epg->base + int_debounce_register_offset[port]);
103 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
105 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
106 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
107 struct irq_chip *irqchip = irq_desc_get_chip(desc);
111 chained_irq_enter(irqchip, desc);
113 stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
114 for_each_set_bit(offset, &stat, 8) {
115 int gpio_irq = gpio_to_irq(0) + offset;
116 generic_handle_irq(gpio_irq);
119 stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
120 for_each_set_bit(offset, &stat, 8) {
121 int gpio_irq = gpio_to_irq(8) + offset;
122 generic_handle_irq(gpio_irq);
125 chained_irq_exit(irqchip, desc);
128 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
131 * map discontiguous hw irq range to continuous sw irq range:
133 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
135 struct irq_chip *irqchip = irq_desc_get_chip(desc);
136 unsigned int irq = irq_desc_get_irq(desc);
137 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
138 int gpio_irq = gpio_to_irq(16) + port_f_idx;
140 chained_irq_enter(irqchip, desc);
141 generic_handle_irq(gpio_irq);
142 chained_irq_exit(irqchip, desc);
145 static void ep93xx_gpio_irq_ack(struct irq_data *d)
147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
148 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
149 int port = ep93xx_gpio_port(gc);
150 int port_mask = BIT(d->irq & 7);
152 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
153 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
154 ep93xx_gpio_update_int_params(epg, port);
157 writeb(port_mask, epg->base + eoi_register_offset[port]);
160 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
162 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
163 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
164 int port = ep93xx_gpio_port(gc);
165 int port_mask = BIT(d->irq & 7);
167 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
168 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
170 gpio_int_unmasked[port] &= ~port_mask;
171 ep93xx_gpio_update_int_params(epg, port);
173 writeb(port_mask, epg->base + eoi_register_offset[port]);
176 static void ep93xx_gpio_irq_mask(struct irq_data *d)
178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
179 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
180 int port = ep93xx_gpio_port(gc);
182 gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
183 ep93xx_gpio_update_int_params(epg, port);
186 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
188 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
189 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
190 int port = ep93xx_gpio_port(gc);
192 gpio_int_unmasked[port] |= BIT(d->irq & 7);
193 ep93xx_gpio_update_int_params(epg, port);
197 * gpio_int_type1 controls whether the interrupt is level (0) or
198 * edge (1) triggered, while gpio_int_type2 controls whether it
199 * triggers on low/falling (0) or high/rising (1).
201 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
203 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
204 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
205 int port = ep93xx_gpio_port(gc);
206 int offset = d->irq & 7;
207 int port_mask = BIT(offset);
208 irq_flow_handler_t handler;
210 gc->direction_input(gc, offset);
213 case IRQ_TYPE_EDGE_RISING:
214 gpio_int_type1[port] |= port_mask;
215 gpio_int_type2[port] |= port_mask;
216 handler = handle_edge_irq;
218 case IRQ_TYPE_EDGE_FALLING:
219 gpio_int_type1[port] |= port_mask;
220 gpio_int_type2[port] &= ~port_mask;
221 handler = handle_edge_irq;
223 case IRQ_TYPE_LEVEL_HIGH:
224 gpio_int_type1[port] &= ~port_mask;
225 gpio_int_type2[port] |= port_mask;
226 handler = handle_level_irq;
228 case IRQ_TYPE_LEVEL_LOW:
229 gpio_int_type1[port] &= ~port_mask;
230 gpio_int_type2[port] &= ~port_mask;
231 handler = handle_level_irq;
233 case IRQ_TYPE_EDGE_BOTH:
234 gpio_int_type1[port] |= port_mask;
235 /* set initial polarity based on current input level */
236 if (gc->get(gc, offset))
237 gpio_int_type2[port] &= ~port_mask; /* falling */
239 gpio_int_type2[port] |= port_mask; /* rising */
240 handler = handle_edge_irq;
246 irq_set_handler_locked(d, handler);
248 gpio_int_enabled[port] |= port_mask;
250 ep93xx_gpio_update_int_params(epg, port);
255 static struct irq_chip ep93xx_gpio_irq_chip = {
257 .irq_ack = ep93xx_gpio_irq_ack,
258 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
259 .irq_mask = ep93xx_gpio_irq_mask,
260 .irq_unmask = ep93xx_gpio_irq_unmask,
261 .irq_set_type = ep93xx_gpio_irq_type,
264 static void ep93xx_gpio_init_irq(struct platform_device *pdev,
265 struct ep93xx_gpio *epg)
271 for (gpio_irq = gpio_to_irq(0);
272 gpio_irq < gpio_to_irq(8);
274 irq_set_chip_data(gpio_irq, &epg->gc[0]);
275 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
277 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
280 for (gpio_irq = gpio_to_irq(8);
281 gpio_irq < gpio_to_irq(16);
283 irq_set_chip_data(gpio_irq, &epg->gc[1]);
284 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
286 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
289 for (gpio_irq = gpio_to_irq(16);
290 gpio_irq < gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ);
292 irq_set_chip_data(gpio_irq, &epg->gc[5]);
293 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
295 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
298 irq_set_chained_handler_and_data(platform_get_irq(pdev, 0),
299 ep93xx_gpio_ab_irq_handler,
301 for (i = 1; i <= 8; i++)
302 irq_set_chained_handler_and_data(platform_get_irq(pdev, i),
303 ep93xx_gpio_f_irq_handler,
308 /*************************************************************************
309 * gpiolib interface for EP93xx on-chip GPIOs
310 *************************************************************************/
311 struct ep93xx_gpio_bank {
319 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \
325 .has_irq = _has_irq, \
328 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
329 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */
330 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */
331 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
332 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
333 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
334 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */
335 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
336 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
339 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
340 unsigned long config)
344 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
347 debounce = pinconf_to_config_argument(config);
348 ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
354 * Map GPIO A0..A7 (0..7) to irq 64..71,
355 * B0..B7 (7..15) to irq 72..79, and
356 * F0..F7 (16..24) to irq 80..87.
358 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
360 int gpio = chip->base + offset;
362 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
368 static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
369 struct ep93xx_gpio *epg,
370 struct ep93xx_gpio_bank *bank)
372 void __iomem *data = epg->base + bank->data;
373 void __iomem *dir = epg->base + bank->dir;
376 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
380 gc->label = bank->label;
381 gc->base = bank->base;
384 gc->set_config = ep93xx_gpio_set_config;
385 gc->to_irq = ep93xx_gpio_to_irq;
388 return devm_gpiochip_add_data(dev, gc, epg);
391 static int ep93xx_gpio_probe(struct platform_device *pdev)
393 struct ep93xx_gpio *epg;
394 struct resource *res;
396 struct device *dev = &pdev->dev;
398 epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 epg->base = devm_ioremap_resource(dev, res);
404 if (IS_ERR(epg->base))
405 return PTR_ERR(epg->base);
407 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
408 struct gpio_chip *gc = &epg->gc[i];
409 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
411 if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank))
412 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
416 ep93xx_gpio_init_irq(pdev, epg);
421 static struct platform_driver ep93xx_gpio_driver = {
423 .name = "gpio-ep93xx",
425 .probe = ep93xx_gpio_probe,
428 static int __init ep93xx_gpio_init(void)
430 return platform_driver_register(&ep93xx_gpio_driver);
432 postcore_initcall(ep93xx_gpio_init);
434 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
435 "H Hartley Sweeten <hsweeten@visionengravers.com>");
436 MODULE_DESCRIPTION("EP93XX GPIO driver");
437 MODULE_LICENSE("GPL");